Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp
===================================================================
--- lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -289,6 +289,11 @@
                                      uint64_t Address,
                                      const void *Decoder);
 
+static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
+                                     unsigned Insn,
+                                     uint64_t Address,
+                                     const void *Decoder);
+
 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
@@ -1338,6 +1343,27 @@
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
+                                     unsigned Insn,
+                                     uint64_t Address,
+                                     const void *Decoder) {
+  int Offset = SignExtend32<9>(Insn & 0x1ff);
+  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
+  unsigned Base = fieldFromInstruction(Insn, 16, 5);
+
+  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
+  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+  if (Inst.getOpcode() == Mips::SCE_MM)
+    Inst.addOperand(MCOperand::createReg(Reg));
+
+  Inst.addOperand(MCOperand::createReg(Reg));
+  Inst.addOperand(MCOperand::createReg(Base));
+  Inst.addOperand(MCOperand::createImm(Offset));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
Index: lib/Target/Mips/MicroMipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrFormats.td
+++ lib/Target/Mips/MicroMipsInstrFormats.td
@@ -655,6 +655,20 @@
   let Inst{11-0}  = addr{11-0};
 }
 
+class LLE_FM_MM<bits<4> funct> {
+  bits<5> rt;
+  bits<21> addr;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x18;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = addr{20-16};
+  let Inst{15-12} = funct;
+  let Inst{11-9} = 0x6;
+  let Inst{8-0}  = addr{8-0};
+}
+
 class ADDS_FM_MM<bits<2> fmt, bits<8> funct> : MMArch {
   bits<5> ft;
   bits<5> fs;
Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -251,6 +251,13 @@
   let mayLoad = 1;
 }
 
+class LLEBaseMM<string opstr, RegisterOperand RO> :
+  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
+         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
+  let DecoderMethod = "DecodeMemMMImm9";
+  let mayLoad = 1;
+}
+
 class SCBaseMM<string opstr, RegisterOperand RO> :
   InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
@@ -259,6 +266,14 @@
   let Constraints = "$rt = $dst";
 }
 
+class SCEBaseMM<string opstr, RegisterOperand RO> :
+  InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
+         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
+  let DecoderMethod = "DecodeMemMMImm9";
+  let mayStore = 1;
+  let Constraints = "$rt = $dst";
+}
+
 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
              InstrItinClass Itin = NoItinerary> :
   InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
@@ -854,6 +869,9 @@
   def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
   def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
 
+  def LLE_MM : LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
+  def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
+
   let DecoderMethod = "DecodeCacheOpMM" in {
   def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
                  CACHE_PREF_FM_MM<0x08, 0x6>;
Index: test/MC/Disassembler/Mips/micromips.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips.txt
+++ test/MC/Disassembler/Mips/micromips.txt
@@ -340,3 +340,7 @@
 0x00 0x00 0x57 0x7c # CHECK: ei
 
 0x00 0x0a 0x57 0x7c # CHECK: ei $10
+
+0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4)
+
+0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)
Index: test/MC/Disassembler/Mips/micromips_le.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips_le.txt
+++ test/MC/Disassembler/Mips/micromips_le.txt
@@ -340,3 +340,7 @@
 0x00 0x00 0x7c 0x57 # CHECK: ei
 
 0x0a 0x00 0x7c 0x57 # CHECK: ei $10
+
+0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4)
+
+0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4)
Index: test/MC/Mips/micromips-control-instructions.s
===================================================================
--- test/MC/Mips/micromips-control-instructions.s
+++ test/MC/Mips/micromips-control-instructions.s
@@ -39,6 +39,8 @@
 # CHECK-EL:    tlbr                       # encoding: [0x00,0x00,0x7c,0x13]
 # CHECK-EL:    tlbwi                      # encoding: [0x00,0x00,0x7c,0x23]
 # CHECK-EL:    tlbwr                      # encoding: [0x00,0x00,0x7c,0x33]
+# CHECK-EL:    lle $2, 8($4)              # encoding: [0x44,0x60,0x08,0x6c]
+# CHECK-EL:    sce $2, 8($4)              # encoding: [0x44,0x60,0x08,0xac]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
@@ -72,6 +74,8 @@
 # CHECK-EB:   tlbr                        # encoding: [0x00,0x00,0x13,0x7c]
 # CHECK-EB:   tlbwi                       # encoding: [0x00,0x00,0x23,0x7c]
 # CHECK-EB:   tlbwr                       # encoding: [0x00,0x00,0x33,0x7c]
+# CHECK-EB:   lle $2, 8($4)               # encoding: [0x60,0x44,0x6c,0x08]
+# CHECK-EB:   sce $2, 8($4)               # encoding: [0x60,0x44,0xac,0x08]
 
     sdbbp
     sdbbp 34
@@ -100,3 +104,5 @@
     tlbr
     tlbwi
     tlbwr
+    lle $2, 8($4)
+    sce $2, 8($4)