diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -30,64 +30,27 @@ //===----------------------------------------------------------------------===// let Predicates = [HasStdExtD] in { - -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in -def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd), - (ins GPR:$rs1, simm12:$imm12), - "fld", "$rd, ${imm12}(${rs1})">, - Sched<[WriteFLD64, ReadFMemBase]>; +def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>; // Operands for stores are in the order srcreg, base, offset rather than // reflecting the order these fields are specified in the instruction // encoding. -let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in -def FSD : RVInstS<0b011, OPC_STORE_FP, (outs), - (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12), - "fsd", "$rs2, ${imm12}(${rs1})">, - Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>; - -let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in { -def FMADD_D : FPFMA_rrr_frm; -def FMSUB_D : FPFMA_rrr_frm; -def FNMSUB_D : FPFMA_rrr_frm; -def FNMADD_D : FPFMA_rrr_frm; -} +def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>; def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; -def FADD_D : FPALU_rr_frm<0b0000001, "fadd.d", FPR64>, - Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>; -def FSUB_D : FPALU_rr_frm<0b0000101, "fsub.d", FPR64>, - Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>; -def FMUL_D : FPALU_rr_frm<0b0001001, "fmul.d", FPR64>, - Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>; -def FDIV_D : FPALU_rr_frm<0b0001101, "fdiv.d", FPR64>, - Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>; - -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; def FSQRT_D : FPUnaryOp_r_frm<0b0101101, 0b00000, FPR64, FPR64, "fsqrt.d">, Sched<[WriteFSqrt64, ReadFSqrt64]>; def : FPUnaryOpDynFrmAlias; -let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64], - mayRaiseFPException = 0 in { -def FSGNJ_D : FPALU_rr<0b0010001, 0b000, "fsgnj.d", FPR64>; -def FSGNJN_D : FPALU_rr<0b0010001, 0b001, "fsgnjn.d", FPR64>; -def FSGNJX_D : FPALU_rr<0b0010001, 0b010, "fsgnjx.d", FPR64>; -} - -let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in { -def FMIN_D : FPALU_rr<0b0010101, 0b000, "fmin.d", FPR64>; -def FMAX_D : FPALU_rr<0b0010101, 0b001, "fmax.d", FPR64>; -} - def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, 0b00001, FPR32, FPR64, "fcvt.s.d">, Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>; def : FPUnaryOpDynFrmAlias; @@ -95,12 +58,6 @@ def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b00000, 0b000, FPR64, FPR32, "fcvt.d.s">, Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>; -let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in { -def FEQ_D : FPCmp_rr<0b1010001, 0b010, "feq.d", FPR64>; -def FLT_D : FPCmp_rr<0b1010001, 0b001, "flt.d", FPR64>; -def FLE_D : FPCmp_rr<0b1010001, 0b000, "fle.d", FPR64>; -} - let mayRaiseFPException = 0 in def FCLASS_D : FPUnaryOp_r<0b1110001, 0b00000, 0b001, GPR, FPR64, "fclass.d">, Sched<[WriteFClass64, ReadFClass64]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -59,6 +59,22 @@ // Instruction class templates //===----------------------------------------------------------------------===// +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class FPLoad_r funct3, string opcodestr, RegisterClass rty, + SchedWrite sw> + : RVInstI, + Sched<[sw, ReadFMemBase]>; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +class FPStore_r funct3, string opcodestr, RegisterClass rty, + SchedWrite sw> + : RVInstS, + Sched<[sw, ReadStoreData, ReadFMemBase]>; + let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, UseNamedOperandTable = 1, hasPostISelHook = 1 in class FPFMA_rrr_frm funct2, string opcodestr, @@ -67,6 +83,20 @@ (ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm), opcodestr, "$rd, $rs1, $rs2, $rs3, $frm">; +multiclass FPFMA_rrr_frm_m { + let Predicates = [HasStdExtF], + SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in + def _S : FPFMA_rrr_frm; + + let Predicates = [HasStdExtD], + SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in + def _D : FPFMA_rrr_frm; + + let Predicates = [HasStdExtZfh], + SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in + def _H : FPFMA_rrr_frm; +} + class FPFMADynFrmAlias : InstAlias; +multiclass FPSGNJ_rr funct3, string OpcodeStr> { + defvar funct5 = 0b00100; + let mayRaiseFPException = 0 in { + let Predicates = [HasStdExtF], + SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32] in + def _S : FPALU_rr<{funct5, 0b00}, funct3, OpcodeStr#".s", FPR32>; + + let Predicates = [HasStdExtD], + SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64] in + def _D : FPALU_rr<{funct5, 0b01}, funct3, OpcodeStr#".d", FPR64>; + + let Predicates = [HasStdExtZfh], + SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16] in + def _H : FPALU_rr<{funct5, 0b10}, funct3, OpcodeStr#".h", FPR16>; + } +} + +multiclass FPSGNJ_rr_m { + defm "" : FPSGNJ_rr<0b000, "fsgnj">; + defm N : FPSGNJ_rr<0b001, "fsgnjn">; + defm X : FPSGNJ_rr<0b010, "fsgnjx">; +} + +multiclass FPMinMax_rr_m funct3, string OpcodeStr> { + defvar funct5 = 0b00101; + let Predicates = [HasStdExtF], + SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in + def _S : FPALU_rr<{funct5, 0b00}, funct3, OpcodeStr#".s", FPR32>; + + let Predicates = [HasStdExtD], + SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in + def _D : FPALU_rr<{funct5, 0b01}, funct3, OpcodeStr#".d", FPR64>; + + let Predicates = [HasStdExtZfh], + SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in + def _H : FPALU_rr<{funct5, 0b10}, funct3, OpcodeStr#".h", FPR16>; +} + let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, UseNamedOperandTable = 1, hasPostISelHook = 1 in class FPALU_rr_frm funct7, string opcodestr, RegisterClass rty> @@ -85,6 +153,50 @@ (ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr, "$rd, $rs1, $rs2, $frm">; +multiclass FPALU_rr_frm_m funct5, string opcodestr> { + let Predicates = [HasStdExtF] in + def _S : FPALU_rr_frm<{funct5, 0b00}, opcodestr#".s", FPR32>, + Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; + + let Predicates = [HasStdExtD] in + def _D : FPALU_rr_frm<{funct5, 0b01}, opcodestr#".d", FPR64>, + Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>; + + let Predicates = [HasStdExtZfh] in + def _H : FPALU_rr_frm<{funct5, 0b10}, opcodestr#".h", FPR16>, + Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>; +} + +multiclass FPMUL_rr_frm_m { + defvar funct5 = 0b00010; + let Predicates = [HasStdExtF] in + def _S : FPALU_rr_frm<{funct5, 0b00}, "fmul.s", FPR32>, + Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>; + + let Predicates = [HasStdExtD] in + def _D : FPALU_rr_frm<{funct5, 0b01}, "fmul.d", FPR64>, + Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>; + + let Predicates = [HasStdExtZfh] in + def _H : FPALU_rr_frm<{funct5, 0b10}, "fmul.h", FPR16>, + Sched<[WriteFMul16, ReadFMul16, ReadFMul16]>; +} + +multiclass FPDIV_rr_frm_m { + defvar funct5 = 0b00011; + let Predicates = [HasStdExtF] in + def _S : FPALU_rr_frm<{funct5, 0b00}, "fdiv.s", FPR32>, + Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>; + + let Predicates = [HasStdExtD] in + def _D : FPALU_rr_frm<{funct5, 0b01}, "fdiv.d", FPR64>, + Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>; + + let Predicates = [HasStdExtZfh] in + def _H : FPALU_rr_frm<{funct5, 0b10}, "fdiv.h", FPR16>, + Sched<[WriteFDiv16, ReadFDiv16, ReadFDiv16]>; +} + class FPALUDynFrmAlias : InstAlias; +multiclass FPCmp_rr_m funct3, string opcodestr> { + defvar funct5 = 0b10100; + let Predicates = [HasStdExtF], + SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in + def _S : FPCmp_rr<{funct5, 0b00}, funct3, opcodestr#".s", FPR32>; + + let Predicates = [HasStdExtD], + SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in + def _D : FPCmp_rr<{funct5, 0b01}, funct3, opcodestr#".d", FPR64>; + + let Predicates = [HasStdExtZfh], + SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in + def _H : FPCmp_rr<{funct5, 0b10}, funct3, opcodestr#".h", FPR16>; +} + +//===----------------------------------------------------------------------===// +// Multiclass Instructions +//===----------------------------------------------------------------------===// + +defm FMADD : FPFMA_rrr_frm_m; +defm FMSUB : FPFMA_rrr_frm_m; +defm FNMSUB : FPFMA_rrr_frm_m; +defm FNMADD : FPFMA_rrr_frm_m; + +defm FADD : FPALU_rr_frm_m<0b00000, "fadd">; +defm FSUB : FPALU_rr_frm_m<0b00001, "fsub">; +defm FMUL : FPMUL_rr_frm_m; +defm FDIV : FPDIV_rr_frm_m; + +defm FSGNJ : FPSGNJ_rr_m; + +defm FMIN : FPMinMax_rr_m<0b000, "fmin">; +defm FMAX : FPMinMax_rr_m<0b001, "fmax">; + +defm FEQ : FPCmp_rr_m<0b010, "feq">; +defm FLT : FPCmp_rr_m<0b001, "flt">; +defm FLE : FPCmp_rr_m<0b000, "fle">; + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// let Predicates = [HasStdExtF] in { -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in -def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd), - (ins GPR:$rs1, simm12:$imm12), - "flw", "$rd, ${imm12}(${rs1})">, - Sched<[WriteFLD32, ReadFMemBase]>; +def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>; // Operands for stores are in the order srcreg, base, offset rather than // reflecting the order these fields are specified in the instruction // encoding. -let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in -def FSW : RVInstS<0b010, OPC_STORE_FP, (outs), - (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12), - "fsw", "$rs2, ${imm12}(${rs1})">, - Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>; - -let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in { -def FMADD_S : FPFMA_rrr_frm; -def FMSUB_S : FPFMA_rrr_frm; -def FNMSUB_S : FPFMA_rrr_frm; -def FNMADD_S : FPFMA_rrr_frm; -} +def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>; def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; -def FADD_S : FPALU_rr_frm<0b0000000, "fadd.s", FPR32>, - Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; -def FSUB_S : FPALU_rr_frm<0b0000100, "fsub.s", FPR32>, - Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; -def FMUL_S : FPALU_rr_frm<0b0001000, "fmul.s", FPR32>, - Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>; -def FDIV_S : FPALU_rr_frm<0b0001100, "fdiv.s", FPR32>, - Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>; - -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; def FSQRT_S : FPUnaryOp_r_frm<0b0101100, 0b00000, FPR32, FPR32, "fsqrt.s">, Sched<[WriteFSqrt32, ReadFSqrt32]>; def : FPUnaryOpDynFrmAlias; -let SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32], - mayRaiseFPException = 0 in { -def FSGNJ_S : FPALU_rr<0b0010000, 0b000, "fsgnj.s", FPR32>; -def FSGNJN_S : FPALU_rr<0b0010000, 0b001, "fsgnjn.s", FPR32>; -def FSGNJX_S : FPALU_rr<0b0010000, 0b010, "fsgnjx.s", FPR32>; -} - -let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in { -def FMIN_S : FPALU_rr<0b0010100, 0b000, "fmin.s", FPR32>; -def FMAX_S : FPALU_rr<0b0010100, 0b001, "fmax.s", FPR32>; -} - def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, 0b00000, GPR, FPR32, "fcvt.w.s">, Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>; def : FPUnaryOpDynFrmAlias; @@ -193,12 +307,6 @@ def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">, Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>; -let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in { -def FEQ_S : FPCmp_rr<0b1010000, 0b010, "feq.s", FPR32>; -def FLT_S : FPCmp_rr<0b1010000, 0b001, "flt.s", FPR32>; -def FLE_S : FPCmp_rr<0b1010000, 0b000, "fle.s", FPR32>; -} - let mayRaiseFPException = 0 in def FCLASS_S : FPUnaryOp_r<0b1110000, 0b00000, 0b001, GPR, FPR32, "fclass.s">, Sched<[WriteFClass32, ReadFClass32]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -32,65 +32,29 @@ //===----------------------------------------------------------------------===// let Predicates = [HasStdExtZfhmin] in { -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in -def FLH : RVInstI<0b001, OPC_LOAD_FP, (outs FPR16:$rd), - (ins GPR:$rs1, simm12:$imm12), - "flh", "$rd, ${imm12}(${rs1})">, - Sched<[WriteFLD16, ReadFMemBase]>; +def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>; // Operands for stores are in the order srcreg, base, offset rather than // reflecting the order these fields are specified in the instruction // encoding. -let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in -def FSH : RVInstS<0b001, OPC_STORE_FP, (outs), - (ins FPR16:$rs2, GPR:$rs1, simm12:$imm12), - "fsh", "$rs2, ${imm12}(${rs1})">, - Sched<[WriteFST16, ReadStoreData, ReadFMemBase]>; +def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>; } // Predicates = [HasStdExtZfhmin] let Predicates = [HasStdExtZfh] in { -let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in { -def FMADD_H : FPFMA_rrr_frm; -def FMSUB_H : FPFMA_rrr_frm; -def FNMSUB_H : FPFMA_rrr_frm; -def FNMADD_H : FPFMA_rrr_frm; -} - def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; def : FPFMADynFrmAlias; -def FADD_H : FPALU_rr_frm<0b0000010, "fadd.h", FPR16>, - Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>; -def FSUB_H : FPALU_rr_frm<0b0000110, "fsub.h", FPR16>, - Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>; -def FMUL_H : FPALU_rr_frm<0b0001010, "fmul.h", FPR16>, - Sched<[WriteFMul16, ReadFMul16, ReadFMul16]>; -def FDIV_H : FPALU_rr_frm<0b0001110, "fdiv.h", FPR16>, - Sched<[WriteFDiv16, ReadFDiv16, ReadFDiv16]>; - -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; +def : FPALUDynFrmAlias; def FSQRT_H : FPUnaryOp_r_frm<0b0101110, 0b00000, FPR16, FPR16, "fsqrt.h">, Sched<[WriteFSqrt16, ReadFSqrt16]>; def : FPUnaryOpDynFrmAlias; -let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16], - mayRaiseFPException = 0 in { -def FSGNJ_H : FPALU_rr<0b0010010, 0b000, "fsgnj.h", FPR16>; -def FSGNJN_H : FPALU_rr<0b0010010, 0b001, "fsgnjn.h", FPR16>; -def FSGNJX_H : FPALU_rr<0b0010010, 0b010, "fsgnjx.h", FPR16>; -} - -let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in { -def FMIN_H : FPALU_rr<0b0010110, 0b000, "fmin.h", FPR16>; -def FMAX_H : FPALU_rr<0b0010110, 0b001, "fmax.h", FPR16>; -} - def FCVT_W_H : FPUnaryOp_r_frm<0b1100010, 0b00000, GPR, FPR16, "fcvt.w.h">, Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; def : FPUnaryOpDynFrmAlias; @@ -125,18 +89,10 @@ Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>; } // Predicates = [HasStdExtZfhmin] -let Predicates = [HasStdExtZfh] in { - -let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in { -def FEQ_H : FPCmp_rr<0b1010010, 0b010, "feq.h", FPR16>; -def FLT_H : FPCmp_rr<0b1010010, 0b001, "flt.h", FPR16>; -def FLE_H : FPCmp_rr<0b1010010, 0b000, "fle.h", FPR16>; -} - +let Predicates = [HasStdExtZfh] in let mayRaiseFPException = 0 in def FCLASS_H : FPUnaryOp_r<0b1110010, 0b00000, 0b001, GPR, FPR16, "fclass.h">, Sched<[WriteFClass16, ReadFClass16]>; -} // Predicates = [HasStdExtZfh] let Predicates = [HasStdExtZfh, IsRV64] in { def FCVT_L_H : FPUnaryOp_r_frm<0b1100010, 0b00010, GPR, FPR16, "fcvt.l.h">,