Index: clang/include/clang/Basic/BuiltinsRISCV.def =================================================================== --- clang/include/clang/Basic/BuiltinsRISCV.def +++ clang/include/clang/Basic/BuiltinsRISCV.def @@ -16,46 +16,46 @@ #endif // Zbb extension -TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb") -TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit") +TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb1p0") +TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb1p0,64bit") // Zbc extension -TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc") -TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc") -TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc") +TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc1p0") +TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc1p0") +TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc1p0") // Zbe extension -TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe") +TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe0p93") TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc", - "experimental-zbe,64bit") + "experimental-zbe0p93,64bit") TARGET_BUILTIN(__builtin_riscv_bdecompress_32, "ZiZiZi", "nc", - "experimental-zbe") + "experimental-zbe0p93") TARGET_BUILTIN(__builtin_riscv_bdecompress_64, "WiWiWi", "nc", - "experimental-zbe,64bit") + "experimental-zbe0p93,64bit") // Zbp extension -TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp") -TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit") -TARGET_BUILTIN(__builtin_riscv_gorc_32, "ZiZiZi", "nc", "experimental-zbp") -TARGET_BUILTIN(__builtin_riscv_gorc_64, "WiWiWi", "nc", "experimental-zbp,64bit") -TARGET_BUILTIN(__builtin_riscv_shfl_32, "ZiZiZi", "nc", "experimental-zbp") -TARGET_BUILTIN(__builtin_riscv_shfl_64, "WiWiWi", "nc", "experimental-zbp,64bit") -TARGET_BUILTIN(__builtin_riscv_unshfl_32, "ZiZiZi", "nc", "experimental-zbp") -TARGET_BUILTIN(__builtin_riscv_unshfl_64, "WiWiWi", "nc", "experimental-zbp,64bit") -TARGET_BUILTIN(__builtin_riscv_xperm_n, "LiLiLi", "nc", "experimental-zbp") -TARGET_BUILTIN(__builtin_riscv_xperm_b, "LiLiLi", "nc", "experimental-zbp") -TARGET_BUILTIN(__builtin_riscv_xperm_h, "LiLiLi", "nc", "experimental-zbp") -TARGET_BUILTIN(__builtin_riscv_xperm_w, "WiWiWi", "nc", "experimental-zbp,64bit") +TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp0p93") +TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp0p93,64bit") +TARGET_BUILTIN(__builtin_riscv_gorc_32, "ZiZiZi", "nc", "experimental-zbp0p93") +TARGET_BUILTIN(__builtin_riscv_gorc_64, "WiWiWi", "nc", "experimental-zbp0p93,64bit") +TARGET_BUILTIN(__builtin_riscv_shfl_32, "ZiZiZi", "nc", "experimental-zbp0p93") +TARGET_BUILTIN(__builtin_riscv_shfl_64, "WiWiWi", "nc", "experimental-zbp0p93,64bit") +TARGET_BUILTIN(__builtin_riscv_unshfl_32, "ZiZiZi", "nc", "experimental-zbp0p93") +TARGET_BUILTIN(__builtin_riscv_unshfl_64, "WiWiWi", "nc", "experimental-zbp0p93,64bit") +TARGET_BUILTIN(__builtin_riscv_xperm_n, "LiLiLi", "nc", "experimental-zbp0p93") +TARGET_BUILTIN(__builtin_riscv_xperm_b, "LiLiLi", "nc", "experimental-zbp0p93") +TARGET_BUILTIN(__builtin_riscv_xperm_h, "LiLiLi", "nc", "experimental-zbp0p93") +TARGET_BUILTIN(__builtin_riscv_xperm_w, "WiWiWi", "nc", "experimental-zbp0p93,64bit") // Zbr extension -TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr") -TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr0p93") +TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr0p93") +TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr0p93") +TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr0p93") +TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr0p93") +TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr0p93") +TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr0p93") +TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr0p93") #undef BUILTIN #undef TARGET_BUILTIN Index: clang/lib/Basic/Targets/RISCV.cpp =================================================================== --- clang/lib/Basic/Targets/RISCV.cpp +++ clang/lib/Basic/Targets/RISCV.cpp @@ -150,7 +150,7 @@ auto ExtName = Extension.first; auto ExtInfo = Extension.second; unsigned Version = - (ExtInfo.MajorVersion * 1000000) + (ExtInfo.MinorVersion * 1000); + (ExtInfo.Version.Major * 1000000) + (ExtInfo.Version.Minor * 1000); Builder.defineMacro(Twine("__riscv_", ExtName), Twine(Version)); } @@ -223,8 +223,9 @@ if (Result.hasValue()) return Result.getValue(); - if (ISAInfo->isSupportedExtensionFeature(Feature)) - return ISAInfo->hasExtension(Feature); + if (ISAInfo->isSupportedExtensionFeature(Feature)) { + return ISAInfo->hasExtensionWithVersion(Feature); + } return false; } Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp =================================================================== --- clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -41,8 +41,12 @@ return false; } - (*ISAInfo)->toFeatures( - Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); }); + std::vector ToFeatures; + (*ISAInfo)->toFeatures(ToFeatures); + + for (const auto &Feature : ToFeatures) + Features.push_back(Args.MakeArgString("+" + Feature)); + return true; } Index: clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c =================================================================== --- clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c +++ clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c @@ -1,6 +1,6 @@ // REQUIRES: riscv-registered-target // RUN: not %clang_cc1 -triple riscv64 -fsyntax-only -verify \ -// RUN: -target-feature +experimental-v %s 2>&1 \ +// RUN: -target-feature +experimental-v0p10 %s 2>&1 \ // RUN: | FileCheck %s #include Index: clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c =================================================================== --- clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c +++ clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -emit-llvm -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -emit-llvm -target-feature +experimental-v0p10 \ // RUN: %s -o - \ // RUN: | FileCheck %s Index: clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c =================================================================== --- clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c +++ clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c @@ -1,9 +1,9 @@ // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v0p10 \ // RUN: -O2 -emit-llvm %s -o - \ // RUN: | FileCheck %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 \ // RUN: -O2 -emit-llvm %s -o - \ // RUN: | FileCheck %s Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c =================================================================== --- clang/test/CodeGen/RISCV/riscv-v-debuginfo.c +++ clang/test/CodeGen/RISCV/riscv-v-debuginfo.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 \ // RUN: -dwarf-version=4 -debug-info-kind=limited -emit-llvm -o - %s \ // RUN: | FileCheck --check-prefix=DEBUGINFO %s #include Index: clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp =================================================================== --- clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp +++ clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp @@ -1,5 +1,5 @@ // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-v \ +// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-v0p10 \ // RUN: -O1 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s #include Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb -verify %s -o - +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb1p0 -verify %s -o - int orc_b_64(int a) { return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires 'RV64' extension support to be enabled}} Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb1p0 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV32ZBB // RV32ZBB-LABEL: @orc_b_32( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbc -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbc1p0 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV32ZBC // RV32ZBC-LABEL: @clmul( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbe -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbe0p93 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV32ZBE // RV32ZBE-LABEL: @bcompress( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbp -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbp0p93 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV32ZBP // RV32ZBP-LABEL: @grev( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbr -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbr0p93 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV32ZBR // RV32ZBR-LABEL: @crc32_b( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbb -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbb1p0 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV64ZBB // RV64ZBB-LABEL: @orc_b_32( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbc -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbc1p0 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV64ZBC // RV64ZBC-LABEL: @clmul( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbe -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbe0p93 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV64ZBE // RV64ZBE-LABEL: @bcompressw( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbp -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbp0p93 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV64ZBP // RV64ZBP-LABEL: @grev( Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbr -emit-llvm %s -o - \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbr0p93 -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=RV64ZBR // RV64ZBR-LABEL: @crc32_b( Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -1588,4 +1588,3 @@ vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { return vadd(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -481,5 +481,3 @@ vfloat64m8_t test_vcompress_vm_f64m8 (vbool8_t mask, vfloat64m8_t dest, vfloat64m8_t src, size_t vl) { return vcompress(mask, dest, src, vl); } - - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -166,4 +166,3 @@ vfloat64m8_t test_vfabs_v_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, size_t vl) { return vfabs(mask, maskedoff, op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -166,4 +166,3 @@ vfloat64m8_t test_vfneg_v_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, size_t vl) { return vfneg(mask, maskedoff, op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -544,4 +544,3 @@ vfloat64m4_t test_vget_v_f64m8_f64m4(vfloat64m8_t src, size_t index) { return vget_f64m4(src, 0); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -3825,4 +3825,3 @@ vfloat64m8_t test_vloxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint64m8_t bindex, size_t vl) { return vloxei64(mask, maskedoff, base, bindex, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v \ +// RUN: -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s @@ -28782,4 +28782,3 @@ void test_vloxseg2ei64_v_f64m4_m (vfloat64m4_t *v0, vfloat64m4_t *v1, vbool16_t mask, vfloat64m4_t maskedoff0, vfloat64m4_t maskedoff1, const double *base, vuint64m4_t bindex, size_t vl) { return vloxseg2ei64(v0, v1, mask, maskedoff0, maskedoff1, base, bindex, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c @@ -1,12 +1,12 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c @@ -1,12 +1,12 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v \ +// RUN: -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s @@ -3645,4 +3645,3 @@ void test_vlsseg2e64_v_f64m4_m (vfloat64m4_t *v0, vfloat64m4_t *v1, vbool16_t mask, vfloat64m4_t maskedoff0, vfloat64m4_t maskedoff1, const double *base, ptrdiff_t bstride, size_t vl) { return vlsseg2e64(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v \ +// RUN: -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s @@ -28782,4 +28782,3 @@ void test_vluxseg2ei64_v_f64m4_m (vfloat64m4_t *v0, vfloat64m4_t *v1, vbool16_t mask, vfloat64m4_t maskedoff0, vfloat64m4_t maskedoff1, const double *base, vuint64m4_t bindex, size_t vl) { return vluxseg2ei64(v0, v1, mask, maskedoff0, maskedoff1, base, bindex, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -328,4 +328,3 @@ vbool8_t test_vmfge_vf_f64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) { return vmfge(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -328,4 +328,3 @@ vbool8_t test_vmfgt_vf_f64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) { return vmfgt(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -66,4 +66,3 @@ vbool64_t test_vmmv_m_b64 (vbool64_t op1, size_t vl) { return vmmv(op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -66,4 +66,3 @@ vbool64_t test_vmnot_m_b64 (vbool64_t op1, size_t vl) { return vmnot(op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -1587,4 +1587,3 @@ vbool8_t test_vmsgeu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { return vmsgeu(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -1587,4 +1587,3 @@ vbool8_t test_vmsgtu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { return vmsgtu(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -543,4 +543,3 @@ vuint32m4_t test_vncvt_x_x_w_u32m4_m (vbool8_t mask, vuint32m4_t maskedoff, vuint64m8_t src, size_t vl) { return vncvt_x(mask, maskedoff, src, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -400,4 +400,3 @@ vint64m8_t test_vneg_v_i64m8_m (vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, size_t vl) { return vneg(mask, maskedoff, op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -796,4 +796,3 @@ vuint64m8_t test_vnot_v_u64m8_m (vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, size_t vl) { return vnot(mask, maskedoff, op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vreinterpret.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vreinterpret.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vreinterpret.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vset.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vset.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vset.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v \ +// RUN: -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s @@ -14262,4 +14262,3 @@ void test_vsoxseg2ei64_v_f64m4_m (vbool16_t mask, double *base, vuint64m4_t bindex, vfloat64m4_t v0, vfloat64m4_t v1, size_t vl) { return vsoxseg2ei64(mask, base, bindex, v0, v1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v \ +// RUN: -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s @@ -3624,4 +3624,3 @@ void test_vsseg2e64_v_f64m4_m (vbool16_t mask, double *base, vfloat64m4_t v0, vfloat64m4_t v1, size_t vl) { return vsseg2e64(mask, base, v0, v1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v \ +// RUN: -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s @@ -3624,4 +3624,3 @@ void test_vssseg2e64_v_f64m4_m (vbool16_t mask, double *base, ptrdiff_t bstride, vfloat64m4_t v0, vfloat64m4_t v1, size_t vl) { return vssseg2e64(mask, base, bstride, v0, v1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v \ +// RUN: -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s @@ -14262,4 +14262,3 @@ void test_vsuxseg2ei64_v_f64m4_m (vbool16_t mask, double *base, vuint64m4_t bindex, vfloat64m4_t v0, vfloat64m4_t v1, size_t vl) { return vsuxseg2ei64(mask, base, bindex, v0, v1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -543,4 +543,3 @@ vuint64m8_t test_vwcvtu_x_x_v_u64m8_m (vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t src, size_t vl) { return vwcvtu_x(mask, maskedoff, src, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -1588,4 +1588,3 @@ vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { return vadd_vx_u64m8_m(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vcpop.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vcpop.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vcpop.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \ +// RUN: -target-feature +experimental-zfh -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c @@ -1,12 +1,12 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c @@ -1,12 +1,12 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \ // RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \ // RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \ +// RUN: -target-feature +experimental-zfh -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \ +// RUN: -target-feature +experimental-zfh -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -1587,4 +1587,3 @@ vuint64m8_t test_vmaxu_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { return vmaxu_vx_u64m8_m(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -66,4 +66,3 @@ vbool64_t test_vmmv_m_b64 (vbool64_t op1, size_t vl) { return vmmv_m_b64(op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -66,4 +66,3 @@ vbool64_t test_vmnot_m_b64 (vbool64_t op1, size_t vl) { return vmnot_m_b64(op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -1587,4 +1587,3 @@ vbool8_t test_vmsgeu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { return vmsgeu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -1587,4 +1587,3 @@ vbool8_t test_vmsgtu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { return vmsgtu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -543,4 +543,3 @@ vuint32m4_t test_vncvt_x_x_w_u32m4_m (vbool8_t mask, vuint32m4_t maskedoff, vuint64m8_t src, size_t vl) { return vncvt_x_x_w_u32m4_m(mask, maskedoff, src, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -400,4 +400,3 @@ vint64m8_t test_vneg_v_i64m8_m (vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, size_t vl) { return vneg_v_i64m8_m(mask, maskedoff, op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -796,4 +796,3 @@ vuint64m8_t test_vnot_v_u64m8_m (vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, size_t vl) { return vnot_v_u64m8_m(mask, maskedoff, op1, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm -o - %s \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -emit-llvm -o - %s \ // RUN: | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm -o - %s \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -emit-llvm -o - %s \ // RUN: | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \ +// RUN: -target-feature +experimental-zfh -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -795,4 +795,3 @@ vuint64m8_t test_vsrl_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, size_t shift, size_t vl) { return vsrl_vx_u64m8_m(mask, maskedoff, op1, shift, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \ +// RUN: -target-feature +experimental-zfh -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \ +// RUN: -target-feature +experimental-zfh -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \ +// RUN: -target-feature +experimental-zfh -target-feature +experimental-v0p10 \ // RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ +// RUN: -target-feature +experimental-v0p10 -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include @@ -543,4 +543,3 @@ vuint64m8_t test_vwcvtu_x_x_v_u64m8_m (vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t src, size_t vl) { return vwcvtu_x_x_v_u64m8_m(mask, maskedoff, src, vl); } - Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c =================================================================== --- clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c +++ clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include Index: clang/test/CodeGen/RISCV/rvv_errors.c =================================================================== --- clang/test/CodeGen/RISCV/rvv_errors.c +++ clang/test/CodeGen/RISCV/rvv_errors.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +experimental-v -fsyntax-only -verify +// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +experimental-v0p10 -fsyntax-only -verify void test() { __builtin_rvv_vsetvli(1, 7, 0); // expected-error {{argument value 7 is outside the valid range [0, 3]}} Index: clang/test/Driver/riscv-arch.c =================================================================== --- clang/test/Driver/riscv-arch.c +++ clang/test/Driver/riscv-arch.c @@ -44,29 +44,29 @@ // RUN: %clang -target riscv32-unknown-elf -mabi=ilp32 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-ILP32 %s -// CHECK-ILP32: "-target-feature" "+m" -// CHECK-ILP32-SAME: {{^}} "-target-feature" "+a" -// CHECK-ILP32-SAME: {{^}} "-target-feature" "+f" -// CHECK-ILP32-SAME: {{^}} "-target-feature" "+d" -// CHECK-ILP32-SAME: {{^}} "-target-feature" "+c" +// CHECK-ILP32: "-target-feature" "+m2p0" +// CHECK-ILP32-SAME: {{^}} "-target-feature" "+a2p0" +// CHECK-ILP32-SAME: {{^}} "-target-feature" "+f2p0" +// CHECK-ILP32-SAME: {{^}} "-target-feature" "+d2p0" +// CHECK-ILP32-SAME: {{^}} "-target-feature" "+c2p0" // RUN: %clang -target riscv32-unknown-elf -mabi=ilp32f -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-ILP32F %s -// CHECK-ILP32F: "-target-feature" "+m" -// CHECK-ILP32F-SAME: {{^}} "-target-feature" "+a" -// CHECK-ILP32F-SAME: {{^}} "-target-feature" "+f" -// CHECK-ILP32F-SAME: {{^}} "-target-feature" "+d" -// CHECK-ILP32F-SAME: {{^}} "-target-feature" "+c" +// CHECK-ILP32F: "-target-feature" "+m2p0" +// CHECK-ILP32F-SAME: {{^}} "-target-feature" "+a2p0" +// CHECK-ILP32F-SAME: {{^}} "-target-feature" "+f2p0" +// CHECK-ILP32F-SAME: {{^}} "-target-feature" "+d2p0" +// CHECK-ILP32F-SAME: {{^}} "-target-feature" "+c2p0" // RUN: %clang -target riscv32-unknown-elf -mabi=ilp32d -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-ILP32D %s -// CHECK-ILP32D: "-target-feature" "+m" -// CHECK-ILP32D-SAME: {{^}} "-target-feature" "+a" -// CHECK-ILP32D-SAME: {{^}} "-target-feature" "+f" -// CHECK-ILP32D-SAME: {{^}} "-target-feature" "+d" -// CHECK-ILP32D-SAME: {{^}} "-target-feature" "+c" +// CHECK-ILP32D: "-target-feature" "+m2p0" +// CHECK-ILP32D-SAME: {{^}} "-target-feature" "+a2p0" +// CHECK-ILP32D-SAME: {{^}} "-target-feature" "+f2p0" +// CHECK-ILP32D-SAME: {{^}} "-target-feature" "+d2p0" +// CHECK-ILP32D-SAME: {{^}} "-target-feature" "+c2p0" // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s @@ -114,29 +114,29 @@ // RUN: %clang -target riscv64-unknown-elf -mabi=lp64 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-LP64 %s -// CHECK-LP64: "-target-feature" "+m" -// CHECK-LP64-SAME: {{^}} "-target-feature" "+a" -// CHECK-LP64-SAME: {{^}} "-target-feature" "+f" -// CHECK-LP64-SAME: {{^}} "-target-feature" "+d" -// CHECK-LP64-SAME: {{^}} "-target-feature" "+c" +// CHECK-LP64: "-target-feature" "+m2p0" +// CHECK-LP64-SAME: {{^}} "-target-feature" "+a2p0" +// CHECK-LP64-SAME: {{^}} "-target-feature" "+f2p0" +// CHECK-LP64-SAME: {{^}} "-target-feature" "+d2p0" +// CHECK-LP64-SAME: {{^}} "-target-feature" "+c2p0" // RUN: %clang -target riscv64-unknown-elf -mabi=lp64f -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-LP64F %s -// CHECK-LP64F: "-target-feature" "+m" -// CHECK-LP64F-SAME: {{^}} "-target-feature" "+a" -// CHECK-LP64F-SAME: {{^}} "-target-feature" "+f" -// CHECK-LP64F-SAME: {{^}} "-target-feature" "+d" -// CHECK-LP64F-SAME: {{^}} "-target-feature" "+c" +// CHECK-LP64F: "-target-feature" "+m2p0" +// CHECK-LP64F-SAME: {{^}} "-target-feature" "+a2p0" +// CHECK-LP64F-SAME: {{^}} "-target-feature" "+f2p0" +// CHECK-LP64F-SAME: {{^}} "-target-feature" "+d2p0" +// CHECK-LP64F-SAME: {{^}} "-target-feature" "+c2p0" // RUN: %clang -target riscv64-unknown-elf -mabi=lp64d -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-LP64D %s -// CHECK-LP64D: "-target-feature" "+m" -// CHECK-LP64D-SAME: {{^}} "-target-feature" "+a" -// CHECK-LP64D-SAME: {{^}} "-target-feature" "+f" -// CHECK-LP64D-SAME: {{^}} "-target-feature" "+d" -// CHECK-LP64D-SAME: {{^}} "-target-feature" "+c" +// CHECK-LP64D: "-target-feature" "+m2p0" +// CHECK-LP64D-SAME: {{^}} "-target-feature" "+a2p0" +// CHECK-LP64D-SAME: {{^}} "-target-feature" "+f2p0" +// CHECK-LP64D-SAME: {{^}} "-target-feature" "+d2p0" +// CHECK-LP64D-SAME: {{^}} "-target-feature" "+c2p0" // CHECK-NOT: error: invalid arch name ' @@ -383,12 +383,12 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s -// RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb" +// RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb1p0" // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0_zbp0p93 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s -// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb" -// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp" +// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb1p0" +// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp0p93" // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s @@ -396,7 +396,7 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s -// RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba" +// RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba1p0" // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s @@ -415,7 +415,7 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s -// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v" +// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v0p10" // RUN: %clang -target riscv32-unknown-elf -march=rv32izfh -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH-NOFLAG %s @@ -424,7 +424,7 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s -// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh" +// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh0p1" // RUN: %clang -target riscv32-unknown-elf -march=rv32izfhmin -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFHMIN-NOFLAG %s @@ -433,7 +433,7 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32izfhmin0p1 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFHMIN %s -// RV32-EXPERIMENTAL-ZFHMIN: "-target-feature" "+experimental-zfhmin" +// RV32-EXPERIMENTAL-ZFHMIN: "-target-feature" "+experimental-zfhmin0p1" // RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s @@ -452,7 +452,7 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s -// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo" +// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo0p10" // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s @@ -471,4 +471,4 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s -// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg" +// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg0p10" Index: clang/test/Driver/riscv-cpus.c =================================================================== --- clang/test/Driver/riscv-cpus.c +++ clang/test/Driver/riscv-cpus.c @@ -48,88 +48,88 @@ // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s // MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20" -// MCPU-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c" +// MCPU-SIFIVE-E20: "-target-feature" "+m2p0" "-target-feature" "+c2p0" // MCPU-SIFIVE-E20: "-target-abi" "ilp32" // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e21 | FileCheck -check-prefix=MCPU-SIFIVE-E21 %s // MCPU-SIFIVE-E21: "-nostdsysteminc" "-target-cpu" "sifive-e21" -// MCPU-SIFIVE-E21: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c" +// MCPU-SIFIVE-E21: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+c2p0" // MCPU-SIFIVE-E21: "-target-abi" "ilp32" // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e24 | FileCheck -check-prefix=MCPU-SIFIVE-E24 %s // MCPU-SIFIVE-E24: "-nostdsysteminc" "-target-cpu" "sifive-e24" -// MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" -// MCPU-SIFIVE-E24: "-target-feature" "+c" +// MCPU-SIFIVE-E24: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+f2p0" +// MCPU-SIFIVE-E24: "-target-feature" "+c2p0" // MCPU-SIFIVE-E24: "-target-abi" "ilp32" // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s // MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34" -// MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" -// MCPU-SIFIVE-E34: "-target-feature" "+c" +// MCPU-SIFIVE-E34: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+f2p0" +// MCPU-SIFIVE-E34: "-target-feature" "+c2p0" // MCPU-SIFIVE-E34: "-target-abi" "ilp32" // mcpu with mabi option // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s // MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21" -// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a" -// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m2p0" "-target-feature" "+a2p0" +// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c2p0" "-target-feature" "+64bit" // MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64" // mcpu with mabi option // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51" -// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a" -// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m2p0" "-target-feature" "+a2p0" +// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c2p0" "-target-feature" "+64bit" // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64" // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s // MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54" -// MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" -// MCPU-SIFIVE-S54: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-SIFIVE-S54: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+f2p0" "-target-feature" "+d2p0" +// MCPU-SIFIVE-S54: "-target-feature" "+c2p0" "-target-feature" "+64bit" // MCPU-SIFIVE-S54: "-target-abi" "lp64d" // mcpu with mabi option // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s // MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76" -// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" -// MCPU-SIFIVE-S76: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-SIFIVE-S76: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+f2p0" "-target-feature" "+d2p0" +// MCPU-SIFIVE-S76: "-target-feature" "+c2p0" "-target-feature" "+64bit" // MCPU-SIFIVE-S76: "-target-abi" "lp64d" // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54" -// MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" -// MCPU-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-SIFIVE-U54: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+f2p0" "-target-feature" "+d2p0" +// MCPU-SIFIVE-U54: "-target-feature" "+c2p0" "-target-feature" "+64bit" // MCPU-SIFIVE-U54: "-target-abi" "lp64d" // mcpu with mabi option // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U54 %s // MCPU-ABI-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54" -// MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" -// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-ABI-SIFIVE-U54: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+f2p0" "-target-feature" "+d2p0" +// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c2p0" "-target-feature" "+64bit" // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64" // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck -check-prefix=MCPU-SIFIVE-E76 %s // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76" -// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" -// MCPU-SIFIVE-E76: "-target-feature" "+c" +// MCPU-SIFIVE-E76: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+f2p0" +// MCPU-SIFIVE-E76: "-target-feature" "+c2p0" // MCPU-SIFIVE-E76: "-target-abi" "ilp32" // mcpu with mabi option // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s // MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74" -// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" -// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m2p0" "-target-feature" "+a2p0" "-target-feature" "+f2p0" "-target-feature" "+d2p0" +// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c2p0" "-target-feature" "+64bit" // MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64" // march overwrite mcpu's default march // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s -// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c" +// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m2p0" "-target-feature" "+c2p0" // MCPU-MARCH: "-target-abi" "ilp32" // Check interaction between mcpu and mtune, mtune won't affect arch related @@ -140,10 +140,10 @@ // // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -mtune=sifive-e76 | FileCheck -check-prefix=MTUNE-E31-MCPU-E76 %s // MTUNE-E31-MCPU-E76: "-target-cpu" "sifive-e31" -// MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f" -// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+m" -// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+a" -// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+c" +// MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f2p0" +// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+m2p0" +// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+a2p0" +// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+c2p0" // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76" // Check failed cases Index: clang/test/Driver/riscv-features.c =================================================================== --- clang/test/Driver/riscv-features.c +++ clang/test/Driver/riscv-features.c @@ -26,11 +26,11 @@ // RUN: %clang -target riscv64-linux -### %s -fsyntax-only 2>&1 \ // RUN: | FileCheck %s -check-prefix=DEFAULT-LINUX -// DEFAULT-LINUX: "-target-feature" "+m" -// DEFAULT-LINUX-SAME: "-target-feature" "+a" -// DEFAULT-LINUX-SAME: "-target-feature" "+f" -// DEFAULT-LINUX-SAME: "-target-feature" "+d" -// DEFAULT-LINUX-SAME: "-target-feature" "+c" +// DEFAULT-LINUX: "-target-feature" "+m2p0" +// DEFAULT-LINUX-SAME: "-target-feature" "+a2p0" +// DEFAULT-LINUX-SAME: "-target-feature" "+f2p0" +// DEFAULT-LINUX-SAME: "-target-feature" "+d2p0" +// DEFAULT-LINUX-SAME: "-target-feature" "+c2p0" // RUN: not %clang -cc1 -triple riscv64-unknown-elf -target-feature +e 2>&1 | FileCheck %s -check-prefix=RV64-WITH-E Index: clang/test/Headers/riscv-vector-header.c =================================================================== --- clang/test/Headers/riscv-vector-header.c +++ clang/test/Headers/riscv-vector-header.c @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -triple riscv64 -fsyntax-only \ // RUN: -target-feature +m -target-feature +a -target-feature +f \ -// RUN: -target-feature +d -target-feature +experimental-v %s +// RUN: -target-feature +d -target-feature +experimental-v0p10 %s // expected-no-diagnostics #include Index: clang/test/Sema/riscv-types.c =================================================================== --- clang/test/Sema/riscv-types.c +++ clang/test/Sema/riscv-types.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v0p10 -ast-print %s \ // RUN: | FileCheck %s void bar(void) { Index: clang/utils/TableGen/RISCVVEmitter.cpp =================================================================== --- clang/utils/TableGen/RISCVVEmitter.cpp +++ clang/utils/TableGen/RISCVVEmitter.cpp @@ -1021,7 +1021,7 @@ OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n"; OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, " - "ATTRS, \"experimental-v\")\n"; + "ATTRS, \"experimental-v0p10\")\n"; OS << "#endif\n"; for (auto &Def : Defs) { auto P = Index: llvm/include/llvm/Support/RISCVISAInfo.h =================================================================== --- llvm/include/llvm/Support/RISCVISAInfo.h +++ llvm/include/llvm/Support/RISCVISAInfo.h @@ -19,10 +19,29 @@ #include namespace llvm { + +/// Represents the major and version number components of a RISC-V extension +struct RISCVExtensionVersion { + unsigned Major; + unsigned Minor; + + bool operator==(const RISCVExtensionVersion &Version) const { + return Major == Version.Major && Minor == Version.Minor; + } + + bool operator!=(const RISCVExtensionVersion &Version) const { + return !operator==(Version); + } + + bool operator<(const RISCVExtensionVersion &Version) const { + return (Major < Version.Major) || + (Major == Version.Major && Minor < Version.Minor); + } +}; + struct RISCVExtensionInfo { std::string ExtName; - unsigned MajorVersion; - unsigned MinorVersion; + RISCVExtensionVersion Version; }; class RISCVISAInfo { @@ -47,15 +66,15 @@ /// Parse RISCV ISA info from arch string. static llvm::Expected> parseArchString(StringRef Arch, bool EnableExperimentalExtension, - bool ExperimentalExtensionVersionCheck = true); + bool ExperimentalExtensionVersionCheck = true, + bool IgnoreUnknownExtension = false); /// Parse RISCV ISA info from feature vector. static llvm::Expected> parseFeatures(unsigned XLen, const std::vector &Features); /// Convert RISCV ISA info to a feature vector. - void toFeatures(std::vector &Features, - std::function StrAlloc) const; + void toFeatures(std::vector &Features) const; const OrderedExtensionMap &getExtensions() const { return Exts; }; @@ -63,6 +82,7 @@ unsigned getFLen() const { return FLen; }; bool hasExtension(StringRef Ext) const; + bool hasExtensionWithVersion(StringRef Ext) const; std::string toString() const; static bool isSupportedExtensionFeature(StringRef Ext); Index: llvm/lib/Object/ELFObjectFile.cpp =================================================================== --- llvm/lib/Object/ELFObjectFile.cpp +++ llvm/lib/Object/ELFObjectFile.cpp @@ -26,6 +26,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/RISCVAttributeParser.h" #include "llvm/Support/RISCVAttributes.h" +#include "llvm/Support/RISCVISAInfo.h" #include #include #include @@ -292,7 +293,7 @@ unsigned PlatformFlags = getPlatformFlags(); if (PlatformFlags & ELF::EF_RISCV_RVC) { - Features.AddFeature("c"); + Features.AddFeature("c2p0"); } // Add features according to the ELF attribute section. @@ -306,38 +307,23 @@ Optional Attr = Attributes.getAttributeString(RISCVAttrs::ARCH); if (Attr.hasValue()) { - // The Arch pattern is [rv32|rv64][i|e]version(_[m|a|f|d|c]version)* - // Version string pattern is (major)p(minor). Major and minor are optional. - // For example, a version number could be 2p0, 2, or p92. - StringRef Arch = Attr.getValue(); - if (Arch.consume_front("rv32")) + auto ParseResult = + llvm::RISCVISAInfo::parseArchString(Attr.getValue(), true, true, true); + if (!ParseResult) + return Features; + + auto &ISAInfo = *ParseResult; + + if (ISAInfo->getXLen() == 32) Features.AddFeature("64bit", false); - else if (Arch.consume_front("rv64")) + else if (ISAInfo->getXLen() == 64) Features.AddFeature("64bit"); - while (!Arch.empty()) { - switch (Arch[0]) { - default: - break; // Ignore unexpected features. - case 'i': - Features.AddFeature("e", false); - break; - case 'd': - Features.AddFeature("f"); // D-ext will imply F-ext. - LLVM_FALLTHROUGH; - case 'e': - case 'm': - case 'a': - case 'f': - case 'c': - Features.AddFeature(Arch.take_front()); - break; - } - - // FIXME: Handle version numbers. - Arch = Arch.drop_until([](char c) { return c == '_' || c == '\0'; }); - Arch = Arch.drop_while([](char c) { return c == '_'; }); - } + std::vector ToFeatures; + ISAInfo->toFeatures(ToFeatures); + + for (const auto &Feature : ToFeatures) + Features.AddFeature(Feature); } return Features; Index: llvm/lib/Support/RISCVISAInfo.cpp =================================================================== --- llvm/lib/Support/RISCVISAInfo.cpp +++ llvm/lib/Support/RISCVISAInfo.cpp @@ -22,11 +22,6 @@ using namespace llvm; namespace { -/// Represents the major and version number components of a RISC-V extension -struct RISCVExtensionVersion { - unsigned Major; - unsigned Minor; -}; struct RISCVSupportedExtension { const char *Name; @@ -68,6 +63,11 @@ {"zfh", RISCVExtensionVersion{0, 1}}, }; +static Error getExtensionVersion(StringRef Ext, StringRef In, unsigned &Major, + unsigned &Minor, unsigned &ConsumeLength, + bool EnableExperimentalExtension, + bool ExperimentalExtensionVersionCheck); + static bool stripExperimentalPrefix(StringRef &Ext) { return Ext.consume_front("experimental-"); } @@ -121,8 +121,8 @@ unsigned MinorVersion) { RISCVExtensionInfo Ext; Ext.ExtName = ExtName.str(); - Ext.MajorVersion = MajorVersion; - Ext.MinorVersion = MinorVersion; + Ext.Version.Major = MajorVersion; + Ext.Version.Minor = MinorVersion; Exts[ExtName.str()] = Ext; } @@ -160,12 +160,23 @@ } bool RISCVISAInfo::isSupportedExtensionFeature(StringRef Ext) { - bool IsExperimental = stripExperimentalPrefix(Ext); + stripExperimentalPrefix(Ext); - if (IsExperimental) - return llvm::any_of(SupportedExperimentalExtensions, FindByName(Ext)); - else - return llvm::any_of(SupportedExtensions, FindByName(Ext)); + auto Pos = findFirstNonVersionCharacter(Ext) + 1; + StringRef Name(Ext.substr(0, Pos)); + StringRef Vers(Ext.substr(Pos)); + + unsigned Major, Minor, ConsumeLength; + if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength, + true, false)) { + consumeError(std::move(E)); + return false; + } + + if (!isSupportedExtension(Name, Major, Minor)) + return false; + + return true; } bool RISCVISAInfo::isSupportedExtension(StringRef Ext) { @@ -192,6 +203,18 @@ return Exts.count(Ext.str()) != 0; } +bool RISCVISAInfo::hasExtensionWithVersion(StringRef Ext) const { + stripExperimentalPrefix(Ext); + + auto Pos = findFirstNonVersionCharacter(Ext) + 1; + StringRef Name(Ext.substr(0, Pos)); + + if (!isSupportedExtension(Name)) + return false; + + return Exts.count(Name.str()) != 0; +} + // Get the rank for single-letter extension, lower value meaning higher // priority. static int singleLetterExtensionRank(char Ext) { @@ -274,26 +297,35 @@ return LHS < RHS; } -void RISCVISAInfo::toFeatures( - std::vector &Features, - std::function StrAlloc) const { +static std::string addVersionSuffix(Twine ExtName, unsigned Major, unsigned Minor) { + return (ExtName + Twine(Major) + "p" + Twine(Minor)).str(); +} + +void RISCVISAInfo::toFeatures(std::vector &Features) const { + for (auto &Ext : Exts) { StringRef ExtName = Ext.first; + auto Extension = Ext.second; + unsigned Major = Ext.second.Version.Major; + unsigned Minor = Ext.second.Version.Minor; if (ExtName == "i") continue; if (ExtName == "zvlsseg") { - Features.push_back("+experimental-v"); - Features.push_back("+experimental-zvlsseg"); + Features.push_back(addVersionSuffix("experimental-v", Major, Minor)); + Features.push_back( + addVersionSuffix("experimental-zvlsseg", Major, Minor)); } else if (ExtName == "zvamo") { - Features.push_back("+experimental-v"); - Features.push_back("+experimental-zvlsseg"); - Features.push_back("+experimental-zvamo"); + Features.push_back(addVersionSuffix("experimental-v", Major, Minor)); + Features.push_back( + addVersionSuffix("experimental-zvlsseg", Major, Minor)); + Features.push_back(addVersionSuffix("experimental-zvamo", Major, Minor)); } else if (isExperimentalExtension(ExtName)) { - Features.push_back(StrAlloc("+experimental-" + ExtName)); + Features.push_back( + addVersionSuffix("experimental-" + ExtName, Major, Minor)); } else { - Features.push_back(StrAlloc("+" + ExtName)); + Features.push_back(addVersionSuffix(ExtName, Major, Minor)); } } } @@ -419,11 +451,15 @@ bool Add = ExtName[0] == '+'; ExtName = ExtName.drop_front(1); // Drop '+' or '-' Experimental = stripExperimentalPrefix(ExtName); + auto Pos = findFirstNonVersionCharacter(ExtName) + 1; + StringRef Name(ExtName.substr(0, Pos)); + StringRef Vers(ExtName.substr(Pos)); + auto ExtensionInfos = Experimental ? makeArrayRef(SupportedExperimentalExtensions) : makeArrayRef(SupportedExtensions); auto ExtensionInfoIterator = - llvm::find_if(ExtensionInfos, FindByName(ExtName)); + llvm::find_if(ExtensionInfos, FindByName(Name)); // Not all features is related to ISA extension, like `relax` or // `save-restore`, skip those feature. @@ -431,10 +467,10 @@ continue; if (Add) - ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version.Major, + ISAInfo->addExtension(Name, ExtensionInfoIterator->Version.Major, ExtensionInfoIterator->Version.Minor); else - ISAInfo->Exts.erase(ExtName.str()); + ISAInfo->Exts.erase(Name.str()); } ISAInfo->updateImplication(); @@ -448,7 +484,8 @@ llvm::Expected> RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, - bool ExperimentalExtensionVersionCheck) { + bool ExperimentalExtensionVersionCheck, + bool IgnoreUnknownExtension) { // RISC-V ISA strings must be lowercase. if (llvm::any_of(Arch, isupper)) { return createStringError(errc::invalid_argument, @@ -549,9 +586,10 @@ "standard user-level extension not given in canonical order '%c'", C); } - - return createStringError(errc::invalid_argument, - "invalid standard user-level extension '%c'", C); + if (!IgnoreUnknownExtension) + return createStringError(errc::invalid_argument, + "invalid standard user-level extension '%c'", + C); } // Move to next char to prevent repeated letter. @@ -563,18 +601,22 @@ Next = std::string(std::next(I), E); if (auto E = getExtensionVersion(std::string(1, C), Next, Major, Minor, ConsumeLength, EnableExperimentalExtension, - ExperimentalExtensionVersionCheck)) - return std::move(E); - - // The order is OK, then push it into features. - // TODO: Use version number when setting target features - // Currently LLVM supports only "mafdcbv". - StringRef SupportedStandardExtension = "mafdcbv"; - if (SupportedStandardExtension.find(C) == StringRef::npos) - return createStringError(errc::invalid_argument, - "unsupported standard user-level extension '%c'", - C); - ISAInfo->addExtension(std::string(1, C), Major, Minor); + ExperimentalExtensionVersionCheck)) { + if (IgnoreUnknownExtension) + consumeError(std::move(E)); + else + return std::move(E); + } else { + // The order is OK, then push it into features. + // TODO: Use version number when setting target features + // Currently LLVM supports only "mafdcbv". + StringRef SupportedStandardExtension = "mafdcbv"; + if (SupportedStandardExtension.find(C) == StringRef::npos) + return createStringError( + errc::invalid_argument, + "unsupported standard user-level extension '%c'", C); + ISAInfo->addExtension(std::string(1, C), Major, Minor); + } // Consume full extension name and version, including any optional '_' // between this extension and the next @@ -757,7 +799,7 @@ StringRef ExtName = Ext.first; auto ExtInfo = Ext.second; Arch << LS << ExtName; - Arch << ExtInfo.MajorVersion << "p" << ExtInfo.MinorVersion; + Arch << ExtInfo.Version.Major << "p" << ExtInfo.Version.Minor; } return Arch.str(); Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1990,7 +1990,7 @@ return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); - setFeatureBits(RISCV::FeatureStdExtC, "c"); + setFeatureBits(RISCV::FeatureStdExtC, "c2p0"); return false; } @@ -2002,7 +2002,7 @@ return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); - clearFeatureBits(RISCV::FeatureStdExtC, "c"); + clearFeatureBits(RISCV::FeatureStdExtC, "c2p0"); return false; } @@ -2154,7 +2154,7 @@ auto &ISAInfo = *ParseResult; for (auto Feature : RISCVFeatureKV) - if (ISAInfo->hasExtension(Feature.Key)) + if (ISAInfo->hasExtensionWithVersion(Feature.Key)) setFeatureBits(Feature.Value, Feature.Key); if (ISAInfo->getXLen() == 32) Index: llvm/lib/Target/RISCV/RISCV.td =================================================================== --- llvm/lib/Target/RISCV/RISCV.td +++ llvm/lib/Target/RISCV/RISCV.td @@ -13,28 +13,28 @@ //===----------------------------------------------------------------------===// def FeatureStdExtM - : SubtargetFeature<"m", "HasStdExtM", "true", + : SubtargetFeature<"m2p0", "StdExtM", "RISCVExtensionVersion{2, 0}", "'M' (Integer Multiplication and Division)">; def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, AssemblerPredicate<(all_of FeatureStdExtM), "'M' (Integer Multiplication and Division)">; def FeatureStdExtA - : SubtargetFeature<"a", "HasStdExtA", "true", + : SubtargetFeature<"a2p0", "StdExtA", "RISCVExtensionVersion{2, 0}", "'A' (Atomic Instructions)">; def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, AssemblerPredicate<(all_of FeatureStdExtA), "'A' (Atomic Instructions)">; def FeatureStdExtF - : SubtargetFeature<"f", "HasStdExtF", "true", + : SubtargetFeature<"f2p0", "StdExtF", "RISCVExtensionVersion{2, 0}", "'F' (Single-Precision Floating-Point)">; def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, AssemblerPredicate<(all_of FeatureStdExtF), "'F' (Single-Precision Floating-Point)">; def FeatureStdExtD - : SubtargetFeature<"d", "HasStdExtD", "true", + : SubtargetFeature<"d2p0", "StdExtD", "RISCVExtensionVersion{2, 0}", "'D' (Double-Precision Floating-Point)", [FeatureStdExtF]>; def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, @@ -42,7 +42,7 @@ "'D' (Double-Precision Floating-Point)">; def FeatureStdExtZfhmin - : SubtargetFeature<"experimental-zfhmin", "HasStdExtZfhmin", "true", + : SubtargetFeature<"experimental-zfhmin0p1", "StdExtZfhmin", "RISCVExtensionVersion{0, 1}", "'Zfhmin' (Half-Precision Floating-Point Minimal)", [FeatureStdExtF]>; def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, @@ -50,7 +50,7 @@ "'Zfhmin' (Half-Precision Floating-Point Minimal)">; def FeatureStdExtZfh - : SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true", + : SubtargetFeature<"experimental-zfh0p1", "StdExtZfh", "RISCVExtensionVersion{0, 1}", "'Zfh' (Half-Precision Floating-Point)", [FeatureStdExtZfhmin, FeatureStdExtF]>; def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, @@ -58,14 +58,14 @@ "'Zfh' (Half-Precision Floating-Point)">; def FeatureStdExtC - : SubtargetFeature<"c", "HasStdExtC", "true", + : SubtargetFeature<"c2p0", "StdExtC", "RISCVExtensionVersion{2, 0}", "'C' (Compressed Instructions)">; def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, AssemblerPredicate<(all_of FeatureStdExtC), "'C' (Compressed Instructions)">; def FeatureStdExtZba - : SubtargetFeature<"experimental-zba", "HasStdExtZba", "true", + : SubtargetFeature<"experimental-zba1p0", "StdExtZba", "RISCVExtensionVersion{1, 0}", "'Zba' (Address calculation 'B' Instructions)">; def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, AssemblerPredicate<(all_of FeatureStdExtZba), @@ -73,63 +73,63 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; def FeatureStdExtZbb - : SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true", + : SubtargetFeature<"experimental-zbb1p0", "StdExtZbb", "RISCVExtensionVersion{1, 0}", "'Zbb' (Base 'B' Instructions)">; def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, AssemblerPredicate<(all_of FeatureStdExtZbb), "'Zbb' (Base 'B' Instructions)">; def FeatureStdExtZbc - : SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true", + : SubtargetFeature<"experimental-zbc1p0", "StdExtZbc", "RISCVExtensionVersion{1, 0}", "'Zbc' (Carry-Less 'B' Instructions)">; def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, AssemblerPredicate<(all_of FeatureStdExtZbc), "'Zbc' (Carry-Less 'B' Instructions)">; def FeatureStdExtZbe - : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", + : SubtargetFeature<"experimental-zbe0p93", "StdExtZbe", "RISCVExtensionVersion{0, 93}", "'Zbe' (Extract-Deposit 'B' Instructions)">; def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, AssemblerPredicate<(all_of FeatureStdExtZbe), "'Zbe' (Extract-Deposit 'B' Instructions)">; def FeatureStdExtZbf - : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", + : SubtargetFeature<"experimental-zbf0p93", "StdExtZbf", "RISCVExtensionVersion{0, 93}", "'Zbf' (Bit-Field 'B' Instructions)">; def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, AssemblerPredicate<(all_of FeatureStdExtZbf), "'Zbf' (Bit-Field 'B' Instructions)">; def FeatureStdExtZbm - : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", + : SubtargetFeature<"experimental-zbm0p93", "StdExtZbm", "RISCVExtensionVersion{0, 93}", "'Zbm' (Matrix 'B' Instructions)">; def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, AssemblerPredicate<(all_of FeatureStdExtZbm), "'Zbm' (Matrix 'B' Instructions)">; def FeatureStdExtZbp - : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true", + : SubtargetFeature<"experimental-zbp0p93", "StdExtZbp", "RISCVExtensionVersion{0, 93}", "'Zbp' (Permutation 'B' Instructions)">; def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, AssemblerPredicate<(all_of FeatureStdExtZbp), "'Zbp' (Permutation 'B' Instructions)">; def FeatureStdExtZbr - : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", + : SubtargetFeature<"experimental-zbr0p93", "StdExtZbr", "RISCVExtensionVersion{0, 93}", "'Zbr' (Polynomial Reduction 'B' Instructions)">; def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, AssemblerPredicate<(all_of FeatureStdExtZbr), "'Zbr' (Polynomial Reduction 'B' Instructions)">; def FeatureStdExtZbs - : SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true", + : SubtargetFeature<"experimental-zbs1p0", "StdExtZbs", "RISCVExtensionVersion{1, 0}", "'Zbs' (Single-Bit 'B' Instructions)">; def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, AssemblerPredicate<(all_of FeatureStdExtZbs), "'Zbs' (Single-Bit 'B' Instructions)">; def FeatureStdExtZbt - : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true", + : SubtargetFeature<"experimental-zbt0p93", "StdExtZbt", "RISCVExtensionVersion{0, 93}", "'Zbt' (Ternary 'B' Instructions)">; def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, AssemblerPredicate<(all_of FeatureStdExtZbt), @@ -151,7 +151,7 @@ "RVC Hint Instructions">; def FeatureStdExtV - : SubtargetFeature<"experimental-v", "HasStdExtV", "true", + : SubtargetFeature<"experimental-v0p10", "StdExtV", "RISCVExtensionVersion{0, 10}", "'V' (Vector Instructions)">; def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, AssemblerPredicate<(all_of FeatureStdExtV), @@ -161,7 +161,7 @@ def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">; def FeatureStdExtZvlsseg - : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true", + : SubtargetFeature<"experimental-zvlsseg0p10", "StdExtZvlsseg", "RISCVExtensionVersion{0, 10}", "'Zvlsseg' (Vector segment load/store instructions)", [FeatureStdExtV]>; def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">, @@ -169,7 +169,7 @@ "'Zvlsseg' (Vector segment load/store instructions)">; def FeatureStdExtZvamo - : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true", + : SubtargetFeature<"experimental-zvamo0p10", "StdExtZvamo", "RISCVExtensionVersion{0, 10}", "'Zvamo' (Vector AMO Operations)", [FeatureStdExtV]>; def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">, @@ -189,7 +189,7 @@ def RV64 : HwMode<"+64bit">; def FeatureRV32E - : SubtargetFeature<"e", "IsRV32E", "true", + : SubtargetFeature<"e1p9", "StdExtE", "RISCVExtensionVersion{1, 9}", "Implements RV32E (provides 16 rather than 32 GPRs)">; def IsRV32E : Predicate<"Subtarget->isRV32E()">, AssemblerPredicate<(all_of FeatureRV32E)>; Index: llvm/lib/Target/RISCV/RISCVSubtarget.h =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.h +++ llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -24,6 +24,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DataLayout.h" +#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Target/TargetMachine.h" #define GET_SUBTARGETINFO_HEADER @@ -34,28 +35,28 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { virtual void anchor(); - bool HasStdExtM = false; - bool HasStdExtA = false; - bool HasStdExtF = false; - bool HasStdExtD = false; - bool HasStdExtC = false; - bool HasStdExtZba = false; - bool HasStdExtZbb = false; - bool HasStdExtZbc = false; - bool HasStdExtZbe = false; - bool HasStdExtZbf = false; - bool HasStdExtZbm = false; - bool HasStdExtZbp = false; - bool HasStdExtZbr = false; - bool HasStdExtZbs = false; - bool HasStdExtZbt = false; - bool HasStdExtV = false; - bool HasStdExtZvlsseg = false; - bool HasStdExtZvamo = false; - bool HasStdExtZfhmin = false; - bool HasStdExtZfh = false; + RISCVExtensionVersion StdExtM = {0, 0}; + RISCVExtensionVersion StdExtA = {0, 0}; + RISCVExtensionVersion StdExtF = {0, 0}; + RISCVExtensionVersion StdExtD = {0, 0}; + RISCVExtensionVersion StdExtC = {0, 0}; + RISCVExtensionVersion StdExtZba = {0, 0}; + RISCVExtensionVersion StdExtZbb = {0, 0}; + RISCVExtensionVersion StdExtZbc = {0, 0}; + RISCVExtensionVersion StdExtZbe = {0, 0}; + RISCVExtensionVersion StdExtZbf = {0, 0}; + RISCVExtensionVersion StdExtZbm = {0, 0}; + RISCVExtensionVersion StdExtZbp = {0, 0}; + RISCVExtensionVersion StdExtZbr = {0, 0}; + RISCVExtensionVersion StdExtZbs = {0, 0}; + RISCVExtensionVersion StdExtZbt = {0, 0}; + RISCVExtensionVersion StdExtV = {0, 0}; + RISCVExtensionVersion StdExtZvlsseg = {0, 0}; + RISCVExtensionVersion StdExtZvamo = {0, 0}; + RISCVExtensionVersion StdExtZfhmin = {0, 0}; + RISCVExtensionVersion StdExtZfh = {0, 0}; + RISCVExtensionVersion StdExtE = {0, 0}; bool HasRV64 = false; - bool IsRV32E = false; bool EnableLinkerRelax = false; bool EnableRVCHintInstrs = true; bool EnableSaveRestore = false; @@ -101,28 +102,34 @@ return &TSInfo; } bool enableMachineScheduler() const override { return true; } - bool hasStdExtM() const { return HasStdExtM; } - bool hasStdExtA() const { return HasStdExtA; } - bool hasStdExtF() const { return HasStdExtF; } - bool hasStdExtD() const { return HasStdExtD; } - bool hasStdExtC() const { return HasStdExtC; } - bool hasStdExtZba() const { return HasStdExtZba; } - bool hasStdExtZbb() const { return HasStdExtZbb; } - bool hasStdExtZbc() const { return HasStdExtZbc; } - bool hasStdExtZbe() const { return HasStdExtZbe; } - bool hasStdExtZbf() const { return HasStdExtZbf; } - bool hasStdExtZbm() const { return HasStdExtZbm; } - bool hasStdExtZbp() const { return HasStdExtZbp; } - bool hasStdExtZbr() const { return HasStdExtZbr; } - bool hasStdExtZbs() const { return HasStdExtZbs; } - bool hasStdExtZbt() const { return HasStdExtZbt; } - bool hasStdExtV() const { return HasStdExtV; } - bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } - bool hasStdExtZvamo() const { return HasStdExtZvamo; } - bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } - bool hasStdExtZfh() const { return HasStdExtZfh; } + bool hasStdExtM() const { return StdExtM != RISCVExtensionVersion{0, 0}; } + bool hasStdExtA() const { return StdExtA != RISCVExtensionVersion{0, 0}; } + bool hasStdExtF() const { return StdExtF != RISCVExtensionVersion{0, 0}; } + bool hasStdExtD() const { return StdExtD != RISCVExtensionVersion{0, 0}; } + bool hasStdExtC() const { return StdExtC != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZba() const { return StdExtZba != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbb() const { return StdExtZbb != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbc() const { return StdExtZbc != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbe() const { return StdExtZbe != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbf() const { return StdExtZbf != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbm() const { return StdExtZbm != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbp() const { return StdExtZbp != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbr() const { return StdExtZbr != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbs() const { return StdExtZbs != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZbt() const { return StdExtZbt != RISCVExtensionVersion{0, 0}; } + bool hasStdExtV() const { return StdExtV != RISCVExtensionVersion{0, 0}; } + bool hasStdExtZvlsseg() const { + return StdExtZvlsseg != RISCVExtensionVersion{0, 0}; + } + bool hasStdExtZvamo() const { + return StdExtZvamo != RISCVExtensionVersion{0, 0}; + } + bool hasStdExtZfhmin() const { + return StdExtZfhmin != RISCVExtensionVersion{0, 0}; + } + bool hasStdExtZfh() const { return StdExtZfh != RISCVExtensionVersion{0, 0}; } bool is64Bit() const { return HasRV64; } - bool isRV32E() const { return IsRV32E; } + bool isRV32E() const { return StdExtE != RISCVExtensionVersion{0, 0}; } bool enableLinkerRelax() const { return EnableLinkerRelax; } bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; } bool enableSaveRestore() const { return EnableSaveRestore; } @@ -135,11 +142,21 @@ } // Vector codegen related methods. - bool hasVInstructions() const { return HasStdExtV; } - bool hasVInstructionsI64() const { return HasStdExtV; } - bool hasVInstructionsF16() const { return HasStdExtV && hasStdExtZfh(); } - bool hasVInstructionsF32() const { return HasStdExtV && hasStdExtF(); } - bool hasVInstructionsF64() const { return HasStdExtV && hasStdExtD(); } + bool hasVInstructions() const { + return StdExtV != RISCVExtensionVersion{0, 0}; + } + bool hasVInstructionsI64() const { + return StdExtV != RISCVExtensionVersion{0, 0}; + } + bool hasVInstructionsF16() const { + return StdExtV != RISCVExtensionVersion{0, 0} && hasStdExtZfh(); + } + bool hasVInstructionsF32() const { + return StdExtV != RISCVExtensionVersion{0, 0} && hasStdExtF(); + } + bool hasVInstructionsF64() const { + return StdExtV != RISCVExtensionVersion{0, 0} && hasStdExtD(); + } // F16 and F64 both require F32. bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } unsigned getMaxInterleaveFactor() const { Index: llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll =================================================================== --- llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll +++ llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -cost-model -analyze -mtriple=riscv64 -mattr=+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s 2>%t | FileCheck %s +; RUN: opt -cost-model -analyze -mtriple=riscv64 -mattr=+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s 2>%t | FileCheck %s ; Check that we don't crash querying costs when vectors are not enabled. ; RUN: opt -cost-model -analyze -mtriple=riscv64 Index: llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll =================================================================== --- llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll +++ llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -cost-model -analyze -mtriple=riscv64 -mattr=+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s 2>%t | FileCheck %s +; RUN: opt -cost-model -analyze -mtriple=riscv64 -mattr=+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s 2>%t | FileCheck %s ; Check that we don't crash querying costs when vectors are not enabled. ; RUN: opt -cost-model -analyze -mtriple=riscv64 Index: llvm/test/CodeGen/RISCV/add-before-shl.ll =================================================================== --- llvm/test/CodeGen/RISCV/add-before-shl.ll +++ llvm/test/CodeGen/RISCV/add-before-shl.ll @@ -3,9 +3,9 @@ ; RUN: | FileCheck -check-prefixes=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs --riscv-no-aliases < %s \ ; RUN: | FileCheck -check-prefixes=RV64I %s -; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs --riscv-no-aliases \ +; RUN: llc -mtriple=riscv32 -mattr=+c2p0 -verify-machineinstrs --riscv-no-aliases \ ; RUN: < %s | FileCheck -check-prefixes=RV32C %s -; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \ +; RUN: llc -mtriple=riscv64 -mattr=+c2p0 -verify-machineinstrs --riscv-no-aliases \ ; RUN: < %s | FileCheck -check-prefixes=RV64C %s ; These test that constant adds are not moved after shifts by DAGCombine, Index: llvm/test/CodeGen/RISCV/addcarry.ll =================================================================== --- llvm/test/CodeGen/RISCV/addcarry.ll +++ llvm/test/CodeGen/RISCV/addcarry.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV32 +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RISCV32 ; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY. ; Signed fixed point multiplication eventually expands down to an ADDCARRY. Index: llvm/test/CodeGen/RISCV/addimm-mulimm.ll =================================================================== --- llvm/test/CodeGen/RISCV/addimm-mulimm.ll +++ llvm/test/CodeGen/RISCV/addimm-mulimm.ll @@ -2,9 +2,9 @@ ;; Test that (mul (add x, c1), c2) can be transformed to ;; (add (mul x, c2), c1*c2) if profitable. -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-zba1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IMB %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-zba1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IMB %s define i32 @add_mul_combine_accept_a1(i32 %x) { Index: llvm/test/CodeGen/RISCV/align.ll =================================================================== --- llvm/test/CodeGen/RISCV/align.ll +++ llvm/test/CodeGen/RISCV/align.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+c2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32C define void @foo() { Index: llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll +++ llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s ; This test ensures that the output of the 'lr.w' instruction is sign-extended. Index: llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll +++ llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { Index: llvm/test/CodeGen/RISCV/atomic-fence.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-fence.ll +++ llvm/test/CodeGen/RISCV/atomic-fence.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s define void @fence_acquire() nounwind { Index: llvm/test/CodeGen/RISCV/atomic-load-store.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-load-store.ll +++ llvm/test/CodeGen/RISCV/atomic-load-store.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { Index: llvm/test/CodeGen/RISCV/atomic-rmw.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { Index: llvm/test/CodeGen/RISCV/atomic-signext.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-signext.ll +++ llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s define signext i8 @atomic_load_i8_unordered(i8 *%a) nounwind { Index: llvm/test/CodeGen/RISCV/attributes.ll =================================================================== --- llvm/test/CodeGen/RISCV/attributes.ll +++ llvm/test/CodeGen/RISCV/attributes.ll @@ -1,43 +1,43 @@ ;; Generate ELF attributes from llc. -; RUN: llc -mtriple=riscv32 -mattr=+m %s -o - | FileCheck --check-prefix=RV32M %s -; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefix=RV32A %s -; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s -; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s -; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32V %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s -; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s -; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s -; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s -; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s -; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 %s -o - | FileCheck --check-prefix=RV32M %s +; RUN: llc -mtriple=riscv32 -mattr=+a2p0 %s -o - | FileCheck --check-prefix=RV32A %s +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 %s -o - | FileCheck --check-prefix=RV32F %s +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 %s -o - | FileCheck --check-prefix=RV32D %s +; RUN: llc -mtriple=riscv32 -mattr=+c2p0 %s -o - | FileCheck --check-prefix=RV32C %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10,+experimental-zvlsseg0p10 %s -o - | FileCheck --check-prefix=RV32V %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfhmin0p1 %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 %s -o - | FileCheck --check-prefix=RV32ZFH %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba1p0 %s -o - | FileCheck --check-prefix=RV32ZBA %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb1p0 %s -o - | FileCheck --check-prefix=RV32ZBB %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc1p0 %s -o - | FileCheck --check-prefix=RV32ZBC %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe0p93 %s -o - | FileCheck --check-prefix=RV32ZBE %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf0p93 %s -o - | FileCheck --check-prefix=RV32ZBF %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm0p93 %s -o - | FileCheck --check-prefix=RV32ZBM %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp0p93 %s -o - | FileCheck --check-prefix=RV32ZBP %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr0p93 %s -o - | FileCheck --check-prefix=RV32ZBR %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs1p0 %s -o - | FileCheck --check-prefix=RV32ZBS %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 %s -o - | FileCheck --check-prefix=RV32ZBT %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb1p0,+experimental-zfh0p1,+experimental-zvamo0p10,+experimental-v0p10,+f2p0,+experimental-zvlsseg0p10 %s -o - | FileCheck --check-prefix=RV32COMBINED %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 %s -o - | FileCheck --check-prefix=RV64M %s +; RUN: llc -mtriple=riscv64 -mattr=+a2p0 %s -o - | FileCheck --check-prefix=RV64A %s +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 %s -o - | FileCheck --check-prefix=RV64F %s +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 %s -o - | FileCheck --check-prefix=RV64D %s +; RUN: llc -mtriple=riscv64 -mattr=+c2p0 %s -o - | FileCheck --check-prefix=RV64C %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10,+experimental-zvlsseg0p10 %s -o - | FileCheck --check-prefix=RV64V %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfhmin0p1 %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 %s -o - | FileCheck --check-prefix=RV64ZFH %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba1p0 %s -o - | FileCheck --check-prefix=RV64ZBA %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb1p0 %s -o - | FileCheck --check-prefix=RV64ZBB %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc1p0 %s -o - | FileCheck --check-prefix=RV64ZBC %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe0p93 %s -o - | FileCheck --check-prefix=RV64ZBE %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf0p93 %s -o - | FileCheck --check-prefix=RV64ZBF %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm0p93 %s -o - | FileCheck --check-prefix=RV64ZBM %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp0p93 %s -o - | FileCheck --check-prefix=RV64ZBP %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr0p93 %s -o - | FileCheck --check-prefix=RV64ZBR %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs1p0 %s -o - | FileCheck --check-prefix=RV64ZBS %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt0p93 %s -o - | FileCheck --check-prefix=RV64ZBT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb1p0,+experimental-zfh0p1,+experimental-zvamo0p10,+experimental-v0p10,+f2p0,+experimental-zvlsseg0p10 %s -o - | FileCheck --check-prefix=RV64COMBINED %s ; RV32M: .attribute 5, "rv32i2p0_m2p0" ; RV32A: .attribute 5, "rv32i2p0_a2p0" Index: llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll =================================================================== --- llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll +++ llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=ILP32 -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=LP64 -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=ILP32F -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=LP64F -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=ILP32D -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=LP64D @var = global [32 x float] zeroinitializer Index: llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll =================================================================== --- llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll +++ llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=ILP32 -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=LP64 -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=ILP32D -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=LP64D @var = global [32 x double] zeroinitializer Index: llvm/test/CodeGen/RISCV/callee-saved-gprs.ll =================================================================== --- llvm/test/CodeGen/RISCV/callee-saved-gprs.ll +++ llvm/test/CodeGen/RISCV/callee-saved-gprs.ll @@ -1,21 +1,21 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I-WITH-FP ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I-WITH-FP Index: llvm/test/CodeGen/RISCV/calling-conv-half.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-half.ll +++ llvm/test/CodeGen/RISCV/calling-conv-half.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F -; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zfhmin -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+f,+experimental-zfhmin -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64ZFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+experimental-zfhmin0p1 -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+experimental-zfhmin0p1 -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64ZFHMIN ; Tests passing half arguments and returns without Zfh. ; Covers with and without F extension and ilp32f/ilp64f Index: llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll +++ llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32f \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all \ -; RUN: -mattr=+f -target-abi ilp32f < %s \ +; RUN: -mattr=+f2p0 -target-abi ilp32f < %s \ ; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s ; This file contains tests that should have identical output for the ilp32, Index: llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll +++ llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll @@ -1,19 +1,19 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32f \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32d \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all \ -; RUN: -mattr=+f -target-abi ilp32f < %s \ +; RUN: -mattr=+f2p0 -target-abi ilp32f < %s \ ; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all \ -; RUN: -mattr=+d -target-abi ilp32d < %s \ +; RUN: -mattr=+d2p0 -target-abi ilp32d < %s \ ; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s ; This file contains tests that should have identical output for the ilp32, Index: llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll +++ llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+d \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+d2p0 \ ; RUN: -target-abi ilp32d < %s \ ; RUN: | FileCheck -check-prefix=RV32-ILP32D %s Index: llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll +++ llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f2p0 \ ; RUN: -target-abi ilp32f < %s \ ; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+d \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+d2p0 \ ; RUN: -target-abi ilp32d < %s \ ; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s Index: llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll +++ llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s Index: llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll +++ llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64d \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s Index: llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll +++ llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IF ; Exercises the ILP32 calling convention code in the case that f32 is a legal Index: llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll =================================================================== --- llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll +++ llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64 %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi=lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64LP64F %s define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) { Index: llvm/test/CodeGen/RISCV/codemodel-lowering.ll =================================================================== --- llvm/test/CodeGen/RISCV/codemodel-lowering.ll +++ llvm/test/CodeGen/RISCV/codemodel-lowering.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -code-model=small -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -code-model=small -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I-SMALL -; RUN: llc -mtriple=riscv32 -mattr=+f -code-model=medium -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -code-model=medium -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM ; Check lowering of globals Index: llvm/test/CodeGen/RISCV/compress-float.ll =================================================================== --- llvm/test/CodeGen/RISCV/compress-float.ll +++ llvm/test/CodeGen/RISCV/compress-float.ll @@ -5,23 +5,23 @@ ; ; RUN: cat %s > %t.tgtattr ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c2p0,+f2p0,+d2p0 -filetype=obj \ ; RUN: -disable-block-placement < %t.tgtattr \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c2p0,+f2p0,+d2p0 -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IFDC %s ; ; RUN: cat %s > %t.fnattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f,+d" }' >> %t.fnattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+c2p0,+f2p0,+d2p0" }' >> %t.fnattr ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -filetype=obj \ ; RUN: -disable-block-placement < %t.fnattr \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c2p0,+f2p0,+d2p0 -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IFDC %s ; ; RUN: cat %s > %t.mixedattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+f,+d" }' >> %t.mixedattr -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c -filetype=obj \ +; RUN: echo 'attributes #0 = { nounwind "target-features"="+f2p0,+d2p0" }' >> %t.mixedattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c2p0 -filetype=obj \ ; RUN: -disable-block-placement < %t.mixedattr \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c2p0,+f2p0,+d2p0 -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IFDC %s ; This acts as a basic correctness check for the codegen instruction compression Index: llvm/test/CodeGen/RISCV/compress-inline-asm.ll =================================================================== --- llvm/test/CodeGen/RISCV/compress-inline-asm.ll +++ llvm/test/CodeGen/RISCV/compress-inline-asm.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s\ -; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\ +; RUN: llc -mtriple=riscv32 -mattr=+c2p0 -filetype=obj < %s\ +; RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d -M no-aliases -\ ; RUN: | FileCheck -check-prefix=CHECK %s @ext = external global i32 @@ -12,4 +12,3 @@ %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1) ret i32 %2 } - Index: llvm/test/CodeGen/RISCV/compress.ll =================================================================== --- llvm/test/CodeGen/RISCV/compress.ll +++ llvm/test/CodeGen/RISCV/compress.ll @@ -3,16 +3,16 @@ ; ; RUN: cat %s > %t.tgtattr ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr -; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj \ +; RUN: llc -mtriple=riscv32 -mattr=+c2p0 -filetype=obj \ ; RUN: -disable-block-placement < %t.tgtattr \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c2p0 -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IC %s ; ; RUN: cat %s > %t.fnattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+c" }' >> %t.fnattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+c2p0" }' >> %t.fnattr ; RUN: llc -mtriple=riscv32 -filetype=obj \ ; RUN: -disable-block-placement < %t.fnattr \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c2p0 -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IC %s ; This acts as a basic correctness check for the codegen instruction compression Index: llvm/test/CodeGen/RISCV/copysign-casts.ll =================================================================== --- llvm/test/CodeGen/RISCV/copysign-casts.ll +++ llvm/test/CodeGen/RISCV/copysign-casts.ll @@ -3,20 +3,20 @@ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f2p0 \ ; RUN: -target-abi ilp32f < %s | FileCheck %s -check-prefix=RV32IF -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f2p0 -mattr=+d2p0 \ ; RUN: -target-abi ilp32d < %s | FileCheck %s -check-prefix=RV32IFD -; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \ +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f2p0 -mattr=+d2p0 \ ; RUN: -target-abi lp64d < %s | FileCheck %s -check-prefix=RV64IFD -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \ -; RUN: -mattr=+experimental-zfh -target-abi ilp32f < %s \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f2p0 \ +; RUN: -mattr=+experimental-zfh0p1 -target-abi ilp32f < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IFZFH -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \ -; RUN: -mattr=+experimental-zfh -target-abi ilp32d < %s \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f2p0 -mattr=+d2p0 \ +; RUN: -mattr=+experimental-zfh0p1 -target-abi ilp32d < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IFDZFH -; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \ -; RUN: -mattr=+experimental-zfh -target-abi lp64d < %s \ +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f2p0 -mattr=+d2p0 \ +; RUN: -mattr=+experimental-zfh0p1 -target-abi lp64d < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IFDZFH ; Test fcopysign scenarios where the sign argument is casted to the type of the Index: llvm/test/CodeGen/RISCV/div.ll =================================================================== --- llvm/test/CodeGen/RISCV/div.ll +++ llvm/test/CodeGen/RISCV/div.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IM %s define i32 @udiv(i32 %a, i32 %b) nounwind { Index: llvm/test/CodeGen/RISCV/double-arith-strict.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-arith-strict.ll +++ llvm/test/CodeGen/RISCV/double-arith-strict.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IFD %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/double-arith.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-arith.ll +++ llvm/test/CodeGen/RISCV/double-arith.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll +++ llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s ; ; This file tests cases where simple floating point operations can be Index: llvm/test/CodeGen/RISCV/double-br-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-br-fcmp.ll +++ llvm/test/CodeGen/RISCV/double-br-fcmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s declare void @abort() Index: llvm/test/CodeGen/RISCV/double-calling-conv.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-calling-conv.ll +++ llvm/test/CodeGen/RISCV/double-calling-conv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s ; Basic correctness checks for calling convention lowering for RV32D. This can Index: llvm/test/CodeGen/RISCV/double-convert.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-convert.ll +++ llvm/test/CodeGen/RISCV/double-convert.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/double-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-fcmp.ll +++ llvm/test/CodeGen/RISCV/double-fcmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/double-frem.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-frem.ll +++ llvm/test/CodeGen/RISCV/double-frem.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s define double @frem_f64(double %a, double %b) nounwind { Index: llvm/test/CodeGen/RISCV/double-imm.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-imm.ll +++ llvm/test/CodeGen/RISCV/double-imm.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s define double @double_imm() nounwind { Index: llvm/test/CodeGen/RISCV/double-intrinsics.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-intrinsics.ll +++ llvm/test/CodeGen/RISCV/double-intrinsics.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d2p0 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IFD %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d2p0 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IFD %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/double-isnan.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-isnan.ll +++ llvm/test/CodeGen/RISCV/double-isnan.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32d -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64d -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV64IFD %s define zeroext i1 @double_is_nan(double %a) nounwind { Index: llvm/test/CodeGen/RISCV/double-mem.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-mem.ll +++ llvm/test/CodeGen/RISCV/double-mem.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s define dso_local double @fld(double *%a) nounwind { Index: llvm/test/CodeGen/RISCV/double-previous-failure.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s define double @test(double %a) nounwind { Index: llvm/test/CodeGen/RISCV/double-select-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-select-fcmp.ll +++ llvm/test/CodeGen/RISCV/double-select-fcmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s define double @select_fcmp_false(double %a, double %b) nounwind { Index: llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll +++ llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s define double @func(double %d, i32 %n) nounwind { Index: llvm/test/CodeGen/RISCV/fastcc-float.ll =================================================================== --- llvm/test/CodeGen/RISCV/fastcc-float.ll +++ llvm/test/CodeGen/RISCV/fastcc-float.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s define fastcc float @callee(<32 x float> %A) nounwind { Index: llvm/test/CodeGen/RISCV/float-arith-strict.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-arith-strict.ll +++ llvm/test/CodeGen/RISCV/float-arith-strict.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IF %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/float-arith.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-arith.ll +++ llvm/test/CodeGen/RISCV/float-arith.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll +++ llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32F %s -; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32FD %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64F %s -; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64FD %s ; These functions perform extra work to ensure that `%a3` starts in a Index: llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll +++ llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s ; This file tests cases where simple floating point operations can be Index: llvm/test/CodeGen/RISCV/float-br-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-br-fcmp.ll +++ llvm/test/CodeGen/RISCV/float-br-fcmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s declare void @abort() Index: llvm/test/CodeGen/RISCV/float-convert.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-convert.ll +++ llvm/test/CodeGen/RISCV/float-convert.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/float-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-fcmp.ll +++ llvm/test/CodeGen/RISCV/float-fcmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/float-frem.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-frem.ll +++ llvm/test/CodeGen/RISCV/float-frem.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/float-imm.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-imm.ll +++ llvm/test/CodeGen/RISCV/float-imm.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s ; TODO: constant pool shouldn't be necessary for RV64IF. Index: llvm/test/CodeGen/RISCV/float-intrinsics.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-intrinsics.ll +++ llvm/test/CodeGen/RISCV/float-intrinsics.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f2p0 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IF %s -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d2p0 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IF %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f2p0 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d2p0 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/float-isnan.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-isnan.ll +++ llvm/test/CodeGen/RISCV/float-isnan.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32f -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV64IF %s define zeroext i1 @float_is_nan(float %a) nounwind { Index: llvm/test/CodeGen/RISCV/float-mem.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-mem.ll +++ llvm/test/CodeGen/RISCV/float-mem.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s define dso_local float @flw(float *%a) nounwind { Index: llvm/test/CodeGen/RISCV/float-select-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-select-fcmp.ll +++ llvm/test/CodeGen/RISCV/float-select-fcmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s define float @select_fcmp_false(float %a, float %b) nounwind { Index: llvm/test/CodeGen/RISCV/fp-imm.ll =================================================================== --- llvm/test/CodeGen/RISCV/fp-imm.ll +++ llvm/test/CodeGen/RISCV/fp-imm.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f2p0 < %s \ ; RUN: | FileCheck --check-prefix=RV32F %s -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f2p0,+d2p0 < %s \ ; RUN: | FileCheck --check-prefix=RV32D %s -; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f2p0 < %s \ ; RUN: | FileCheck --check-prefix=RV64F %s -; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f2p0,+d2p0 < %s \ ; RUN: | FileCheck --check-prefix=RV64D %s define float @f32_positive_zero(float *%pf) nounwind { Index: llvm/test/CodeGen/RISCV/fp16-promote.ll =================================================================== --- llvm/test/CodeGen/RISCV/fp16-promote.ll +++ llvm/test/CodeGen/RISCV/fp16-promote.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr +d -target-abi ilp32d < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr +d2p0 -target-abi ilp32d < %s | FileCheck %s define void @test_load_store(half* %p, half* %q) nounwind { ; CHECK-LABEL: test_load_store: Index: llvm/test/CodeGen/RISCV/fpclamptosat.ll =================================================================== --- llvm/test/CodeGen/RISCV/fpclamptosat.ll +++ llvm/test/CodeGen/RISCV/fpclamptosat.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64,RV64IF %s -; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32,RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64,RV64IFD %s ; i32 saturate Index: llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll =================================================================== --- llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll +++ llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s ; i32 saturate Index: llvm/test/CodeGen/RISCV/fpenv.ll =================================================================== --- llvm/test/CodeGen/RISCV/fpenv.ll +++ llvm/test/CodeGen/RISCV/fpenv.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s define i32 @func_01() { ; RV32IF-LABEL: func_01: Index: llvm/test/CodeGen/RISCV/frm-dependency.ll =================================================================== --- llvm/test/CodeGen/RISCV/frm-dependency.ll +++ llvm/test/CodeGen/RISCV/frm-dependency.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f,+d -stop-after=finalize-isel < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+d2p0 -stop-after=finalize-isel < %s \ ; RUN: | FileCheck -check-prefixes=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f,+d -stop-after=finalize-isel < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0 -stop-after=finalize-isel < %s \ ; RUN: | FileCheck -check-prefixes=RV64IF %s ; Make sure an implicit FRM dependency is added to instructions with dynamic Index: llvm/test/CodeGen/RISCV/ghccc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/ghccc-rv32.ll +++ llvm/test/CodeGen/RISCV/ghccc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f,+d < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+d2p0 < %s | FileCheck %s ; Check the GHC call convention works (rv32) Index: llvm/test/CodeGen/RISCV/ghccc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/ghccc-rv64.ll +++ llvm/test/CodeGen/RISCV/ghccc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+f,+d < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0 < %s | FileCheck %s ; Check the GHC call convention works (rv64) Index: llvm/test/CodeGen/RISCV/half-arith-strict.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-arith-strict.ll +++ llvm/test/CodeGen/RISCV/half-arith-strict.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -disable-strictnode-mutation -target-abi ilp32f < %s \ ; RUN: | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -disable-strictnode-mutation -target-abi lp64f < %s \ ; RUN: | FileCheck -check-prefix=RV64IZFH %s Index: llvm/test/CodeGen/RISCV/half-arith.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-arith.ll +++ llvm/test/CodeGen/RISCV/half-arith.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll +++ llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV32IZFH %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV64IZFH %s ; This file tests cases where simple floating point operations can be Index: llvm/test/CodeGen/RISCV/half-br-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-br-fcmp.ll +++ llvm/test/CodeGen/RISCV/half-br-fcmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s declare void @abort() Index: llvm/test/CodeGen/RISCV/half-convert.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-convert.ll +++ llvm/test/CodeGen/RISCV/half-convert.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV32I %s Index: llvm/test/CodeGen/RISCV/half-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-fcmp.ll +++ llvm/test/CodeGen/RISCV/half-fcmp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck -check-prefix=RV64I %s define i32 @fcmp_false(half %a, half %b) nounwind { Index: llvm/test/CodeGen/RISCV/half-frem.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-frem.ll +++ llvm/test/CodeGen/RISCV/half-frem.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s \ ; RUN: | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s \ ; RUN: | FileCheck -check-prefix=RV64IZFH %s Index: llvm/test/CodeGen/RISCV/half-imm.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-imm.ll +++ llvm/test/CodeGen/RISCV/half-imm.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s ; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh Index: llvm/test/CodeGen/RISCV/half-intrinsics.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-intrinsics.ll +++ llvm/test/CodeGen/RISCV/half-intrinsics.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+experimental-zfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs -target-abi ilp32f | \ ; RUN: FileCheck -check-prefix=RV32IZFH %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+experimental-zfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs -target-abi lp64f | \ ; RUN: FileCheck -check-prefix=RV64IZFH %s -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ -; RUN: -mattr=+experimental-zfh -verify-machineinstrs -target-abi ilp32d | \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d2p0 \ +; RUN: -mattr=+experimental-zfh0p1 -verify-machineinstrs -target-abi ilp32d | \ ; RUN: FileCheck -check-prefix=RV32IDZFH %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ -; RUN: -mattr=+experimental-zfh -verify-machineinstrs -target-abi lp64d | \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d2p0 \ +; RUN: -mattr=+experimental-zfh0p1 -verify-machineinstrs -target-abi lp64d | \ ; RUN: FileCheck -check-prefix=RV64IDZFH %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ ; RUN: -verify-machineinstrs | \ Index: llvm/test/CodeGen/RISCV/half-isnan.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-isnan.ll +++ llvm/test/CodeGen/RISCV/half-isnan.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s define zeroext i1 @half_is_nan(half %a) nounwind { Index: llvm/test/CodeGen/RISCV/half-mem.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-mem.ll +++ llvm/test/CodeGen/RISCV/half-mem.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s define half @flh(half *%a) nounwind { Index: llvm/test/CodeGen/RISCV/half-select-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-select-fcmp.ll +++ llvm/test/CodeGen/RISCV/half-select-fcmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s define half @select_fcmp_false(half %a, half %b) nounwind { Index: llvm/test/CodeGen/RISCV/imm.ll =================================================================== --- llvm/test/CodeGen/RISCV/imm.ll +++ llvm/test/CodeGen/RISCV/imm.ll @@ -3,9 +3,9 @@ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba1p0 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBA -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs1p0 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBS ; Materializing constants Index: llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll +++ llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll @@ -2,21 +2,21 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32ID %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64ID %s Index: llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll +++ llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+d2p0 -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0 -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s ; These test that we can use both the architectural names (x*) and the ABI names Index: llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll +++ llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32F %s -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64F %s @gd = external global double Index: llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll +++ llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s ; These test that we can use both the architectural names (x*) and the ABI names Index: llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll +++ llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32F %s -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64F %s @gf = external global float Index: llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll =================================================================== --- llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll +++ llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32 -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f2p0 -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-F -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f2p0,+d2p0 -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-FD ; ; The test case check that the function call in an interrupt handler will use Index: llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll =================================================================== --- llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll +++ llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32 -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f2p0 -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32IF -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f2p0,+d2p0 -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32IFD ; ; TODO: Add RV64 tests when we can lower global addresses. Index: llvm/test/CodeGen/RISCV/interrupt-attr.ll =================================================================== --- llvm/test/CodeGen/RISCV/interrupt-attr.ll +++ llvm/test/CodeGen/RISCV/interrupt-attr.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32 -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f2p0 -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-F -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f2p0,+d2p0 -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-FD ; ; RUN: llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64 -; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f -o - %s \ +; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f2p0 -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-F -; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f,+d -o - %s \ +; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f2p0,+d2p0 -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD ; Index: llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll =================================================================== --- llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll +++ llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \ +; RUN: not --crash llc -mtriple=riscv64 -mattr=+e1p9 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64E %s ; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target Index: llvm/test/CodeGen/RISCV/module-target-abi.ll =================================================================== --- llvm/test/CodeGen/RISCV/module-target-abi.ll +++ llvm/test/CodeGen/RISCV/module-target-abi.ll @@ -19,6 +19,6 @@ ret float %conv } -attributes #0 = { "target-features"="+f"} +attributes #0 = { "target-features"="+f2p0"} !llvm.module.flags = !{!0} !0 = !{i32 1, !"target-abi", !"ilp32"} Index: llvm/test/CodeGen/RISCV/module-target-abi2.ll =================================================================== --- llvm/test/CodeGen/RISCV/module-target-abi2.ll +++ llvm/test/CodeGen/RISCV/module-target-abi2.ll @@ -22,6 +22,6 @@ ret float %conv } -attributes #0 = { "target-features"="+f"} +attributes #0 = { "target-features"="+f2p0"} !llvm.module.flags = !{!0} !0 = !{i32 1, !"target-abi", !"ilp32f"} Index: llvm/test/CodeGen/RISCV/mul.ll =================================================================== --- llvm/test/CodeGen/RISCV/mul.ll +++ llvm/test/CodeGen/RISCV/mul.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IM %s define signext i32 @square(i32 %a) nounwind { @@ -1548,4 +1548,3 @@ %5 = trunc i128 %4 to i64 ret i64 %5 } - Index: llvm/test/CodeGen/RISCV/neg-abs.ll =================================================================== --- llvm/test/CodeGen/RISCV/neg-abs.ll +++ llvm/test/CodeGen/RISCV/neg-abs.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV32IBT ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV64IBT declare i32 @llvm.abs.i32(i32, i1 immarg) @@ -160,4 +160,3 @@ %3 = select i1 %1, i64 %x, i64 %2 ret i64 %3 } - Index: llvm/test/CodeGen/RISCV/option-nopic.ll =================================================================== --- llvm/test/CodeGen/RISCV/option-nopic.ll +++ llvm/test/CodeGen/RISCV/option-nopic.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=riscv32 -filetype=obj --relocation-model=pic < %s\ -; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\ +; RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d -M no-aliases -\ ; RUN: | FileCheck -check-prefix=CHECK %s ; This test demonstrates that .option nopic has no effect on codegen when Index: llvm/test/CodeGen/RISCV/option-norvc.ll =================================================================== --- llvm/test/CodeGen/RISCV/option-norvc.ll +++ llvm/test/CodeGen/RISCV/option-norvc.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s\ -; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\ +; RUN: llc -mtriple=riscv32 -mattr=+c2p0 -filetype=obj < %s\ +; RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d -M no-aliases -\ ; RUN: | FileCheck -check-prefix=CHECK %s ; This test demonstrates that .option norvc has no effect on codegen when Index: llvm/test/CodeGen/RISCV/option-pic.ll =================================================================== --- llvm/test/CodeGen/RISCV/option-pic.ll +++ llvm/test/CodeGen/RISCV/option-pic.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=riscv32 -filetype=obj < %s\ -; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\ +; RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d -M no-aliases -\ ; RUN: | FileCheck -check-prefix=CHECK %s ; This test demonstrates that .option pic has no effect on codegen when Index: llvm/test/CodeGen/RISCV/option-rvc.ll =================================================================== --- llvm/test/CodeGen/RISCV/option-rvc.ll +++ llvm/test/CodeGen/RISCV/option-rvc.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=riscv32 -filetype=obj < %s\ -; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\ +; RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d -M no-aliases -\ ; RUN: | FileCheck -check-prefix=CHECK %s ; This test demonstrates that .option norvc has no effect on codegen when Index: llvm/test/CodeGen/RISCV/patchable-function-entry.ll =================================================================== --- llvm/test/CodeGen/RISCV/patchable-function-entry.ll +++ llvm/test/CodeGen/RISCV/patchable-function-entry.ll @@ -1,8 +1,8 @@ ;; Test the function attribute "patchable-function-entry". ; RUN: llc -mtriple=riscv32 --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,NORVC ; RUN: llc -mtriple=riscv64 --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,NORVC -; RUN: llc -mtriple=riscv32 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC -; RUN: llc -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC +; RUN: llc -mtriple=riscv32 -mattr=+c2p0 --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC +; RUN: llc -mtriple=riscv64 -mattr=+c2p0 --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC define void @f0() "patchable-function-entry"="0" { ; CHECK-LABEL: f0: Index: llvm/test/CodeGen/RISCV/pr51206.ll =================================================================== --- llvm/test/CodeGen/RISCV/pr51206.ll +++ llvm/test/CodeGen/RISCV/pr51206.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -;RUN: llc < %s -mtriple=riscv64-unknown-linux-gnu -mattr=+m | FileCheck %s +;RUN: llc < %s -mtriple=riscv64-unknown-linux-gnu -mattr=+m2p0 | FileCheck %s ; This test used to cause an infinite loop. Index: llvm/test/CodeGen/RISCV/rem.ll =================================================================== --- llvm/test/CodeGen/RISCV/rem.ll +++ llvm/test/CodeGen/RISCV/rem.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IM %s define i32 @urem(i32 %a, i32 %b) nounwind { Index: llvm/test/CodeGen/RISCV/rv32e.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32e.ll +++ llvm/test/CodeGen/RISCV/rv32e.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=riscv32 -mattr=+e < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=riscv32 -mattr=+e1p9 < %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Codegen not yet implemented for RV32E Index: llvm/test/CodeGen/RISCV/rv32zba.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zba.ll +++ llvm/test/CodeGen/RISCV/rv32zba.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-zba1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBA define signext i16 @sh1add(i64 %0, i16* %1) { Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll +++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBB declare i32 @llvm.riscv.orc.b.i32(i32) Index: llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll +++ llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBB -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBP define i32 @andn_i32(i32 %a, i32 %b) nounwind { Index: llvm/test/CodeGen/RISCV/rv32zbb.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbb.ll +++ llvm/test/CodeGen/RISCV/rv32zbb.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBB declare i32 @llvm.ctlz.i32(i32, i1) Index: llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll +++ llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBC declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b) Index: llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll +++ llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBE declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) Index: llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll +++ llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBP declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) Index: llvm/test/CodeGen/RISCV/rv32zbp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbp.ll +++ llvm/test/CodeGen/RISCV/rv32zbp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBP define i32 @gorc1_i32(i32 %a) nounwind { Index: llvm/test/CodeGen/RISCV/rv32zbr.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbr.ll +++ llvm/test/CodeGen/RISCV/rv32zbr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBR declare i32 @llvm.riscv.crc32.b.i32(i32) Index: llvm/test/CodeGen/RISCV/rv32zbs.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbs.ll +++ llvm/test/CodeGen/RISCV/rv32zbs.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBS define i32 @bclr_i32(i32 %a, i32 %b) nounwind { Index: llvm/test/CodeGen/RISCV/rv32zbt.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv32zbt.ll +++ llvm/test/CodeGen/RISCV/rv32zbt.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBT define i32 @cmix_i32(i32 %a, i32 %b, i32 %c) nounwind { Index: llvm/test/CodeGen/RISCV/rv64d-double-convert.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64d-double-convert.ll +++ llvm/test/CodeGen/RISCV/rv64d-double-convert.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ID ; This file exhaustively checks double<->i32 conversions. In general, Index: llvm/test/CodeGen/RISCV/rv64f-float-convert.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64f-float-convert.ll +++ llvm/test/CodeGen/RISCV/rv64f-float-convert.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IF ; This file exhaustively checks float<->i32 conversions. In general, Index: llvm/test/CodeGen/RISCV/rv64f-half-convert.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64f-half-convert.ll +++ llvm/test/CodeGen/RISCV/rv64f-half-convert.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFH ; This file exhaustively checks half<->i32 conversions. In general, Index: llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll +++ llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s | FileCheck %s ; This test has multiple opportunities for SimplifyDemandedBits after type ; legalization. There are 2 opportunities on the chain feeding the LHS of the Index: llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll +++ llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s ; The test cases check that we use the si versions of the conversions from @@ -55,4 +55,3 @@ %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") ret i32 %conv } - Index: llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll +++ llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV64,RV64I -; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+experimental-zba < %s \ +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+experimental-zba1p0 < %s \ ; RUN: | FileCheck %s -check-prefixes=RV64,RV64ZBA ; The patterns for the 'W' suffixed RV64I instructions have the potential of Index: llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll +++ llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s | FileCheck %s define signext i32 @addw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind { ; CHECK-LABEL: addw: Index: llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll +++ llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IM ; The patterns for the 'W' suffixed RV64M instructions have the potential of Index: llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll +++ llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s | FileCheck %s define signext i32 @mulw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind { ; CHECK-LABEL: mulw: Index: llvm/test/CodeGen/RISCV/rv64zba.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zba.ll +++ llvm/test/CodeGen/RISCV/rv64zba.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-zba1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBA define i64 @slliuw(i64 %a) nounwind { Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll +++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBB declare i32 @llvm.riscv.orc.b.i32(i32) Index: llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll +++ llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBB -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBP define signext i32 @andn_i32(i32 signext %a, i32 signext %b) nounwind { Index: llvm/test/CodeGen/RISCV/rv64zbb.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbb.ll +++ llvm/test/CodeGen/RISCV/rv64zbb.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBB declare i32 @llvm.ctlz.i32(i32, i1) Index: llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll +++ llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBC declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b) Index: llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll +++ llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBE declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) Index: llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll +++ llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBP declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) Index: llvm/test/CodeGen/RISCV/rv64zbp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbp.ll +++ llvm/test/CodeGen/RISCV/rv64zbp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBP define signext i32 @gorc1_i32(i32 signext %a) nounwind { Index: llvm/test/CodeGen/RISCV/rv64zbr.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbr.ll +++ llvm/test/CodeGen/RISCV/rv64zbr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBR declare i64 @llvm.riscv.crc32.b.i64(i64) Index: llvm/test/CodeGen/RISCV/rv64zbs.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbs.ll +++ llvm/test/CodeGen/RISCV/rv64zbs.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs1p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBS define signext i32 @bclr_i32(i32 signext %a, i32 signext %b) nounwind { Index: llvm/test/CodeGen/RISCV/rv64zbt.ll =================================================================== --- llvm/test/CodeGen/RISCV/rv64zbt.ll +++ llvm/test/CodeGen/RISCV/rv64zbt.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBT define signext i32 @cmix_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare @llvm.abs.nxv1i16(, i1) Index: llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll +++ llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -O2 < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IV define @access_fixed_object(i64 *%val) { Index: llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir +++ llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=riscv64 -mattr=+experimental-v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s +# RUN: llc -march=riscv64 -mattr=+experimental-v0p10 -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s --- | define void @add_scalable_offset( Index: llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll +++ llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s define void @lmul1() nounwind { Index: llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @bitreverse_nxv1i8( %va) { ; CHECK-LABEL: bitreverse_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @bswap_nxv1i16( %va) { ; CHECK-LABEL: bswap_nxv1i16: Index: llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll +++ llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 define fastcc @ret_nxv4i8(* %p) { Index: llvm/test/CodeGen/RISCV/rvv/calling-conv.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/calling-conv.ll +++ llvm/test/CodeGen/RISCV/rvv/calling-conv.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 < %s | FileCheck %s --check-prefix=RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 < %s | FileCheck %s --check-prefix=RV64 ; Check that we correctly scale the split part indirect offsets by VSCALE. define @callee_scalable_vector_split_indirect( %x, %y) { Index: llvm/test/CodeGen/RISCV/rvv/combine-sats.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/combine-sats.ll +++ llvm/test/CodeGen/RISCV/rvv/combine-sats.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 ; fold (add (umax X, C), -C) --> (usubsat X, C) Index: llvm/test/CodeGen/RISCV/rvv/combine-splats.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/combine-splats.ll +++ llvm/test/CodeGen/RISCV/rvv/combine-splats.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 < %s | FileCheck %s ; fold (and (or x, C), D) -> D if (C & D) == D Index: llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s define void @combine_fp_zero_stores_crash(float* %ptr) { ; CHECK-LABEL: combine_fp_zero_stores_crash: Index: llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll +++ llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" target triple = "riscv64-unknown-unknown-elf" Index: llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir +++ llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=riscv64 -mattr=+experimental-v -run-pass=simple-register-coalescing %s -o - 2>&1 | FileCheck %s +# RUN: llc -march=riscv64 -mattr=+experimental-v0p10 -run-pass=simple-register-coalescing %s -o - 2>&1 | FileCheck %s # This test used to crash in the register coalescer when the target would # return the out-of-bounds CommuteAnyOperandIndex for one of its commutable Index: llvm/test/CodeGen/RISCV/rvv/constant-folding.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/constant-folding.ll +++ llvm/test/CodeGen/RISCV/rvv/constant-folding.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 ; These tests check that the scalable-vector version of this series of Index: llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D define @ctlz_nxv1i8( %va) { ; RV32I-LABEL: ctlz_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @ctpop_nxv1i8( %va) { ; CHECK-LABEL: ctpop_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D define @cttz_nxv1i8( %va) { ; RV32I-LABEL: cttz_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir +++ llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir @@ -1,6 +1,6 @@ -# RUN: llc -march=riscv64 -mattr=+experimental-v -o %t0 -filetype=obj \ +# RUN: llc -march=riscv64 -mattr=+experimental-v0p10 -o %t0 -filetype=obj \ # RUN: -start-before=prologepilog %s -# RUN: llc -march=riscv64 -mattr=+experimental-v -o %t1 -filetype=obj \ +# RUN: llc -march=riscv64 -mattr=+experimental-v0p10 -o %t1 -filetype=obj \ # RUN: -frame-pointer=all -start-before=prologepilog %s # RUN: llvm-dwarfdump --name="value0" %t0 | FileCheck %s --check-prefix=CHECK0-PLUS # RUN: llvm-dwarfdump --name="value1" %t0 | FileCheck %s --check-prefix=CHECK1-PLUS Index: llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir +++ llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v -run-pass=prologepilog -o - \ +# RUN: llc -mtriple riscv64 -mattr=+m2p0,+experimental-v0p10 -run-pass=prologepilog -o - \ # RUN: -verify-machineinstrs %s | FileCheck %s --- | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" Index: llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll +++ llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @sextload_nxv1i1_nxv1i8(* %x) { ; CHECK-LABEL: sextload_nxv1i1_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll +++ llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv32 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv64 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @extract_nxv8i32_nxv4i32_0( %vec) { ; CHECK-LABEL: extract_nxv8i32_nxv4i32_0: Index: llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define half @extractelt_nxv1f16_0( %v) { @@ -481,4 +481,3 @@ %r = extractelement %v, i32 %idx ret double %r } - Index: llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define half @extractelt_nxv1f16_0( %v) { @@ -481,4 +481,3 @@ %r = extractelement %v, i32 %idx ret double %r } - Index: llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll +++ llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define i1 @extractelt_nxv1i1(* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_nxv1i1: Index: llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define signext i8 @extractelt_nxv1i8_0( %v) { @@ -741,4 +741,3 @@ %r = extractelement %v, i32 %idx ret i64 %r } - Index: llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define signext i8 @extractelt_nxv1i8_0( %v) { @@ -705,4 +705,3 @@ %r = extractelement %v, i32 %idx ret i64 %r } - Index: llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @ceil_nxv1f16( %x) { Index: llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @floor_nxv1f16( %x) { Index: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-negative.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-negative.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-negative.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt %s -S -riscv-gather-scatter-lowering -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=256 | FileCheck %s +; RUN: opt %s -S -riscv-gather-scatter-lowering -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=256 | FileCheck %s ; This contains negative tests for the strided load/store recognition in ; RISCVGatherScatterLowering.cpp Index: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll @@ -1,5 +1,5 @@ -; RUN: opt %s -S -riscv-gather-scatter-lowering -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=256 | FileCheck %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=256 | FileCheck %s --check-prefix=CHECK-ASM +; RUN: opt %s -S -riscv-gather-scatter-lowering -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=256 | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=256 | FileCheck %s --check-prefix=CHECK-ASM %struct.foo = type { i32, i32, i32, i32 } Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 define void @abs_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: abs_v16i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=256 < %s | FileCheck %s --check-prefix=VLEN256 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=512 < %s | FileCheck %s --check-prefix=VLEN512 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=1024 < %s | FileCheck %s --check-prefix=VLEN1024 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=256 < %s | FileCheck %s --check-prefix=VLEN256 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=512 < %s | FileCheck %s --check-prefix=VLEN512 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=1024 < %s | FileCheck %s --check-prefix=VLEN1024 define <512 x i8> @bitcast_1024B(<256 x i16> %a, <512 x i8> %b) { ; VLEN256-LABEL: bitcast_1024B: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -riscv-v-vector-bits-min=128 -target-abi=ilp32d < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -riscv-v-vector-bits-min=128 -target-abi=lp64d < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -riscv-v-vector-bits-min=128 \ ; RUN: -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d < %s \ ; RUN: | FileCheck %s --check-prefixes=ELEN32,RV32ELEN32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: -riscv-v-vector-bits-min=128 \ ; RUN: -riscv-v-fixed-length-vector-elen-max=32 -target-abi=lp64d < %s \ ; RUN: | FileCheck %s --check-prefixes=ELEN32,RV64ELEN32 Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 define void @bitreverse_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-LABEL: bitreverse_v8i16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-LABEL: bswap_v8i16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 define fastcc <4 x i8> @ret_v4i8(<4 x i8>* %p) { ; CHECK-LABEL: ret_v4i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define <4 x i8> @ret_v4i8(<4 x i8>* %p) { ; CHECK-LABEL: ret_v4i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32I -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64I -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32D -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64D -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32I +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64I +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32D +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64D +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8-RV64 define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) nounwind { ; LMULMAX2-RV32-LABEL: ctlz_v16i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64 define void @ctpop_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: ctpop_v16i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32I -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64I -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32D -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64D -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32I +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64I +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32D +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64D +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8-RV64 define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) nounwind { ; LMULMAX2-RV32-LABEL: cttz_v16i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; Test that limiting ELEN, scalarizes elements larger than that and disables ; some fractional LMULs. Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -# RUN: llc -mtriple riscv64 -mattr=+experimental-v -start-before=prologepilog -o - \ +# RUN: llc -mtriple riscv64 -mattr=+experimental-v0p10 -start-before=prologepilog -o - \ # RUN: -verify-machineinstrs %s | FileCheck %s --- | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 define <2 x i16> @sextload_v2i1_v2i16(<2 x i1>* %x) { ; CHECK-LABEL: sextload_v2i1_v2i16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define i1 @extractelt_v1i1(<1 x i8>* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_v1i1: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define void @extract_v2i8_v4i8_0(<4 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: extract_v2i8_v4i8_0: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define i8 @extractelt_v16i8(<16 x i8>* %x) nounwind { ; CHECK-LABEL: extractelt_v16i8: @@ -596,4 +596,3 @@ store i64 %b, i64* %p ret void } - Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV32-FP -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV64-FP +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV32-FP +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV64-FP define i16 @bitcast_v1f16_i16(<1 x half> %a) { ; CHECK-LABEL: bitcast_v1f16_i16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; Tests that a floating-point build_vector doesn't try and generate a VID ; instruction Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define void @fpext_v2f16_v2f32(<2 x half>* %x, <2 x float>* %y) { ; CHECK-LABEL: fpext_v2f16_v2f32: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s define void @fcmp_oeq_vv_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oeq_vv_v8f16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define <4 x half> @shuffle_v4f16(<4 x half> %x, <4 x half> %y) { ; CHECK-LABEL: shuffle_v4f16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define void @splat_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: splat_v8f16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define void @gather_const_v8f16(<8 x half>* %x) { ; CHECK-LABEL: gather_const_v8f16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64 define void @fadd_v8f16(<8 x half>* %x, <8 x half>* %y) { ; CHECK-LABEL: fadd_v8f16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define void @fp2si_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) { ; CHECK-LABEL: fp2si_v2f32_v2i32: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define void @si2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) { ; CHECK-LABEL: si2fp_v2i32_v2f32: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 define <1 x i1> @insertelt_v1i1(<1 x i1> %x, i1 %elt) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 - -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 + +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define @insert_nxv8i32_v2i32_0( %vec, <2 x i32>* %svp) { ; CHECK-LABEL: insert_nxv8i32_v2i32_0: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; FIXME: This codegen needs to be improved. These tests previously asserted ; type legalizing the i64 type on RV32. Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @buildvec_vid_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: buildvec_vid_v16i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define void @sext_v4i8_v4i32(<4 x i8>* %x, <4 x i32>* %z) { ; CHECK-LABEL: sext_v4i8_v4i32: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s ; FIXME: We use exclusively byte types here because the MVT we use for the ; stores is calculated assuming byte elements. We need to deal with mismatched Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define <4 x i16> @shuffle_v4i16(<4 x i16> %x, <4 x i16> %y) { ; CHECK-LABEL: shuffle_v4i16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8-RV32 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV32 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8-RV64 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV64 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8-RV32 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV32 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8-RV64 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV64 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64 define void @splat_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: splat_v16i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX4 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define void @gather_const_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: gather_const_v16i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2,LMULMAX2-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2,LMULMAX2-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1,LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1,LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2,LMULMAX2-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2,LMULMAX2-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1,LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1,LMULMAX1-RV64 define void @add_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: add_v16i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX1 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX4 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX4 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX8 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX8 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX1 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX4 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX4 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX8 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX8 define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) { ; CHECK-LABEL: buildvec_mask_nonconst_v1i1: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) { ; CHECK-LABEL: load_store_v1i1: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s define void @and_v8i1(<8 x i1>* %x, <8 x i1>* %y) { ; CHECK-LABEL: and_v8i1: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 define void @splat_ones_v1i1(<1 x i1>* %x) { ; CHECK-LABEL: splat_ones_v1i1: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 declare <1 x i8> @llvm.masked.gather.v1i8.v1p0i8(<1 x i8*>, i32, <1 x i1>, <1 x i8>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @masked_load_v1f16(<1 x half>* %a, <1 x half>* %m_ptr, <1 x half>* %res_ptr) nounwind { ; CHECK-LABEL: masked_load_v1f16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @masked_load_v1i8(<1 x i8>* %a, <1 x i8>* %m_ptr, <1 x i8>* %res_ptr) nounwind { ; CHECK-LABEL: masked_load_v1i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 declare void @llvm.masked.scatter.v1i8.v1p0i8(<1 x i8>, <1 x i8*>, i32, <1 x i1>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half>* %m_ptr) nounwind { ; CHECK-LABEL: masked_store_v1f16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @masked_store_v1i8(<1 x i8>* %val_ptr, <1 x i8>* %a, <1 x i8>* %m_ptr) nounwind { ; CHECK-LABEL: masked_store_v1i8: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare half @llvm.vp.reduce.fadd.v2f16(half, <2 x half>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare i8 @llvm.vp.reduce.add.v2i8(i8, <2 x i8>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s declare i1 @llvm.vp.reduce.and.v1i1(i1, <1 x i1>, <1 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <2 x half> @select_v2f16(i1 zeroext %c, <2 x half> %a, <2 x half> %b) { Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 define <1 x i1> @select_v1i1(i1 zeroext %c, <1 x i1> %a, <1 x i1> %b) { Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 declare <2 x i8> @llvm.experimental.stepvector.v2i8() Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 declare <2 x i8> @llvm.experimental.stepvector.v2i8() Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-v \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zbb1p0,+experimental-v0p10 \ ; RUN: -riscv-v-vector-bits-min=128 | FileCheck %s ; This test loads to values and stores them in reversed order. This previously Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV64 define <4 x i32> @load_v4i32_align1(<4 x i32>* %ptr) { Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.add.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.and.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.sdiv.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.udiv.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fadd.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fdiv.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fmul.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fdiv.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fsub.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fsub.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.mul.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK define <8 x i8> @vnsra_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) { ; CHECK-LABEL: vnsra_v8i16_v8i8_scalar: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.or.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 declare <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x i8> @llvm.vp.load.v2i8.p0v2i8(<2 x i8>*, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 declare void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8>, <2 x i8*>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.vp.store.v2i8.p0v2i8(<2 x i8>, <2 x i8>*, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.srem.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.urem.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <2 x i8> @llvm.vp.sub.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x i8> @llvm.vp.select.v2i8(<2 x i1>, <2 x i8>, <2 x i8>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s define void @vselect_vv_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) { ; CHECK-LABEL: vselect_vv_v8i32: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.shl.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.ashr.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.lshr.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.sub.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK define <2 x i16> @vwmacc_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) { ; CHECK-LABEL: vwmacc_v2i16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK define <2 x i16> @vwmaccu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) { ; CHECK-LABEL: vwmaccu_v2i16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define <2 x i16> @vwmul_v2i16(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: vwmul_v2i16: Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK define <2 x i16> @vwmulu_v2i16(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: vwmulu_v2i16: @@ -891,4 +891,3 @@ %g = mul <2 x i64> %e, %f ret <2 x i64> %g } - Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare <8 x i7> @llvm.vp.xor.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32) Index: llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll +++ llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s ; This test makes sure we match FrameIndex into the base address. ; Done as a MIR test because eliminateFrameIndex will likely turn it Index: llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @trunc_nxv1f16( %x) { Index: llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir +++ llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=riscv64 -mattr=+experimental-v -o - %s \ +# RUN: llc -march=riscv64 -mattr=+experimental-v0p10 -o - %s \ # RUN: -stop-after=prologepilog | FileCheck %s --- | Index: llvm/test/CodeGen/RISCV/rvv/inline-asm.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/inline-asm.ll +++ llvm/test/CodeGen/RISCV/rvv/inline-asm.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 < %s \ ; RUN: --verify-machineinstrs | FileCheck %s define @test_1xi1( %in, %in2) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll +++ llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv32 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv64 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @insert_nxv8i32_nxv4i32_0( %vec, %subvec) { ; CHECK-LABEL: insert_nxv8i32_nxv4i32_0: Index: llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @insertelt_nxv1f16_0( %v, half %elt) { @@ -526,4 +526,3 @@ %r = insertelement %v, double %elt, i32 %idx ret %r } - Index: llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @insertelt_nxv1f16_0( %v, half %elt) { @@ -526,4 +526,3 @@ %r = insertelement %v, double %elt, i32 %idx ret %r } - Index: llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll +++ llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @insertelt_nxv1i1( %x, i1 %elt) { ; CHECK-LABEL: insertelt_nxv1i1: Index: llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @insertelt_nxv1i8_0( %v, i8 signext %elt) { Index: llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @insertelt_nxv1i8_0( %v, i8 signext %elt) { @@ -775,4 +775,3 @@ %r = insertelement %v, i64 %elt, i32 %idx ret %r } - Index: llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll +++ llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -O1 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=1024 < %s | FileCheck %s --check-prefix=RV64-1024 -; RUN: llc -mtriple=riscv64 -O1 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=2048 < %s | FileCheck %s --check-prefix=RV64-2048 +; RUN: llc -mtriple=riscv64 -O1 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=1024 < %s | FileCheck %s --check-prefix=RV64-1024 +; RUN: llc -mtriple=riscv64 -O1 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=2048 < %s | FileCheck %s --check-prefix=RV64-2048 define void @interleave256(<256 x i16>* %agg.result, <128 x i16>* %0, <128 x i16>* %1) { ; RV64-1024-LABEL: interleave256: Index: llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir +++ llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -# RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v -start-before=prologepilog -o - \ +# RUN: llc -mtriple riscv64 -mattr=+m2p0,+experimental-v0p10 -start-before=prologepilog -o - \ # RUN: -verify-machineinstrs %s | FileCheck %s --- | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" Index: llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs < %s | FileCheck %s ; Check that we are able to legalize scalable-vector loads that require widening. Index: llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll +++ llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @trunc_nxv4i32_to_nxv4i5( %a) { ; CHECK-LABEL: trunc_nxv4i32_to_nxv4i5: Index: llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs < %s | FileCheck %s ; Check that we are able to legalize scalable-vector stores that require widening. Index: llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll +++ llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv32 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv64 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s define void @vadd_vint16m1( *%pc, *%pa, *%pb) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll +++ llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv32 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv64 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s define void @vadd_vint32m1( *%pc, *%pa, *%pb) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll +++ llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv32 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv64 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s define void @vadd_vint64m1( *%pc, *%pa, *%pb) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll +++ llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv32 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv64 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s define void @vadd_vint8m1( *%pc, *%pa, *%pb) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/load-mask.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/load-mask.ll +++ llvm/test/CodeGen/RISCV/rvv/load-mask.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv32 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ +; RUN: llc -mtriple riscv64 -mattr=+experimental-v0p10 %s -o - \ ; RUN: -verify-machineinstrs | FileCheck %s define void @test_load_mask_64(* %pa, * %pb) { Index: llvm/test/CodeGen/RISCV/rvv/localvar.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/localvar.ll +++ llvm/test/CodeGen/RISCV/rvv/localvar.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IV define void @local_var_mf8() { Index: llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @sext_nxv1i1_nxv1i8( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i8: @@ -726,4 +726,3 @@ %r = trunc %v to ret %r } - Index: llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @sext_nxv1i1_nxv1i8( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i8: @@ -726,4 +726,3 @@ %r = trunc %v to ret %r } - Index: llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir +++ llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +# RUN: llc -march=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ # RUN: -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s --- | Index: llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s define @masked_load_nxv1f16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1f16: Index: llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll +++ llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @masked_load_nxv1i8(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s define void @masked_store_nxv1f16( %val, * %a, %mask) nounwind { ; CHECK-LABEL: masked_store_nxv1f16: Index: llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll +++ llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define void @masked_store_nxv1i8( %val, * %a, %mask) nounwind { ; CHECK-LABEL: masked_store_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/memory-args.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/memory-args.ll +++ llvm/test/CodeGen/RISCV/rvv/memory-args.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -O2 < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IV declare @llvm.riscv.vmacc.nxv64i8.nxv64i8( Index: llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 declare @llvm.masked.gather.nxv1i8.nxv1p0i8(, i32, , ) Index: llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 declare void @llvm.masked.scatter.nxv1i8.nxv1p0i8(, , i32, ) Index: llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll +++ llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-UNKNOWN -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-256 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-512 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-UNKNOWN -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-256 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-512 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-UNKNOWN +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-256 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-512 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-UNKNOWN +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-256 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+f2p0,+d2p0,+experimental-zfh0p1 -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-512 ; ; VECTOR_REVERSE - masks Index: llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll +++ llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s define signext i32 @foo(i32 signext %aa) #0 { Index: llvm/test/CodeGen/RISCV/rvv/pr52475.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/pr52475.ll +++ llvm/test/CodeGen/RISCV/rvv/pr52475.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 \ ; RUN: -pre-RA-sched=list-burr -disable-machine-cse -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 \ ; RUN: -pre-RA-sched=list-burr -disable-machine-cse -verify-machineinstrs < %s | FileCheck %s define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) { Index: llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir +++ llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc %s -mtriple=riscv64 -mattr=+experimental-v -run-pass=simple-register-coalescing -o - | FileCheck %s +# RUN: llc %s -mtriple=riscv64 -mattr=+experimental-v0p10 -run-pass=simple-register-coalescing -o - | FileCheck %s --- # Make sure that SrcReg & DstReg of PseudoVRGATHER are not coalesced name: test_earlyclobber Index: llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll +++ llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh,+m \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1,+m \ ; RUN: -regalloc=fast -verify-machineinstrs < %s | FileCheck %s ; This test previously crashed with an error "ran out of registers during register allocation" Index: llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll +++ llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -O0 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0 -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -O2 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0 -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 Index: llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll +++ llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -O0 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -O2 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s define @spill_lmul_mf2( %va) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll +++ llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -mattr=+m -O0 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -mattr=+m2p0 -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -mattr=+m -O2 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -mattr=+m2p0 -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s define @spill_zvlsseg_nxv1i32(i32* %base, i32 %vl) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll +++ llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare i32 @llvm.riscv.vsetvli.i32(i32, i32, i32) declare i32 @llvm.riscv.vsetvlimax.i32(i32, i32) Index: llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll +++ llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -mattr=+d -O0 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -mattr=+d2p0 -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -mattr=+d -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -mattr=+d2p0 -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 Index: llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll +++ llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -O0 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s define @spill_lmul_1( %va) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll +++ llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+m -O0 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -mattr=+m2p0 -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+m -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -mattr=+m2p0 -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s define @spill_zvlsseg_nxv1i32(i32* %base, i64 %vl) nounwind { Index: llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll +++ llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare i64 @llvm.riscv.vsetvli.i64(i64, i64, i64) declare i64 @llvm.riscv.vsetvlimax.i64(i64, i64) Index: llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll +++ llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+m -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+m -verify-machineinstrs < %s | FileCheck %s define void @rvv_vla(i64 %n, i64 %i) nounwind { ; CHECK-LABEL: rvv_vla: Index: llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll +++ llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s define dso_local void @lots_args(i32 signext %x0, i32 signext %x1, %v0, i32 signext %x2, i32 signext %x3, i32 signext %x4, i32 signext %x5, i32 signext %x6, i32 %x7, i32 %x8, i32 %x9) #0 { Index: llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll +++ llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+m,+experimental-v < %s \ +; RUN: llc -mtriple riscv32 -mattr=+m2p0,+experimental-v0p10 < %s \ ; RUN: | FileCheck %s define i32 @vscale_zero() nounwind { Index: llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll +++ llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v < %s \ +; RUN: llc -mtriple riscv64 -mattr=+m2p0,+experimental-v0p10 < %s \ ; RUN: | FileCheck %s -check-prefix=RV64 -; RUN: llc -mtriple riscv32 -mattr=+m,+experimental-v < %s \ +; RUN: llc -mtriple riscv32 -mattr=+m2p0,+experimental-v0p10 < %s \ ; RUN: | FileCheck %s -check-prefix=RV32 Index: llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare { , } @llvm.sadd.with.overflow.nxv2i32(, ) Index: llvm/test/CodeGen/RISCV/rvv/select-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/select-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/select-fp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @select_nxv1f16(i1 zeroext %c, %a, %b) { Index: llvm/test/CodeGen/RISCV/rvv/select-int.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/select-int.ll +++ llvm/test/CodeGen/RISCV/rvv/select-int.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 define @select_nxv1i1(i1 zeroext %c, %a, %b) { Index: llvm/test/CodeGen/RISCV/rvv/select-sra.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/select-sra.ll +++ llvm/test/CodeGen/RISCV/rvv/select-sra.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 ; This test checks a regression in the select-to-sra transform, which was ; asserting (without a precondition) when the vector constants implicitly Index: llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; FIXME: The scalar/vector operations ('fv' tests) should swap operands and Index: llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; FIXME: The scalar/vector operations ('fv' tests) should swap operands and Index: llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @icmp_eq_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i8: Index: llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @icmp_eq_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i8: Index: llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll +++ llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-v,+f \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10,+f2p0 \ ; RUN: -riscv-v-vector-bits-min=128 | FileCheck %s define void @sink_splat_mul(i32* nocapture %a, i32 signext %x) { Index: llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare { , } @llvm.smul.with.overflow.nxv1i8(, ) Index: llvm/test/CodeGen/RISCV/rvv/stepvector.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/stepvector.ll +++ llvm/test/CodeGen/RISCV/rvv/stepvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 declare @llvm.experimental.stepvector.nxv1i8() Index: llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir +++ llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc %s -mtriple=riscv64 -mattr=experimental-v -riscv-v-vector-bits-min=128 -run-pass=finalize-isel -o - | FileCheck %s +# RUN: llc %s -mtriple=riscv64 -mattr=experimental-v0p10 -riscv-v-vector-bits-min=128 -run-pass=finalize-isel -o - | FileCheck %s # This test makes sure we peak through the COPY instruction between the # IMPLICIT_DEF and PseudoVLE64_V_M8_MASK in order to select the tail agnostic @@ -21,8 +21,8 @@ ; Function Attrs: argmemonly nofree nosync nounwind readonly willreturn declare @llvm.masked.load.nxv8i64.p0nxv8i64(*, i32 immarg, , ) #1 - attributes #0 = { nounwind "target-features"="+experimental-v" } - attributes #1 = { argmemonly nofree nosync nounwind readonly willreturn "target-features"="+experimental-v" } + attributes #0 = { nounwind "target-features"="+experimental-v0p10" } + attributes #1 = { argmemonly nofree nosync nounwind readonly willreturn "target-features"="+experimental-v0p10" } ... --- Index: llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare { , } @llvm.umul.with.overflow.nxv1i8(, ) Index: llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll +++ llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+d,+experimental-zfh,+experimental-v < %s \ +; RUN: llc -mtriple riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 < %s \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+d,+experimental-zfh,+experimental-v < %s \ +; RUN: llc -mtriple riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 < %s \ ; RUN: -verify-machineinstrs | FileCheck %s define @unaligned_load_nxv1i32_a1(* %ptr) { Index: llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll +++ llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; Test that we can remove trivially-undef VP operations of various kinds. Index: llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll +++ llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: not --crash llc -mtriple=riscv64 -mattr=+experimental-v < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=riscv64 -mattr=+experimental-v0p10 < %s 2>&1 | FileCheck %s ; A rather pathological test case in which we exhaust all vector registers and ; all scalar registers, forcing %z to go through the stack. This is not yet Index: llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll +++ llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 < %s | FileCheck %s --check-prefix=RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 < %s | FileCheck %s --check-prefix=RV64 define @test_urem_vec_even_divisor_eq0( %x) nounwind { ; RV32-LABEL: test_urem_vec_even_divisor_eq0: Index: llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vaadd.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vaadd.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vadc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vadc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll +++ llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vadd.nxv8i8.nxv8i8( @@ -62,4 +62,3 @@ ret %a } - Index: llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vadd.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vadd.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vadd_vx_nxv1i8( %va, i8 signext %b) { ; CHECK-LABEL: vadd_vx_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.add.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoadd.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoadd.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoand.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoand.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamomax.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamomax.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamomaxu.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamomaxu.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamomin.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamomin.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamominu.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamominu.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoor.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoor.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoswap.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoswap.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoxor.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zvamo0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vamoxor.nxv1i32.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vand.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vand.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vand_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv1i8: @@ -1351,4 +1351,3 @@ %vc = and %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vand-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vand-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vand-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.and.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vasub.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vasub.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vasubu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vasubu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vcompress.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vcompress.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vcpop-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vcpop-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vcpop-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare i32 @llvm.riscv.vcpop.i32.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vcpop-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vcpop-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vcpop-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare i64 @llvm.riscv.vcpop.i64.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vdiv.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vdiv.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vdiv_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv1i8: @@ -1178,4 +1178,3 @@ %vc = sdiv %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.sdiv.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vdivu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vdivu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vdivu_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.udiv.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vsext_nxv1i8_nxv1i16( %va) { ; CHECK-LABEL: vsext_nxv1i8_nxv1i16: @@ -617,4 +617,3 @@ %evec = zext %va to ret %evec } - Index: llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.fabs.nxv1f16() Index: llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfadd.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ -; RUN: -mattr=+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -mattr=+experimental-zfh0p1 \ +; RUN: -mattr=+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfadd.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfadd_vv_nxv1f16( %va, %vb) { @@ -369,4 +369,3 @@ %vc = fadd %splat, %va ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fadd.nxv1f16(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfclass.nxv1i16( , Index: llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfclass.nxv1i16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.copysign.nxv1f16(, ) Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfdiv.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfdiv_vv_nxv1f16( %va, %vb) { @@ -369,4 +369,3 @@ %vc = fdiv %splat, %va ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fdiv.nxv1f16(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare i32 @llvm.riscv.vfirst.i32.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare i64 @llvm.riscv.vfirst.i64.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfmacc and vfmadd by using different operand orders to Index: llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmax.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmax.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.maxnum.nxv1f16(, ) Index: llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmerge.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmerge.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmin.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmin.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.minnum.nxv1f16(, ) Index: llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfmsac and vfmsub by using different operand orders to Index: llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmul.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmul.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfmul_vv_nxv1f16( %va, %vb) { @@ -369,4 +369,3 @@ %vc = fmul %splat, %va ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fmul.nxv1f16(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-v,+experimental-zfh -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-v,+experimental-zfh -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-v0p10,+experimental-zfh0p1 -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-v0p10,+experimental-zfh0p1 -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s declare half @llvm.riscv.vfmv.f.s.nxv1f16() Index: llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-v,+experimental-zfh -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-v0p10,+experimental-zfh0p1 -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s declare @llvm.riscv.vfmv.s.f.nxv1f16(, half, i32) Index: llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-v,+experimental-zfh -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-v0p10,+experimental-zfh0p1 -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s declare @llvm.riscv.vfmv.s.f.nxv1f16(, half, i64) Index: llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -target-abi ilp32d -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmv.v.f.nxv1f16( half, Index: llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -target-abi lp64d -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfmv.v.f.nxv1f16( half, Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfneg_vv_nxv1f16( %va) { Index: llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfnmacc and vfnmadd by using different operand orders to Index: llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfnmsac and vfnmsub by using different operand orders to Index: llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 define @vfpext_nxv1f16_nxv1f32( %va) { @@ -258,4 +258,3 @@ %evec = fpext %va to ret %evec } - Index: llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfptosi_nxv1f16_nxv1i1( %va) { @@ -1615,4 +1615,3 @@ %evec = fptoui %va to ret %evec } - Index: llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 define @vfptrunc_nxv1f32_nxv1f16( %va) { @@ -258,4 +258,3 @@ %evec = fptrunc %va to ret %evec } - Index: llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfrdiv.nxv1f16.f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfrdiv.nxv1f16.f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fdiv.nxv1f16(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfrec7.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfrec7.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfredusum-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfredusum-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfredusum-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfredusum-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfredusum-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfredusum-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfrsqrt7.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfrsqrt7.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfrsub.nxv1f16.f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ -; RUN: -mattr=+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -mattr=+experimental-zfh0p1 \ +; RUN: -mattr=+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfrsub.nxv1f16.f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fsub.nxv1f16(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsgnj.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsgnjn.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsgnjx.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfslide1down.nxv1f16.f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfslide1down.nxv1f16.f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfslide1up.nxv1f16.f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfslide1up.nxv1f16.f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsqrt.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsqrt.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.sqrt.nxv1f16() Index: llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsub.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ -; RUN: -mattr=+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -mattr=+experimental-zfh0p1 \ +; RUN: -mattr=+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfsub.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfsub_vv_nxv1f16( %va, %vb) { @@ -369,4 +369,3 @@ %vc = fsub %splat, %va ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fsub.nxv1f16(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vid.nxv1i8( i32); Index: llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vid.nxv1i8( i64); Index: llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.viota.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.viota.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vsitofp_nxv1i1_nxv1f16( %va) { @@ -1573,4 +1573,3 @@ %evec = uitofp %va to ret %evec } - Index: llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -mattr=+experimental-zfh \ -; RUN: -mattr=+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -mattr=+experimental-zfh0p1 \ +; RUN: -mattr=+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vle.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ -; RUN: -mattr=+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -mattr=+experimental-zfh0p1 \ +; RUN: -mattr=+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vle.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare { , i32 } @llvm.riscv.vleff.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare { , i64 } @llvm.riscv.vleff.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vlm.nxv1i1(*, i32); Index: llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vlm.nxv1i1(*, i64); Index: llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vloxei.nxv1i8.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vloxei.nxv1i8.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, , i32) @@ -12874,4 +12874,3 @@ %1 = extractvalue {,,,} %0, 1 ret %1 } - Index: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, , i64) @@ -18416,4 +18416,3 @@ %1 = extractvalue {,,,} %0, 1 ret %1 } - Index: llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vlse.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vlse.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vlseg2.nxv16i16(i16* , i32) Index: llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vlseg2.nxv16i16(i16* , i64) Index: llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll +++ llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) Index: llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) @@ -5236,4 +5236,3 @@ store i32 %2, i32* %outvl ret %1 } - Index: llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll +++ llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) Index: llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) @@ -5678,4 +5678,3 @@ store i64 %2, i64* %outvl ret %1 } - Index: llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vlsseg2.nxv16i16(i16*, i32, i32) Index: llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vlsseg2.nxv16i16(i16*, i64, i64) Index: llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vluxei.nxv1i8.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vluxei.nxv1i8.nxv1i64( *, Index: llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, , i32) @@ -12874,4 +12874,3 @@ %1 = extractvalue {,,,} %0, 1 ret %1 } - Index: llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, , i64) @@ -18416,4 +18416,3 @@ %1 = extractvalue {,,,} %0, 1 ret %1 } - Index: llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmacc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmacc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmadc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmadc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmadd.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmadd.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -target-abi=ilp32 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -target-abi=lp64 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; This tests a mix of vmacc and vmadd by using different operand orders to Index: llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmand.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmand.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmandn-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmandn-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmandn-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmandn.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmandn-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmandn-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmandn-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmandn.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vmand_vv_nxv1i1( %va, %vb) { ; CHECK-LABEL: vmand_vv_nxv1i1: @@ -476,4 +476,3 @@ %vc = or %va, %not ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmax.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmax.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vmax_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv1i8: @@ -889,4 +889,3 @@ %vc = select %cmp, %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vmax_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv1i8: @@ -889,4 +889,3 @@ %vc = select %cmp, %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmclr.nxv1i1( i32); Index: llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmclr.nxv1i1( i64); Index: llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmerge.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmerge.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfeq.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfeq.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfge.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfge.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfgt.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfgt.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfle.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfle.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmflt.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmflt.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfne.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmfne.nxv1f16( , Index: llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmin.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmin.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vmin_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv1i8: @@ -889,4 +889,3 @@ %vc = select %cmp, %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vminu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vminu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vmin_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv1i8: @@ -889,4 +889,3 @@ %vc = select %cmp, %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmnand.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmnand.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmnor.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmnor.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmor.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmor.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmorn-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmorn-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmorn-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmorn.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmorn-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmorn-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmorn-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmorn.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsbf.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsbf.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmseq.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmseq.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmset.nxv1i1( i32); Index: llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmset.nxv1i1( i64); Index: llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsge.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsge.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsgeu.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsgeu.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsgt.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsgt.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsgtu.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsgtu.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsif.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsif.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsle.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsle.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsleu.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsleu.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmslt.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmslt.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsltu.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsltu.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsne.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsne.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsof.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmsof.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmul.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmul.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vmul_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.mul.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmulh.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmulh.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; Test that the prepareSREMEqFold optimization doesn't crash on scalable ; vector types. Index: llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vmulhu_vv_nxv1i32( %va, %vb) { ; CHECK-LABEL: vmulhu_vv_nxv1i32: Index: llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare @llvm.riscv.vmv.s.x.nxv1i8(, i8, i32) Index: llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare @llvm.riscv.vmv.s.x.nxv1i8(, i8, i64); Index: llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmv.v.v.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmv.v.v.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmv.v.x.nxv1i8( i8, Index: llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmv.v.x.nxv1i8( i8, Index: llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare i8 @llvm.riscv.vmv.x.s.nxv1i8() Index: llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare i8 @llvm.riscv.vmv.x.s.nxv1i8() Index: llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmxnor.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmxnor.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmxor.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmxor.nxv1i1( , Index: llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -target-abi=ilp32 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -target-abi=lp64 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; This tests a mix of vmacc and vmsub by using different operand orders to Index: llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vor.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vor.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vor_vx_nxv1i8( %va, i8 signext %b) { ; CHECK-LABEL: vor_vx_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/vor-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vor-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vor-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.or.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.gather.nxv1i8.nxv1p0i8(, , i32) Index: llvm/test/CodeGen/RISCV/rvv/vpload.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vpload.ll +++ llvm/test/CodeGen/RISCV/rvv/vpload.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.load.nxv1i8.p0nxv1i8(*, , i32) Index: llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 declare void @llvm.vp.scatter.nxv1i8.nxv1p0i8(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vpstore.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vpstore.ll +++ llvm/test/CodeGen/RISCV/rvv/vpstore.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.vp.store.nxv1i8.p0nxv1i8(, *, , i32) Index: llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredand.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredand.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredmax.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredmax.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredmin.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredmin.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredminu.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredminu.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredor.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredor.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredsum.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredsum.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare half @llvm.vector.reduce.fadd.nxv1f16(half, ) Index: llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare half @llvm.vp.reduce.fadd.nxv1f16(half, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare i8 @llvm.vector.reduce.add.nxv1i8() Index: llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare i8 @llvm.vector.reduce.add.nxv1i8() Index: llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare i8 @llvm.vp.reduce.add.nxv1i8(i8, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare i1 @llvm.vp.reduce.and.nxv1i1(i1, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll +++ llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s declare i1 @llvm.vector.reduce.or.nxv1i1() Index: llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredxor.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vredxor.nxv8i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vrem.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vrem.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vrem_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv1i8: @@ -1228,4 +1228,3 @@ %vc = srem %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.srem.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vremu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vremu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vremu_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.urem.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vrgather.vv.nxv1i8.i32( , Index: llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vrgather.vv.nxv1i8.i64( , Index: llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vrgatherei16.vv.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vrgatherei16.vv.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vrsub.nxv1i8.i8( , Index: llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vrsub.nxv1i8.i8( , Index: llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vrsub_vx_nxv1i8( %va, i8 signext %b) { ; CHECK-LABEL: vrsub_vx_nxv1i8: @@ -581,4 +581,3 @@ %vc = sub %splat, %va ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.sub.nxv1i8(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsadd.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsadd.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.sadd.sat.nxv1i8(, ) Index: llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.uadd.sat.nxv1i8(, ) Index: llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsbc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsbc.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -mattr=+experimental-zfh \ -; RUN: -mattr=+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -mattr=+experimental-zfh0p1 \ +; RUN: -mattr=+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vse.nxv1i64( , Index: llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ -; RUN: -mattr=+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -mattr=+experimental-zfh0p1 \ +; RUN: -mattr=+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vse.nxv1i64( , Index: llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfmerge_vv_nxv1f16( %va, %vb, %cond) { Index: llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfmerge_vv_nxv1f16( %va, %vb, %cond) { Index: llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vmerge_vv_nxv1i8( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vmerge_vv_nxv1i8( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll +++ llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vselect_nxv1i1( %a, %b, %cc) { ; CHECK-LABEL: vselect_nxv1i1: Index: llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.select.nxv1i8(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll +++ llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-v | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-v0p10 | FileCheck %s declare i64 @llvm.riscv.vsetvli( i64, i64, i64); Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll +++ llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+experimental-v \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+f2p0,+d2p0,+a2p0,+c2p0,+experimental-v0p10 \ ; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s ; The following tests check whether inserting VSETVLI avoids inserting Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir +++ llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc %s -o - -mtriple=riscv64 -mattr=experimental-v \ +# RUN: llc %s -o - -mtriple=riscv64 -mattr=experimental-v0p10 \ # RUN: -run-pass=riscv-insert-vsetvli | FileCheck %s --- | @@ -116,7 +116,7 @@ ; Function Attrs: nounwind readnone declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, i64) #1 - attributes #0 = { "target-features"="+experimental-v" } + attributes #0 = { "target-features"="+experimental-v0p10" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } attributes #3 = { nounwind readonly } Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll +++ llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+experimental-v \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+f2p0,+d2p0,+a2p0,+c2p0,+experimental-v0p10 \ ; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s declare i64 @llvm.riscv.vsetvli(i64, i64, i64) Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir +++ llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc %s -o - -mtriple=riscv64 -mattr=experimental-v \ +# RUN: llc %s -o - -mtriple=riscv64 -mattr=experimental-v0p10 \ # RUN: -run-pass=riscv-insert-vsetvli | FileCheck %s --- | @@ -84,7 +84,7 @@ ; Function Attrs: nounwind readnone declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, i64) #1 - attributes #0 = { "target-features"="+experimental-v" } + attributes #0 = { "target-features"="+experimental-v0p10" } attributes #1 = { nounwind readnone } attributes #2 = { nofree nosync nounwind readnone willreturn } attributes #3 = { nounwind } Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll +++ llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-v | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-v0p10 | FileCheck %s ; This test checks a regression in the vsetvli insertion pass. We used to ; prserve the VL on the second vsetvli with ratio e32/m1, when the the last Index: llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsext.nxv1i64.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsext.nxv1i64.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vshl_vx_nxv1i8( %va, i8 signext %b) { ; CHECK-LABEL: vshl_vx_nxv1i8: Index: llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.shl.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslide1down.nxv1i8.i8( , Index: llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslide1down.nxv1i8.i8( , Index: llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslide1up.nxv1i8.i8( , Index: llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslide1up.nxv1i8.i8( , Index: llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslidedown.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslidedown.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslideup.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslideup.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsll.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsll.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vsm.nxv1i1(, *, i32); Index: llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vsm.nxv1i1(, *, i64); Index: llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vsoxei.nxv1i8.nxv1i64( , Index: llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vsoxei.nxv1i8.nxv1i64( , Index: llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(,, i16*, , i32) @@ -13329,4 +13329,3 @@ tail call void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i32( %val, %val, %val, %val, float* %base, %index, %mask, i32 %vl) ret void } - Index: llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(,, i16*, , i64) @@ -19064,4 +19064,3 @@ tail call void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i16( %val, %val, %val, %val, float* %base, %index, %mask, i64 %vl) ret void } - Index: llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll +++ llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+experimental-zfh,+experimental-v -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV32V -; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zfh,+experimental-v -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0,+experimental-zfh0p1,+experimental-v0p10 -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV64V define @vsplat_nxv8f16(half %f) { Index: llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll +++ llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vsplat_nxv1i1_0() { ; CHECK-LABEL: vsplat_nxv1i1_0: Index: llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV32V -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV64V define @vsplat_nxv8i64_1() { Index: llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsra.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsra.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vsra_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv1i8: @@ -801,4 +801,3 @@ %vc = ashr %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.ashr.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsrl.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsrl.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vsrl_vx_nxv1i8( %va, i8 signext %b) { ; CHECK-LABEL: vsrl_vx_nxv1i8: @@ -581,4 +581,3 @@ %vc = lshr %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.lshr.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vsse.nxv1i64( , Index: llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vsse.nxv1i64( , Index: llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsseg2.nxv16i16(,, i16* , i32) Index: llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsseg2.nxv16i16(,, i16* , i64) Index: llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vssra.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vssra.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vssrl.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vssrl.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vssseg2.nxv16i16(,, i16*, i32, i32) Index: llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vssseg2.nxv16i16(,, i16*, i64, i64) Index: llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vssub.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vssub.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.ssub.sat.nxv1i8(, ) Index: llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vssubu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vssubu.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.usub.sat.nxv1i8(, ) Index: llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsub.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vsub.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vsub_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv1i8: @@ -838,4 +838,3 @@ %vc = sub %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.sub.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vsuxei.nxv1i8.nxv1i64( , Index: llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare void @llvm.riscv.vsuxei.nxv1i8.nxv1i64( , Index: llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(,, i16*, , i32) @@ -13329,4 +13329,3 @@ tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i32( %val, %val, %val, %val, float* %base, %index, %mask, i32 %vl) ret void } - Index: llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(,, i16*, , i64) @@ -19064,4 +19064,3 @@ tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16( %val, %val, %val, %val, float* %base, %index, %mask, i64 %vl) ret void } - Index: llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s define @vtrunc_nxv1i16_nxv1i8( %va) { ; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8: @@ -313,4 +313,3 @@ %tvec = trunc %va to ret %tvec } - Index: llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -early-live-intervals < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs -early-live-intervals < %s | FileCheck %s declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8( , , Index: llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -early-live-intervals < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -early-live-intervals < %s | FileCheck %s declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8( , , Index: llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmaccus.nxv1i16.i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmaccus.nxv1i16.i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10,+f2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vxor.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vxor.nxv1i8.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll +++ llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vxor_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv1i8: @@ -1351,4 +1351,3 @@ %vc = xor %va, %splat ret %vc } - Index: llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll +++ llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.xor.nxv8i7(, , , i32) Index: llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll +++ llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vzext.nxv1i64.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll +++ llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vzext.nxv1i64.nxv1i8( , Index: llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir +++ llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -# RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -o - %s \ +# RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -o - %s \ # RUN: -start-before=prologepilog | FileCheck %s # # This test checks that we are assigning the right stack slot to GPRs and to Index: llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir +++ llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -# RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -o - %s \ +# RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -o - %s \ # RUN: -start-before=prologepilog | FileCheck %s # # This test checks that we are assigning the right stack slot to GPRs and to Index: llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir +++ llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple riscv64 -mattr=+experimental-v -verify-machineinstrs -run-pass=postrapseudos %s -o - | FileCheck %s +# RUN: llc -mtriple riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs -run-pass=postrapseudos %s -o - | FileCheck %s ... --- Index: llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir =================================================================== --- llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir +++ llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=riscv64 -mattr=+experimental-v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s +# RUN: llc -march=riscv64 -mattr=+experimental-v0p10 -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s --- | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" Index: llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll +++ llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zvlsseg0p10,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use Index: llvm/test/CodeGen/RISCV/sadd_sat.ll =================================================================== --- llvm/test/CodeGen/RISCV/sadd_sat.ll +++ llvm/test/CodeGen/RISCV/sadd_sat.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RV32I +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 | FileCheck %s --check-prefix=RV64I +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0,+experimental-zbt0p93 | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0,+experimental-zbt0p93 | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt declare i4 @llvm.sadd.sat.i4(i4, i4) declare i8 @llvm.sadd.sat.i8(i8, i8) Index: llvm/test/CodeGen/RISCV/sadd_sat_plus.ll =================================================================== --- llvm/test/CodeGen/RISCV/sadd_sat_plus.ll +++ llvm/test/CodeGen/RISCV/sadd_sat_plus.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RV32I +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 | FileCheck %s --check-prefix=RV64I +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0,+experimental-zbt0p93 | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0,+experimental-zbt0p93 | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt declare i4 @llvm.sadd.sat.i4(i4, i4) declare i8 @llvm.sadd.sat.i8(i8, i8) Index: llvm/test/CodeGen/RISCV/saverestore.ll =================================================================== --- llvm/test/CodeGen/RISCV/saverestore.ll +++ llvm/test/CodeGen/RISCV/saverestore.ll @@ -2,8 +2,8 @@ ; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I ; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR ; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR -; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR -; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR ; Check that the correct save/restore libcalls are generated. Index: llvm/test/CodeGen/RISCV/scalable-vector-struct.ll =================================================================== --- llvm/test/CodeGen/RISCV/scalable-vector-struct.ll +++ llvm/test/CodeGen/RISCV/scalable-vector-struct.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s | FileCheck %s ; This demonstrates that we can pass a struct containing scalable vectors across ; a basic block. Index: llvm/test/CodeGen/RISCV/select-and.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-and.ll +++ llvm/test/CodeGen/RISCV/select-and.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IBT %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IBT %s ;; There are a few different ways to lower (select (and A, B), X, Y). This test Index: llvm/test/CodeGen/RISCV/select-bare.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-bare.ll +++ llvm/test/CodeGen/RISCV/select-bare.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IBT define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind { Index: llvm/test/CodeGen/RISCV/select-cc.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-cc.ll +++ llvm/test/CodeGen/RISCV/select-cc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -disable-block-placement -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IBT %s define signext i32 @foo(i32 signext %a, i32 *%b) nounwind { Index: llvm/test/CodeGen/RISCV/select-const.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-const.ll +++ llvm/test/CodeGen/RISCV/select-const.ll @@ -1,19 +1,19 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IBT %s -; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0,+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFBT %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFD %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IBT %s -; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0,+d2p0,+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IFDBT %s ;; This tests how good we are at materialising constants using `select`. The aim Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-optimize-multiple.ll +++ llvm/test/CodeGen/RISCV/select-optimize-multiple.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0,+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IBT -; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0,+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IBT ; Selects of wide values are split into two selects, which can easily cause Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.mir =================================================================== --- llvm/test/CodeGen/RISCV/select-optimize-multiple.mir +++ llvm/test/CodeGen/RISCV/select-optimize-multiple.mir @@ -1,11 +1,11 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \ # RUN: | FileCheck -check-prefix=RV32I %s -# RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \ +# RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 -run-pass=finalize-isel -simplify-mir -o - %s \ # RUN: | FileCheck -check-prefix=RV32IBT %s # RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \ # RUN: | FileCheck -check-prefix=RV64I %s -# RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \ +# RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt0p93 -run-pass=finalize-isel -simplify-mir -o - %s \ # RUN: | FileCheck -check-prefix=RV64IBT %s # Provide dummy definitions of functions and just enough metadata to create a Index: llvm/test/CodeGen/RISCV/select-or.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-or.ll +++ llvm/test/CodeGen/RISCV/select-or.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IBT %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt0p93 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IBT %s ;; There are a few different ways to lower (select (or A, B), X, Y). This test Index: llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll =================================================================== --- llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll +++ llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll @@ -3,9 +3,9 @@ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,RV32I ; RUN: llc < %s -mtriple=riscv64 \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-zbb \ +; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-zbb1p0 \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZBB -; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zbb \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zbb1p0 \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZBB ; Compare if negative and select of constants where one constant is zero. Index: llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll =================================================================== --- llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll +++ llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10,+d2p0,+experimental-zfh0p1 \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck %s Index: llvm/test/CodeGen/RISCV/srem-lkk.ll =================================================================== --- llvm/test/CodeGen/RISCV/srem-lkk.ll +++ llvm/test/CodeGen/RISCV/srem-lkk.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s define i32 @fold_srem_positive_odd(i32 %x) nounwind { Index: llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll =================================================================== --- llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll +++ llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=RV32 ; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m < %s | FileCheck %s --check-prefixes=RV32M -; RUN: llc -mtriple=riscv64 -mattr=+m < %s | FileCheck %s --check-prefixes=RV64M -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=RV32MV -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=RV64MV +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 < %s | FileCheck %s --check-prefixes=RV32M +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 < %s | FileCheck %s --check-prefixes=RV64M +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=RV32MV +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=RV64MV define i1 @test_srem_odd(i29 %X) nounwind { ; RV32-LABEL: test_srem_odd: Index: llvm/test/CodeGen/RISCV/srem-vector-lkk.ll =================================================================== --- llvm/test/CodeGen/RISCV/srem-vector-lkk.ll +++ llvm/test/CodeGen/RISCV/srem-vector-lkk.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IM %s define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind { Index: llvm/test/CodeGen/RISCV/ssub_sat.ll =================================================================== --- llvm/test/CodeGen/RISCV/ssub_sat.ll +++ llvm/test/CodeGen/RISCV/ssub_sat.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RV32I +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 | FileCheck %s --check-prefix=RV64I +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0,+experimental-zbt0p93 | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0,+experimental-zbt0p93 | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt declare i4 @llvm.ssub.sat.i4(i4, i4) declare i8 @llvm.ssub.sat.i8(i8, i8) Index: llvm/test/CodeGen/RISCV/ssub_sat_plus.ll =================================================================== --- llvm/test/CodeGen/RISCV/ssub_sat_plus.ll +++ llvm/test/CodeGen/RISCV/ssub_sat_plus.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RV32I +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 | FileCheck %s --check-prefix=RV64I +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0,+experimental-zbt0p93 | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0,+experimental-zbt0p93 | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt declare i4 @llvm.ssub.sat.i4(i4, i4) declare i8 @llvm.ssub.sat.i8(i8, i8) Index: llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll =================================================================== --- llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll +++ llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll @@ -2,7 +2,7 @@ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s -; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \ +; RUN: llc -mtriple=riscv32 -mattr=-f2p0 -target-abi ilp32f <%s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s ; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension @@ -17,4 +17,4 @@ ret float %conv } -attributes #0 = { "target-features"="+f"} +attributes #0 = { "target-features"="+f2p0"} Index: llvm/test/CodeGen/RISCV/target-abi-invalid.ll =================================================================== --- llvm/test/CodeGen/RISCV/target-abi-invalid.ll +++ llvm/test/CodeGen/RISCV/target-abi-invalid.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=riscv32 -target-abi foo < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32I-FOO %s -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32foof < %s 2>&1 \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32foof < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32FOOF %s ; RV32I-FOO: 'foo' is not a recognized ABI for this target (ignoring target-abi) @@ -8,9 +8,9 @@ ; RUN: llc -mtriple=riscv64 -target-abi ilp32 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64I-ILP32 %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi ilp32f < %s 2>&1 \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64IF-ILP32F %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi ilp32d < %s 2>&1 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi ilp32d < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64IFD-ILP32D %s ; RUN: llc -mtriple=riscv64 -target-abi ilp32e < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64I-ILP32E %s @@ -22,9 +22,9 @@ ; RUN: llc -mtriple=riscv32 -target-abi lp64 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32I-LP64 %s -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi lp64f < %s 2>&1 \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi lp64f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-LP64F %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi lp64d < %s 2>&1 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi lp64d < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IFD-LP64D %s ; RV32I-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi) @@ -41,11 +41,11 @@ ; RUN: llc -mtriple=riscv32 -target-abi ilp32d < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32I-ILP32D %s -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32d < %s 2>&1 \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32d < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32D %s ; RUN: llc -mtriple=riscv64 -target-abi lp64d < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64I-LP64D %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64d < %s 2>&1 \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64d < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64IF-LP64D %s ; RV32I-ILP32D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi) Index: llvm/test/CodeGen/RISCV/target-abi-valid.ll =================================================================== --- llvm/test/CodeGen/RISCV/target-abi-valid.ll +++ llvm/test/CodeGen/RISCV/target-abi-valid.ll @@ -2,29 +2,29 @@ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32 < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32 < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s ; RUN: llc -mtriple=riscv64 < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s ; RUN: llc -mtriple=riscv64 -target-abi lp64 < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64 < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64 < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f < %s 2>&1 \ +; RUN: llc -mtriple=riscv32 -mattr=+f2p0 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f < %s 2>&1 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d < %s 2>&1 \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32d < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f < %s 2>&1 \ +; RUN: llc -mtriple=riscv64 -mattr=+f2p0 -target-abi lp64f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64f < %s 2>&1 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d < %s 2>&1 \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64d < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=CHECK-IMP %s define void @nothing() nounwind { Index: llvm/test/CodeGen/RISCV/uadd_sat.ll =================================================================== --- llvm/test/CodeGen/RISCV/uadd_sat.ll +++ llvm/test/CodeGen/RISCV/uadd_sat.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RV32I +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 | FileCheck %s --check-prefix=RV64I +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefix=RV32IZbb +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefix=RV64IZbb declare i4 @llvm.uadd.sat.i4(i4, i4) declare i8 @llvm.uadd.sat.i8(i8, i8) Index: llvm/test/CodeGen/RISCV/uadd_sat_plus.ll =================================================================== --- llvm/test/CodeGen/RISCV/uadd_sat_plus.ll +++ llvm/test/CodeGen/RISCV/uadd_sat_plus.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RV32I +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 | FileCheck %s --check-prefix=RV64I +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefix=RV32IZbb +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefix=RV64IZbb declare i4 @llvm.uadd.sat.i4(i4, i4) declare i8 @llvm.uadd.sat.i8(i8, i8) Index: llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll =================================================================== --- llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll +++ llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32 +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefixes=RISCV32 define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 { ; RISCV32-LABEL: muloti_test: Index: llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll =================================================================== --- llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll +++ llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll @@ -3,9 +3,9 @@ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,RV32I ; RUN: llc -mtriple=riscv64 < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,RV64I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb1p0 < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZBB -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb1p0 < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZBB ; TODO: Should we convert these to X ^ ((X ^ Y) & M) form when Zbb isn't Index: llvm/test/CodeGen/RISCV/urem-lkk.ll =================================================================== --- llvm/test/CodeGen/RISCV/urem-lkk.ll +++ llvm/test/CodeGen/RISCV/urem-lkk.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s define i32 @fold_urem_positive_odd(i32 %x) nounwind { Index: llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll =================================================================== --- llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll +++ llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=RV32 ; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m < %s | FileCheck %s --check-prefixes=RV32M -; RUN: llc -mtriple=riscv64 -mattr=+m < %s | FileCheck %s --check-prefixes=RV64M -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=RV32MV -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=RV64MV +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 < %s | FileCheck %s --check-prefixes=RV32M +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 < %s | FileCheck %s --check-prefixes=RV64M +; RUN: llc -mtriple=riscv32 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=RV32MV +; RUN: llc -mtriple=riscv64 -mattr=+m2p0,+experimental-v0p10 -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=RV64MV define i1 @test_urem_odd(i13 %X) nounwind { ; RV32-LABEL: test_urem_odd: Index: llvm/test/CodeGen/RISCV/urem-vector-lkk.ll =================================================================== --- llvm/test/CodeGen/RISCV/urem-vector-lkk.ll +++ llvm/test/CodeGen/RISCV/urem-vector-lkk.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s Index: llvm/test/CodeGen/RISCV/usub_sat.ll =================================================================== --- llvm/test/CodeGen/RISCV/usub_sat.ll +++ llvm/test/CodeGen/RISCV/usub_sat.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RV32I +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 | FileCheck %s --check-prefix=RV64I +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefix=RV32IZbb +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefix=RV64IZbb declare i4 @llvm.usub.sat.i4(i4, i4) declare i8 @llvm.usub.sat.i8(i8, i8) Index: llvm/test/CodeGen/RISCV/usub_sat_plus.ll =================================================================== --- llvm/test/CodeGen/RISCV/usub_sat_plus.ll +++ llvm/test/CodeGen/RISCV/usub_sat_plus.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 | FileCheck %s --check-prefix=RV32I +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 | FileCheck %s --check-prefix=RV64I +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefix=RV32IZbb +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zbb1p0 | FileCheck %s --check-prefix=RV64IZbb declare i4 @llvm.usub.sat.i4(i4, i4) declare i8 @llvm.usub.sat.i8(i8, i8) Index: llvm/test/CodeGen/RISCV/vararg.ll =================================================================== --- llvm/test/CodeGen/RISCV/vararg.ll +++ llvm/test/CodeGen/RISCV/vararg.ll @@ -3,20 +3,20 @@ ; RUN: | FileCheck -check-prefix=ILP32-ILP32F-FPELIM %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck -check-prefix=ILP32-ILP32F-WITHFP %s -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32f \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d2p0 -target-abi ilp32d \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64f \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64f \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d2p0 -target-abi lp64d \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all < %s \ Index: llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll =================================================================== --- llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll +++ llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v0p10 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV64 ; This test would lead one of the DAGCombiner's visitVSELECT optimizations to Index: llvm/test/CodeGen/RISCV/xaluo.ll =================================================================== --- llvm/test/CodeGen/RISCV/xaluo.ll +++ llvm/test/CodeGen/RISCV/xaluo.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m -verify-machineinstrs | FileCheck %s --check-prefix=RV32 -; RUN: llc < %s -mtriple=riscv64 -mattr=+m -verify-machineinstrs | FileCheck %s --check-prefix=RV64 -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZBA -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZBA +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0 -verify-machineinstrs | FileCheck %s --check-prefix=RV32 +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0 -verify-machineinstrs | FileCheck %s --check-prefix=RV64 +; RUN: llc < %s -mtriple=riscv32 -mattr=+m2p0,+experimental-zba1p0 -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZBA +; RUN: llc < %s -mtriple=riscv64 -mattr=+m2p0,+experimental-zba1p0 -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZBA ; ; Get the actual value of the overflow bit. @@ -4014,4 +4014,3 @@ declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone - Index: llvm/test/CodeGen/RISCV/zfh-imm.ll =================================================================== --- llvm/test/CodeGen/RISCV/zfh-imm.ll +++ llvm/test/CodeGen/RISCV/zfh-imm.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfh < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfh0p1 < %s \ ; RUN: | FileCheck --check-prefix=RV32IZFH %s -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+experimental-zfh,+d < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+experimental-zfh0p1,+d2p0 < %s \ ; RUN: | FileCheck --check-prefix=RV32IDZFH %s -; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfh < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfh0p1 < %s \ ; RUN: | FileCheck --check-prefix=RV64IZFH %s -; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+experimental-zfh,+d < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+experimental-zfh0p1,+d2p0 < %s \ ; RUN: | FileCheck --check-prefix=RV64IDZFH %s define half @f16_positive_zero(half *%pf) nounwind { Index: llvm/test/MC/Disassembler/RISCV/branch-targets.txt =================================================================== --- llvm/test/MC/Disassembler/RISCV/branch-targets.txt +++ llvm/test/MC/Disassembler/RISCV/branch-targets.txt @@ -1,7 +1,7 @@ -# RUN: llvm-mc -assemble -triple riscv32 -mattr=+c -filetype=obj %s -o - 2>&1 | \ -# RUN: llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s -# RUN: llvm-mc -assemble -triple riscv64 -mattr=+c -filetype=obj %s -o - 2>&1 | \ -# RUN: llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s +# RUN: llvm-mc -assemble -triple riscv32 -mattr=+c2p0 -filetype=obj %s -o - 2>&1 | \ +# RUN: llvm-objdump -d --mattr=+c2p0 -M no-aliases - | FileCheck %s +# RUN: llvm-mc -assemble -triple riscv64 -mattr=+c2p0 -filetype=obj %s -o - 2>&1 | \ +# RUN: llvm-objdump -d --mattr=+c2p0 -M no-aliases - | FileCheck %s label1: .option norvc Index: llvm/test/MC/Disassembler/RISCV/invalid-fp-rounding-mode.txt =================================================================== --- llvm/test/MC/Disassembler/RISCV/invalid-fp-rounding-mode.txt +++ llvm/test/MC/Disassembler/RISCV/invalid-fp-rounding-mode.txt @@ -1,5 +1,5 @@ -# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+f,+d < %s 2>&1 | FileCheck %s -# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+f,+d < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+f2p0,+d2p0 < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+f2p0,+d2p0 < %s 2>&1 | FileCheck %s # # Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer # for the RISC-V assembly language. Index: llvm/test/MC/Disassembler/RISCV/invalid-instruction.txt =================================================================== --- llvm/test/MC/Disassembler/RISCV/invalid-instruction.txt +++ llvm/test/MC/Disassembler/RISCV/invalid-instruction.txt @@ -1,5 +1,5 @@ -# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+c < %s 2>&1 | FileCheck %s -# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+c < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+c2p0 < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+c2p0 < %s 2>&1 | FileCheck %s # # Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer # for the RISC-V assembly language. Index: llvm/test/MC/RISCV/align.s =================================================================== --- llvm/test/MC/RISCV/align.s +++ llvm/test/MC/RISCV/align.s @@ -15,17 +15,17 @@ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=NORELAX-RELOC %s # Relaxation enabled with C extension: -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0,+relax < %s \ # RUN: | llvm-objdump -d -M no-aliases - \ # RUN: | FileCheck -check-prefix=C-EXT-RELAX-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0,+relax < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-EXT-RELAX-RELOC %s # Relaxation disabled with C extension: -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0,-relax < %s \ # RUN: | llvm-objdump -d -M no-aliases - \ # RUN: | FileCheck -check-prefix=C-EXT-NORELAX-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0,-relax < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-EXT-NORELAX-RELOC %s # We need to insert N-MinNopSize bytes NOPs and R_RISCV_ALIGN relocation Index: llvm/test/MC/RISCV/attribute-with-option.s =================================================================== --- llvm/test/MC/RISCV/attribute-with-option.s +++ llvm/test/MC/RISCV/attribute-with-option.s @@ -2,11 +2,11 @@ ## architecture attribute, we use the architecture attribute instead of the ## command line option. ## -## This test uses option '-mattr=+e' to specify the "e" extension. However, +## This test uses option '-mattr=+e1p9' to specify the "e" extension. However, ## there is an architecture attribute in the file to specify rv32i. We will ## use rv32i to assemble the file instead of rv32e. -# RUN: llvm-mc %s -triple=riscv32 -mattr=+e -filetype=obj -o - \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+e1p9 -filetype=obj -o - \ # RUN: | llvm-readobj -A - | FileCheck %s .attribute arch, "rv32i2p0" Index: llvm/test/MC/RISCV/cnop.s =================================================================== --- llvm/test/MC/RISCV/cnop.s +++ llvm/test/MC/RISCV/cnop.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0 < %s \ # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=CHECK-INST %s # alpha and main are 8 byte alignment Index: llvm/test/MC/RISCV/compress-cjal.s =================================================================== --- llvm/test/MC/RISCV/compress-cjal.s +++ llvm/test/MC/RISCV/compress-cjal.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding < %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d - \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIASOBJ %s -# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases - \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INSTOBJ %s # c.jal is an rv32 only instruction. Index: llvm/test/MC/RISCV/compress-debug-info.s =================================================================== --- llvm/test/MC/RISCV/compress-debug-info.s +++ llvm/test/MC/RISCV/compress-debug-info.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+c %s -g -o - -riscv-no-aliases \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 %s -g -o - -riscv-no-aliases \ # RUN: | FileCheck %s -check-prefixes=COMPRESS,BOTH # RUN: llvm-mc -triple riscv32 %s -g -o - -riscv-no-aliases \ # RUN: | FileCheck %s -check-prefixes=UNCOMPRESS,BOTH Index: llvm/test/MC/RISCV/compress-rv32d.s =================================================================== --- llvm/test/MC/RISCV/compress-rv32d.s +++ llvm/test/MC/RISCV/compress-rv32d.s @@ -1,23 +1,23 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding < %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0,+d2p0 -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0,+d2p0 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+d -d - \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0,+d2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0,+d2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+d -d -M no-aliases - \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0,+d2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0,+d2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s -# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0,+d2p0 -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0,+d2p0 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s -# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c,+d -d - \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0,+d2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0,+d2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c,+d -d -M no-aliases - \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0,+d2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0,+d2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s # Tests double precision floating point instructions available in rv32 and in rv64. Index: llvm/test/MC/RISCV/compress-rv32f.s =================================================================== --- llvm/test/MC/RISCV/compress-rv32f.s +++ llvm/test/MC/RISCV/compress-rv32f.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding < %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0,+f2p0 -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0,+f2p0 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+f -d - \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0,+f2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0,+f2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+f -d -M no-aliases - \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0,+f2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0,+f2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s # Instructions that are 32 bit only. Index: llvm/test/MC/RISCV/compress-rv32i.s =================================================================== --- llvm/test/MC/RISCV/compress-rv32i.s +++ llvm/test/MC/RISCV/compress-rv32i.s @@ -1,23 +1,23 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding < %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS,CHECK-ALIASASM %s -# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-INSTASM %s -# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d - \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS,CHECK-ALIASOBJ32 %s -# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases - \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INSTOBJ32 %s -# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0 -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK-ALIAS,CHECK-ALIASASM %s -# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST,CHECK-INSTASM %s -# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d - \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS,CHECK-ALIASOBJ64 %s -# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d -M no-aliases - \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INSTOBJ64 %s # CHECK-BYTES: 2e 85 Index: llvm/test/MC/RISCV/compress-rv64i.s =================================================================== --- llvm/test/MC/RISCV/compress-rv64i.s +++ llvm/test/MC/RISCV/compress-rv64i.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0 -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s -# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d - \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s -# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d -M no-aliases - \ +# RUN: llvm-mc -triple riscv64 -mattr=+c2p0 -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s # Tests compressed instructions available in rv64 and not in rv32. Index: llvm/test/MC/RISCV/compressed-relocations.s =================================================================== --- llvm/test/MC/RISCV/compressed-relocations.s +++ llvm/test/MC/RISCV/compressed-relocations.s @@ -1,8 +1,8 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+c -riscv-no-aliases < %s -show-encoding \ +# RUN: llvm-mc -triple riscv32 -mattr=+c2p0 -riscv-no-aliases < %s -show-encoding \ # RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0 < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0,+relax < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s # Check prefixes: Index: llvm/test/MC/RISCV/csr-aliases.s =================================================================== --- llvm/test/MC/RISCV/csr-aliases.s +++ llvm/test/MC/RISCV/csr-aliases.s @@ -1,38 +1,38 @@ -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump -d --mattr=+f2p0 -M no-aliases - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump -d --mattr=+f2p0 - \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump -d --mattr=+f2p0 - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+f2p0 - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \ # RUN: | llvm-objdump -d --mattr=-f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f2p0 < %s \ # RUN: | llvm-objdump -d --mattr=-f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump -d --mattr=+f2p0 -M no-aliases - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump -d --mattr=+f2p0 - \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump -d --mattr=+f2p0 - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F %s # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: | llvm-objdump -d --mattr=+f2p0 - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F %s # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \ # RUN: | llvm-objdump -d --mattr=-f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f2p0 < %s \ # RUN: | llvm-objdump -d --mattr=-f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s @@ -114,4 +114,3 @@ # CHECK-EXT-F: fsflagsi 31 # CHECK-EXT-F-OFF: csrwi fflags, 31 csrrwi zero, 1, 31 - Index: llvm/test/MC/RISCV/elf-flags.s =================================================================== --- llvm/test/MC/RISCV/elf-flags.s +++ llvm/test/MC/RISCV/elf-flags.s @@ -1,8 +1,8 @@ # RUN: llvm-mc -triple=riscv32 -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVI %s # RUN: llvm-mc -triple=riscv64 -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVI %s -# RUN: llvm-mc -triple=riscv32 -mattr=+c -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVIC %s -# RUN: llvm-mc -triple=riscv64 -mattr=+c -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVIC %s -# RUN: llvm-mc -triple=riscv32 -mattr=+e -filetype=obj < %s \ +# RUN: llvm-mc -triple=riscv32 -mattr=+c2p0 -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVIC %s +# RUN: llvm-mc -triple=riscv64 -mattr=+c2p0 -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVIC %s +# RUN: llvm-mc -triple=riscv32 -mattr=+e1p9 -filetype=obj < %s \ # RUN: | llvm-readobj --file-headers - \ # RUN: | FileCheck -check-prefix=CHECK-RVE %s Index: llvm/test/MC/RISCV/fixups-compressed.s =================================================================== --- llvm/test/MC/RISCV/fixups-compressed.s +++ llvm/test/MC/RISCV/fixups-compressed.s @@ -1,8 +1,8 @@ -# RUN: llvm-mc %s -triple riscv32 -mattr=+c -show-encoding \ +# RUN: llvm-mc %s -triple riscv32 -mattr=+c2p0 -show-encoding \ # RUN: | FileCheck -check-prefix=CHECK-FIXUP %s -# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \ +# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c2p0 < %s \ # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=CHECK-INSTR %s -# RUN: llvm-mc -filetype=obj -mattr=+c -triple=riscv32 %s \ +# RUN: llvm-mc -filetype=obj -mattr=+c2p0 -triple=riscv32 %s \ # RUN: | llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL .LBB0_2: Index: llvm/test/MC/RISCV/insn.s =================================================================== --- llvm/test/MC/RISCV/insn.s +++ llvm/test/MC/RISCV/insn.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+f2p0 -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM %s -# RUN: llvm-mc %s -triple riscv64 -mattr=+f -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple riscv64 -mattr=+f2p0 -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump --mattr=+f -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump --mattr=+f2p0 -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump --mattr=+f -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump --mattr=+f2p0 -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ %s target: Index: llvm/test/MC/RISCV/invalid-instruction-spellcheck.s =================================================================== --- llvm/test/MC/RISCV/invalid-instruction-spellcheck.s +++ llvm/test/MC/RISCV/invalid-instruction-spellcheck.s @@ -2,9 +2,9 @@ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV32,CHECK-RV32I %s # RUN: not llvm-mc -triple=riscv64 < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV64,CHECK-RV64I %s -# RUN: not llvm-mc -triple=riscv32 -mattr=+f < %s 2>&1 \ +# RUN: not llvm-mc -triple=riscv32 -mattr=+f2p0 < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV32,CHECK-RV32IF %s -# RUN: not llvm-mc -triple=riscv64 -mattr=+f < %s 2>&1 \ +# RUN: not llvm-mc -triple=riscv64 -mattr=+f2p0 < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV64,CHECK-RV64IF %s # Tests for the mnemonic spell checker. Suggestions should only include those Index: llvm/test/MC/RISCV/mattr-invalid-combination.s =================================================================== --- llvm/test/MC/RISCV/mattr-invalid-combination.s +++ llvm/test/MC/RISCV/mattr-invalid-combination.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \ +# RUN: not --crash llvm-mc -triple riscv64 -mattr=+e1p9 < %s 2>&1 \ # RUN: | FileCheck %s -check-prefix=RV64E # RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target Index: llvm/test/MC/RISCV/numeric-reg-names-d.s =================================================================== --- llvm/test/MC/RISCV/numeric-reg-names-d.s +++ llvm/test/MC/RISCV/numeric-reg-names-d.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+f,+d -M numeric < %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+f2p0,+d2p0 -M numeric < %s \ # RUN: | FileCheck -check-prefix=CHECK-NUMERIC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+d < %s \ -# RUN: | llvm-objdump --mattr=+f,+d -d -M numeric - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f2p0,+d2p0 < %s \ +# RUN: | llvm-objdump --mattr=+f2p0,+d2p0 -d -M numeric - \ # RUN: | FileCheck -check-prefix=CHECK-NUMERIC %s # CHECK-NUMERIC: fsqrt.d f10, f0 Index: llvm/test/MC/RISCV/numeric-reg-names-f.s =================================================================== --- llvm/test/MC/RISCV/numeric-reg-names-f.s +++ llvm/test/MC/RISCV/numeric-reg-names-f.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+f -M numeric < %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+f2p0 -M numeric < %s \ # RUN: | FileCheck -check-prefix=CHECK-NUMERIC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump --mattr=+f -d -M numeric - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f2p0 < %s \ +# RUN: | llvm-objdump --mattr=+f2p0 -d -M numeric - \ # RUN: | FileCheck -check-prefix=CHECK-NUMERIC %s # CHECK-NUMERIC: fsqrt.s f10, f0 Index: llvm/test/MC/RISCV/option-pushpop.s =================================================================== --- llvm/test/MC/RISCV/option-pushpop.s +++ llvm/test/MC/RISCV/option-pushpop.s @@ -3,7 +3,7 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s # RUN: llvm-mc -triple riscv32 -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d - \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s # RUN: llvm-mc -triple riscv64 -mattr=-relax -riscv-no-aliases < %s \ @@ -11,7 +11,7 @@ # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s # RUN: llvm-mc -triple riscv64 -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d - \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s # Test the operation of the push and pop assembler directives when Index: llvm/test/MC/RISCV/option-rvc.s =================================================================== --- llvm/test/MC/RISCV/option-rvc.s +++ llvm/test/MC/RISCV/option-rvc.s @@ -3,10 +3,10 @@ # RUN: llvm-mc -triple riscv32 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s # RUN: llvm-mc -triple riscv32 -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d - \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s # RUN: llvm-mc -triple riscv32 -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases - \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s # RUN: llvm-mc -triple riscv64 -show-encoding < %s \ @@ -14,10 +14,10 @@ # RUN: llvm-mc -triple riscv64 -show-encoding \ # RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s # RUN: llvm-mc -triple riscv64 -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d - \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0 -d - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s # RUN: llvm-mc -triple riscv64 -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d -M no-aliases - \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+c2p0 -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s # CHECK-BYTES: 13 85 05 00 Index: llvm/test/MC/RISCV/relocations.s =================================================================== --- llvm/test/MC/RISCV/relocations.s +++ llvm/test/MC/RISCV/relocations.s @@ -1,6 +1,6 @@ # RUN: llvm-mc -triple riscv32 -riscv-no-aliases < %s -show-encoding \ # RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0 < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s # Check prefixes: Index: llvm/test/MC/RISCV/rv32-relaxation.s =================================================================== --- llvm/test/MC/RISCV/rv32-relaxation.s +++ llvm/test/MC/RISCV/rv32-relaxation.s @@ -1,8 +1,8 @@ -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0 < %s \ # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=INSTR %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0,+relax < %s \ # RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=RELAX-INSTR %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c2p0,+relax < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELAX-RELOC %s FAR_JUMP_NEGATIVE: Index: llvm/test/MC/RISCV/rv32a-invalid.s =================================================================== --- llvm/test/MC/RISCV/rv32a-invalid.s +++ llvm/test/MC/RISCV/rv32a-invalid.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv32 -mattr=+a2p0 < %s 2>&1 | FileCheck %s # Final operand must have parentheses amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset Index: llvm/test/MC/RISCV/rv32a-valid.s =================================================================== --- llvm/test/MC/RISCV/rv32a-valid.s +++ llvm/test/MC/RISCV/rv32a-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+a2p0 -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+a2p0 -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \ -# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a2p0 < %s \ +# RUN: | llvm-objdump --mattr=+a2p0 -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \ -# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a2p0 < %s \ +# RUN: | llvm-objdump --mattr=+a2p0 -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: lr.w t0, (t1) Index: llvm/test/MC/RISCV/rv32c-aliases-valid.s =================================================================== --- llvm/test/MC/RISCV/rv32c-aliases-valid.s +++ llvm/test/MC/RISCV/rv32c-aliases-valid.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc -triple=riscv32 -mattr