diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -252,6 +252,10 @@ errs() << "Hard-float 'd' ABI can't be used for a target that " "doesn't support the D instruction set extension (ignoring " "target-abi)\n"; + } else if (!ABIName.endswith("e") && + getSTI().getFeatureBits()[RISCV::FeatureRV32E]) { + errs() << "Only the ilp32e ABI is supported for RV32E (ignoring " + "target-abi)\n"; } const MCObjectFileInfo *MOFI = Parser.getContext().getObjectFileInfo(); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -51,11 +51,6 @@ errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " "target-abi)\n"; TargetABI = ABI_Unknown; - } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { - // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser - errs() - << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; - TargetABI = ABI_Unknown; } if (TargetABI != ABI_Unknown) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -66,6 +66,10 @@ "doesn't support the D instruction set extension (ignoring " "target-abi)\n"; ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; + } else if (Subtarget.isRV32E() && ABI != RISCVABI::ABI_ILP32E) { + errs() << "Only the ilp32e ABI is supported for RV32E (ignoring " + "target-abi)\n"; + ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; } switch (ABI) {