diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18280,8 +18280,8 @@
   if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
     if (ST->isUnindexed() && ST->isSimple() &&
         ST1->isUnindexed() && ST1->isSimple()) {
-      if (ST1->getBasePtr() == Ptr && ST1->getValue() == Value &&
-          ST->getMemoryVT() == ST1->getMemoryVT() &&
+      if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr &&
+          ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() &&
           ST->getAddressSpace() == ST1->getAddressSpace()) {
         // If this is a store followed by a store with the same value to the
         // same location, then the store is dead/noop.
diff --git a/llvm/test/CodeGen/RISCV/dbg-combine.ll b/llvm/test/CodeGen/RISCV/dbg-combine.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/dbg-combine.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
+
+; Make sure that the sequence of store instructions for function foo is correctly
+; generated. More specifically, `sw a0, -20(s0)` instruction sequences must appear in
+; the output assembly.
+
+; cat dbg-combine.c
+; 1 int main ()
+; 2 {
+; 3   int size;
+; 4
+; 5   size = (int) sizeof (long long);
+; 6   size = (int) sizeof (void*);
+; 7   size = (int) sizeof (void (*)(void));
+; 8
+; 9   return 0;
+; 10 }
+
+define dso_local signext i32 @foo() #0 {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    addi s0, sp, 32
+; CHECK-NEXT:    li a0, 8
+; CHECK-NEXT:    sw a0, -20(s0)
+; CHECK-NEXT:    sw a0, -20(s0)
+; CHECK-NEXT:    sw a0, -20(s0)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+entry:
+  %size = alloca i32, align 4
+  store i32 8, i32* %size, align 4
+  store i32 8, i32* %size, align 4
+  store i32 8, i32* %size, align 4
+  ret i32 0
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+a,+c,+m,+relax,-save-restore" }
+