diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -89,30 +89,24 @@
 
   friend class SIMemOpAccess;
 
-  AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
-  AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic;
-  SIAtomicScope Scope = SIAtomicScope::SYSTEM;
-  SIAtomicAddrSpace OrderingAddrSpace = SIAtomicAddrSpace::NONE;
-  SIAtomicAddrSpace InstrAddrSpace = SIAtomicAddrSpace::NONE;
-  bool IsCrossAddressSpaceOrdering = false;
-  bool IsVolatile = false;
-  bool IsNonTemporal = false;
-
-  SIMemOpInfo(AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent,
-              SIAtomicScope Scope = SIAtomicScope::SYSTEM,
-              SIAtomicAddrSpace OrderingAddrSpace = SIAtomicAddrSpace::ATOMIC,
-              SIAtomicAddrSpace InstrAddrSpace = SIAtomicAddrSpace::ALL,
-              bool IsCrossAddressSpaceOrdering = true,
-              AtomicOrdering FailureOrdering =
-                AtomicOrdering::SequentiallyConsistent,
-              bool IsVolatile = false,
-              bool IsNonTemporal = false)
-    : Ordering(Ordering), FailureOrdering(FailureOrdering),
-      Scope(Scope), OrderingAddrSpace(OrderingAddrSpace),
-      InstrAddrSpace(InstrAddrSpace),
-      IsCrossAddressSpaceOrdering(IsCrossAddressSpaceOrdering),
-      IsVolatile(IsVolatile),
-      IsNonTemporal(IsNonTemporal) {
+  AtomicOrdering Ordering;
+  AtomicOrdering FailureOrdering;
+  SIAtomicScope Scope;
+  SIAtomicAddrSpace OrderingAddrSpace;
+  SIAtomicAddrSpace InstrAddrSpace;
+  bool IsCrossAddressSpaceOrdering;
+  bool IsVolatile;
+  bool IsNonTemporal;
+
+  SIMemOpInfo(AtomicOrdering Ordering, SIAtomicScope Scope,
+              SIAtomicAddrSpace OrderingAddrSpace,
+              SIAtomicAddrSpace InstrAddrSpace,
+              bool IsCrossAddressSpaceOrdering, AtomicOrdering FailureOrdering,
+              bool IsVolatile = false, bool IsNonTemporal = false)
+      : Ordering(Ordering), FailureOrdering(FailureOrdering), Scope(Scope),
+        OrderingAddrSpace(OrderingAddrSpace), InstrAddrSpace(InstrAddrSpace),
+        IsCrossAddressSpaceOrdering(IsCrossAddressSpaceOrdering),
+        IsVolatile(IsVolatile), IsNonTemporal(IsNonTemporal) {
 
     if (Ordering == AtomicOrdering::NotAtomic) {
       assert(Scope == SIAtomicScope::NONE &&
@@ -688,10 +682,6 @@
   if (!(MI->mayLoad() && !MI->mayStore()))
     return None;
 
-  // Be conservative if there are no memory operands.
-  if (MI->getNumMemOperands() == 0)
-    return SIMemOpInfo();
-
   return constructFromMIWithMMO(MI);
 }
 
@@ -702,10 +692,6 @@
   if (!(!MI->mayLoad() && MI->mayStore()))
     return None;
 
-  // Be conservative if there are no memory operands.
-  if (MI->getNumMemOperands() == 0)
-    return SIMemOpInfo();
-
   return constructFromMIWithMMO(MI);
 }
 
@@ -749,10 +735,6 @@
   if (!(MI->mayLoad() && MI->mayStore()))
     return None;
 
-  // Be conservative if there are no memory operands.
-  if (MI->getNumMemOperands() == 0)
-    return SIMemOpInfo();
-
   return constructFromMIWithMMO(MI);
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir b/llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
--- a/llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
+++ b/llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
@@ -53,49 +53,49 @@
     %28:vgpr_32 = COPY %23.sub13
     %29:vgpr_32 = COPY %23.sub12
     %30:vreg_128 = REG_SEQUENCE killed %29, %subreg.sub0, killed %28, %subreg.sub1, killed %27, %subreg.sub2, killed %26, %subreg.sub3
-    GLOBAL_STORE_DWORDX4_SADDR %1, killed %30, %2, 48, 0, implicit $exec
+    GLOBAL_STORE_DWORDX4_SADDR %1, killed %30, %2, 48, 0, implicit $exec :: (store 16)
     %31:vgpr_32 = COPY %23.sub11
     %32:vgpr_32 = COPY %23.sub10
     %33:vgpr_32 = COPY %23.sub9
     %34:vgpr_32 = COPY %23.sub8
     %35:vreg_128 = REG_SEQUENCE killed %34, %subreg.sub0, killed %33, %subreg.sub1, killed %32, %subreg.sub2, killed %31, %subreg.sub3
-    GLOBAL_STORE_DWORDX4_SADDR %1, killed %35, %2, 32, 0, implicit $exec
+    GLOBAL_STORE_DWORDX4_SADDR %1, killed %35, %2, 32, 0, implicit $exec :: (store 16)
     %36:vgpr_32 = COPY %23.sub7
     %37:vgpr_32 = COPY %23.sub6
     %38:vgpr_32 = COPY %23.sub5
     %39:vgpr_32 = COPY %23.sub4
     %40:vreg_128 = REG_SEQUENCE killed %39, %subreg.sub0, killed %38, %subreg.sub1, killed %37, %subreg.sub2, killed %36, %subreg.sub3
-    GLOBAL_STORE_DWORDX4_SADDR %1, killed %40, %2, 16, 0, implicit $exec
+    GLOBAL_STORE_DWORDX4_SADDR %1, killed %40, %2, 16, 0, implicit $exec :: (store 16)
     %41:vgpr_32 = COPY %23.sub3
     %42:vgpr_32 = COPY %23.sub2
     %43:vgpr_32 = COPY %23.sub1
     %44:vgpr_32 = COPY killed %23.sub0
     %45:vreg_128 = REG_SEQUENCE killed %44, %subreg.sub0, killed %43, %subreg.sub1, killed %42, %subreg.sub2, killed %41, %subreg.sub3
-    GLOBAL_STORE_DWORDX4_SADDR %1, killed %45, %2, 0, 0, implicit $exec
+    GLOBAL_STORE_DWORDX4_SADDR %1, killed %45, %2, 0, 0, implicit $exec :: (store 16)
     %46:vgpr_32 = COPY %25.sub15
     %47:vgpr_32 = COPY %25.sub14
     %48:vgpr_32 = COPY %25.sub13
     %49:vgpr_32 = COPY %25.sub12
     %50:vreg_128 = REG_SEQUENCE killed %49, %subreg.sub0, killed %48, %subreg.sub1, killed %47, %subreg.sub2, killed %46, %subreg.sub3
-    GLOBAL_STORE_DWORDX4_SADDR %1, killed %50, %2, 112, 0, implicit $exec
+    GLOBAL_STORE_DWORDX4_SADDR %1, killed %50, %2, 112, 0, implicit $exec :: (store 16)
     %51:vgpr_32 = COPY %25.sub11
     %52:vgpr_32 = COPY %25.sub10
     %53:vgpr_32 = COPY %25.sub9
     %54:vgpr_32 = COPY %25.sub8
     %55:vreg_128 = REG_SEQUENCE killed %54, %subreg.sub0, killed %53, %subreg.sub1, killed %52, %subreg.sub2, killed %51, %subreg.sub3
-    GLOBAL_STORE_DWORDX4_SADDR %1, killed %55, %2, 96, 0, implicit $exec
+    GLOBAL_STORE_DWORDX4_SADDR %1, killed %55, %2, 96, 0, implicit $exec :: (store 16)
     %56:vgpr_32 = COPY %25.sub7
     %57:vgpr_32 = COPY %25.sub6
     %58:vgpr_32 = COPY %25.sub5
     %59:vgpr_32 = COPY %25.sub4
     %60:vreg_128 = REG_SEQUENCE killed %59, %subreg.sub0, killed %58, %subreg.sub1, killed %57, %subreg.sub2, killed %56, %subreg.sub3
-    GLOBAL_STORE_DWORDX4_SADDR %1, killed %60, %2, 80, 0, implicit $exec
+    GLOBAL_STORE_DWORDX4_SADDR %1, killed %60, %2, 80, 0, implicit $exec :: (store 16)
     %61:vgpr_32 = COPY %25.sub3
     %62:vgpr_32 = COPY %25.sub2
     %63:vgpr_32 = COPY %25.sub1
     %64:vgpr_32 = COPY killed %25.sub0
     %65:vreg_128 = REG_SEQUENCE killed %64, %subreg.sub0, killed %63, %subreg.sub1, killed %62, %subreg.sub2, killed %61, %subreg.sub3
-    GLOBAL_STORE_DWORDX4_SADDR killed %1, killed %65, killed %2, 64, 0, implicit $exec
+    GLOBAL_STORE_DWORDX4_SADDR killed %1, killed %65, killed %2, 64, 0, implicit $exec :: (store 16)
     S_ENDPGM 0
 
 ...
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir
--- a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir
@@ -21,7 +21,7 @@
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
     %4, %5 = V_SUBBREV_U32_e64 0, %0, %3, 0, implicit $exec
-    GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
+    GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec :: (store 4)
 
 ...
 
@@ -46,7 +46,7 @@
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
     %4, %5 = V_SUBB_U32_e64 %0, 0, %3, 0, implicit $exec
-    GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
+    GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec :: (store 4)
 
 ...
 
@@ -71,7 +71,7 @@
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
     %4, %5 = V_ADDC_U32_e64 0, %0, %3, 0, implicit $exec
-    GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
+    GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec :: (store 4)
 
 ...
 
@@ -96,6 +96,6 @@
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
     %4, %5 = V_ADDC_U32_e64 %0, 0, %3, 0, implicit $exec
-    GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
+    GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec :: (store 4)
 
 ...
diff --git a/llvm/test/CodeGen/AMDGPU/subvector-test.mir b/llvm/test/CodeGen/AMDGPU/subvector-test.mir
--- a/llvm/test/CodeGen/AMDGPU/subvector-test.mir
+++ b/llvm/test/CodeGen/AMDGPU/subvector-test.mir
@@ -31,6 +31,6 @@
 
   bb.2:
 
-    GLOBAL_STORE_DWORD %15, %16, 0, 0, implicit $exec
+    GLOBAL_STORE_DWORD %15, %16, 0, 0, implicit $exec :: (store 4)
     S_ENDPGM 0
 ...