diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -260,10 +260,10 @@
 // Pseudo instructions used by address sanitizer.
 //===----------------------------------------------------------------------===//
 let
-  Defs = [R8, EFLAGS] in {
+  Defs = [R10, R11, EFLAGS] in {
 def ASAN_CHECK_MEMACCESS : PseudoI<
-  (outs), (ins GR64NoR8:$addr, i32imm:$accessinfo),
-  [(int_asan_check_memaccess GR64NoR8:$addr, (i32 timm:$accessinfo))]>,
+  (outs), (ins GR64PLTSafe:$addr, i32imm:$accessinfo),
+  [(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>,
   Sched<[]>;
 }
 
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1359,7 +1359,8 @@
                                              MCSubtargetInfo &STI) {
   assert(AccessInfo.AccessSizeIndex == 0 || AccessInfo.AccessSizeIndex == 1 ||
          AccessInfo.AccessSizeIndex == 2);
-  assert(Reg != X86::R8);
+  assert(Reg != X86::R10);
+  assert(Reg != X86::R11);
 
   uint64_t ShadowBase;
   int MappingScale;
@@ -1368,41 +1369,42 @@
       Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(),
       AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset);
 
-  OutStreamer->emitInstruction(
-      MCInstBuilder(X86::MOV64rr).addReg(X86::R8).addReg(X86::NoRegister + Reg),
-      STI);
+  OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
+                                   .addReg(X86::R10)
+                                   .addReg(X86::NoRegister + Reg),
+                               STI);
   OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
-                                   .addReg(X86::R8)
-                                   .addReg(X86::R8)
+                                   .addReg(X86::R10)
+                                   .addReg(X86::R10)
                                    .addImm(MappingScale),
                                STI);
   if (OrShadowOffset) {
     OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
-                                     .addReg(X86::R8)
-                                     .addReg(X86::R8)
+                                     .addReg(X86::R10)
+                                     .addReg(X86::R10)
                                      .addImm(ShadowBase),
                                  STI);
     OutStreamer->emitInstruction(MCInstBuilder(X86::MOV8rm)
-                                     .addReg(X86::R8B)
-                                     .addReg(X86::R8)
+                                     .addReg(X86::R10B)
+                                     .addReg(X86::R10)
                                      .addImm(1)
                                      .addReg(X86::NoRegister)
                                      .addImm(0)
                                      .addReg(X86::NoRegister),
                                  STI);
     OutStreamer->emitInstruction(
-        MCInstBuilder(X86::TEST8rr).addReg(X86::R8B).addReg(X86::R8B), STI);
+        MCInstBuilder(X86::TEST8rr).addReg(X86::R10B).addReg(X86::R10B), STI);
   } else {
     OutStreamer->emitInstruction(MCInstBuilder(X86::MOVSX32rm8)
-                                     .addReg(X86::R8D)
-                                     .addReg(X86::R8)
+                                     .addReg(X86::R10D)
+                                     .addReg(X86::R10)
                                      .addImm(1)
                                      .addReg(X86::NoRegister)
                                      .addImm(ShadowBase)
                                      .addReg(X86::NoRegister),
                                  STI);
     OutStreamer->emitInstruction(
-        MCInstBuilder(X86::TEST32rr).addReg(X86::R8D).addReg(X86::R8D), STI);
+        MCInstBuilder(X86::TEST32rr).addReg(X86::R10D).addReg(X86::R10D), STI);
   }
   MCSymbol *AdditionalCheck = OutContext.createTempSymbol();
   OutStreamer->emitInstruction(
@@ -1416,37 +1418,33 @@
 
   // Shadow byte is non-zero so we need to perform additional checks.
   OutStreamer->emitLabel(AdditionalCheck);
-  OutStreamer->emitInstruction(MCInstBuilder(X86::PUSH64r).addReg(X86::RCX),
-                               STI);
   OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
-                                   .addReg(X86::RCX)
+                                   .addReg(X86::R11)
                                    .addReg(X86::NoRegister + Reg),
                                STI);
   const size_t Granularity = 1ULL << MappingScale;
   OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8)
                                    .addReg(X86::NoRegister)
-                                   .addReg(X86::ECX)
+                                   .addReg(X86::R11D)
                                    .addImm(Granularity - 1),
                                STI);
   if (AccessInfo.AccessSizeIndex == 1) {
     OutStreamer->emitInstruction(MCInstBuilder(X86::ADD32ri8)
                                      .addReg(X86::NoRegister)
-                                     .addReg(X86::ECX)
+                                     .addReg(X86::R11D)
                                      .addImm(1),
                                  STI);
   } else if (AccessInfo.AccessSizeIndex == 2) {
     OutStreamer->emitInstruction(MCInstBuilder(X86::ADD32ri8)
                                      .addReg(X86::NoRegister)
-                                     .addReg(X86::ECX)
+                                     .addReg(X86::R11D)
                                      .addImm(3),
                                  STI);
   }
 
   OutStreamer->emitInstruction(
-      MCInstBuilder(X86::CMP32rr).addReg(X86::ECX).addReg(X86::R8D).addImm(1),
+      MCInstBuilder(X86::CMP32rr).addReg(X86::R11D).addReg(X86::R10D).addImm(1),
       STI);
-  OutStreamer->emitInstruction(MCInstBuilder(X86::POP64r).addReg(X86::RCX),
-                               STI);
   OutStreamer->emitInstruction(
       MCInstBuilder(X86::JCC_1)
           .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext))
@@ -1460,7 +1458,8 @@
                                           const ASanAccessInfo &AccessInfo,
                                           MCSubtargetInfo &STI) {
   assert(AccessInfo.AccessSizeIndex == 3 || AccessInfo.AccessSizeIndex == 4);
-  assert(Reg != X86::R8);
+  assert(Reg != X86::R10);
+  assert(Reg != X86::R11);
 
   uint64_t ShadowBase;
   int MappingScale;
@@ -1469,23 +1468,24 @@
       Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(),
       AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset);
 
-  OutStreamer->emitInstruction(
-      MCInstBuilder(X86::MOV64rr).addReg(X86::R8).addReg(X86::NoRegister + Reg),
-      STI);
+  OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
+                                   .addReg(X86::R10)
+                                   .addReg(X86::NoRegister + Reg),
+                               STI);
   OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
-                                   .addReg(X86::R8)
-                                   .addReg(X86::R8)
+                                   .addReg(X86::R10)
+                                   .addReg(X86::R10)
                                    .addImm(MappingScale),
                                STI);
   if (OrShadowOffset) {
     OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
-                                     .addReg(X86::R8)
-                                     .addReg(X86::R8)
+                                     .addReg(X86::R10)
+                                     .addReg(X86::R10)
                                      .addImm(ShadowBase),
                                  STI);
     auto OpCode = AccessInfo.AccessSizeIndex == 3 ? X86::CMP8mi : X86::CMP16mi8;
     OutStreamer->emitInstruction(MCInstBuilder(OpCode)
-                                     .addReg(X86::R8)
+                                     .addReg(X86::R10)
                                      .addImm(1)
                                      .addReg(X86::NoRegister)
                                      .addImm(0)
@@ -1495,7 +1495,7 @@
   } else {
     auto OpCode = AccessInfo.AccessSizeIndex == 3 ? X86::CMP8mi : X86::CMP16mi8;
     OutStreamer->emitInstruction(MCInstBuilder(OpCode)
-                                     .addReg(X86::R8)
+                                     .addReg(X86::R10)
                                      .addImm(1)
                                      .addReg(X86::NoRegister)
                                      .addImm(ShadowBase)
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -430,11 +430,11 @@
                          (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
                               RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
 
-// GR64 - 64-bit GPRs without R8 and RIP. Could be used when emitting code for
-// intrinsics, which use implict input registers.
-def GR64NoR8 : RegisterClass<"X86", [i64], 64,
-                              (add RAX, RCX, RDX, RSI, RDI, R9, R10, R11,
-                                   RBX, R14, R15, R12, R13, RBP, RSP)>;
+// GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
+// emitting code for intrinsics, which use implict input registers.
+def GR64PLTSafe : RegisterClass<"X86", [i64], 64,
+                              (add RAX, RCX, RDX, RSI, RDI, R8, R9,
+                                   RBX, R14, R15, R12, R13, RBP)>;
 
 // Segment registers for use by MOV instructions (and others) that have a
 //   segment register as one operand.  Always contain a 16-bit segment
diff --git a/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll b/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
--- a/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
+++ b/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
@@ -73,19 +73,17 @@
 ; CHECK-NEXT:         .weak   __asan_check_load1_rn[[RN1]]
 ; CHECK-NEXT:         .hidden __asan_check_load1_rn[[RN1]]
 ; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         movsbl  2147450880(%r8), %r8d
-; CHECK-NEXT:         testl   %r8d, %r8d
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         movsbl  2147450880(%r10), %r10d
+; CHECK-NEXT:         testl   %r10d, %r10d
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_load1
@@ -94,20 +92,18 @@
 ; CHECK-NEXT:         .weak   __asan_check_load2_rn[[RN2]]
 ; CHECK-NEXT:         .hidden __asan_check_load2_rn[[RN2]]
 ; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         movsbl  2147450880(%r8), %r8d
-; CHECK-NEXT:         testl   %r8d, %r8d
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         movsbl  2147450880(%r10), %r10d
+; CHECK-NEXT:         testl   %r10d, %r10d
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         addl    $1, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         addl    $1, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_load2
@@ -116,20 +112,18 @@
 ; CHECK-NEXT:         .weak   __asan_check_load4_rn[[RN4]]
 ; CHECK-NEXT:         .hidden __asan_check_load4_rn[[RN4]]
 ; CHECK-NEXT: __asan_check_load4_rn[[RN4]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         movsbl  2147450880(%r8), %r8d
-; CHECK-NEXT:         testl   %r8d, %r8d
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         movsbl  2147450880(%r10), %r10d
+; CHECK-NEXT:         testl   %r10d, %r10d
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         addl    $3, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         addl    $3, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_load4
@@ -138,9 +132,9 @@
 ; CHECK-NEXT:         .weak   __asan_check_load8_rn[[RN8]]
 ; CHECK-NEXT:         .hidden __asan_check_load8_rn[[RN8]]
 ; CHECK-NEXT: __asan_check_load8_rn[[RN8]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         cmpb    $0, 2147450880(%r8)
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         cmpb    $0, 2147450880(%r10)
 ; CHECK-NEXT:         jne     [[FAIL:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
@@ -152,9 +146,9 @@
 ; CHECK-NEXT:         .weak   __asan_check_load16_rn[[RN16]]
 ; CHECK-NEXT:         .hidden __asan_check_load16_rn[[RN16]]
 ; CHECK-NEXT: __asan_check_load16_rn[[RN16]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         cmpw    $0, 2147450880(%r8)
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         cmpw    $0, 2147450880(%r10)
 ; CHECK-NEXT:         jne     [[FAIL:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
@@ -166,19 +160,17 @@
 ; CHECK-NEXT:         .weak   __asan_check_store1_rn[[RN1]]
 ; CHECK-NEXT:         .hidden __asan_check_store1_rn[[RN1]]
 ; CHECK-NEXT: __asan_check_store1_rn[[RN1]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         movsbl  2147450880(%r8), %r8d
-; CHECK-NEXT:         testl   %r8d, %r8d
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         movsbl  2147450880(%r10), %r10d
+; CHECK-NEXT:         testl   %r10d, %r10d
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_store1@PLT
@@ -187,20 +179,18 @@
 ; CHECK-NEXT:         .weak   __asan_check_store2_rn[[RN2]]
 ; CHECK-NEXT:         .hidden __asan_check_store2_rn[[RN2]]
 ; CHECK-NEXT: __asan_check_store2_rn[[RN2]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         movsbl  2147450880(%r8), %r8d
-; CHECK-NEXT:         testl   %r8d, %r8d
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         movsbl  2147450880(%r10), %r10d
+; CHECK-NEXT:         testl   %r10d, %r10d
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         addl    $1, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         addl    $1, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_store2@PLT
@@ -209,20 +199,18 @@
 ; CHECK-NEXT:         .weak   __asan_check_store4_rn[[RN4]]
 ; CHECK-NEXT:         .hidden __asan_check_store4_rn[[RN4]]
 ; CHECK-NEXT: __asan_check_store4_rn[[RN4]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         movsbl  2147450880(%r8), %r8d
-; CHECK-NEXT:         testl   %r8d, %r8d
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         movsbl  2147450880(%r10), %r10d
+; CHECK-NEXT:         testl   %r10d, %r10d
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         addl    $3, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         addl    $3, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_store4@PLT
@@ -231,9 +219,9 @@
 ; CHECK-NEXT:         .weak   __asan_check_store8_rn[[RN8]]
 ; CHECK-NEXT:         .hidden __asan_check_store8_rn[[RN8]]
 ; CHECK-NEXT: __asan_check_store8_rn[[RN8]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         cmpb    $0, 2147450880(%r8)
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         cmpb    $0, 2147450880(%r10)
 ; CHECK-NEXT:         jne     [[FAIL:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
@@ -245,9 +233,9 @@
 ; CHECK-NEXT:         .weak   __asan_check_store16_rn[[RN16]]
 ; CHECK-NEXT:         .hidden __asan_check_store16_rn[[RN16]]
 ; CHECK-NEXT: __asan_check_store16_rn[[RN16]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         cmpw    $0, 2147450880(%r8)
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         cmpw    $0, 2147450880(%r10)
 ; CHECK-NEXT:         jne     [[FAIL:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
diff --git a/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll b/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
--- a/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
+++ b/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -73,20 +73,18 @@
 ; CHECK-NEXT:         .weak   __asan_check_load1_rn[[RN1]]
 ; CHECK-NEXT:         .hidden __asan_check_load1_rn[[RN1]]
 ; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8{{.*}}
-; CHECK-NEXT:         movb    (%r8), %r8b
-; CHECK-NEXT:         testb   %r8b, %r8b
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10{{.*}}
+; CHECK-NEXT:         movb    (%r10), %r10b
+; CHECK-NEXT:         testb   %r10b, %r10b
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_load1
@@ -95,21 +93,19 @@
 ; CHECK-NEXT:         .weak   __asan_check_load2_rn[[RN2]]
 ; CHECK-NEXT:         .hidden __asan_check_load2_rn[[RN2]]
 ; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8{{.*}}
-; CHECK-NEXT:         movb    (%r8), %r8b
-; CHECK-NEXT:         testb   %r8b, %r8b
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10{{.*}}
+; CHECK-NEXT:         movb    (%r10), %r10b
+; CHECK-NEXT:         testb   %r10b, %r10b
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         addl    $1, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         addl    $1, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_load2
@@ -118,21 +114,19 @@
 ; CHECK-NEXT:         .weak   __asan_check_load4_rn[[RN4]]
 ; CHECK-NEXT:         .hidden __asan_check_load4_rn[[RN4]]
 ; CHECK-NEXT: __asan_check_load4_rn[[RN4]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8{{.*}}
-; CHECK-NEXT:         movb    (%r8), %r8b
-; CHECK-NEXT:         testb   %r8b, %r8b
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10{{.*}}
+; CHECK-NEXT:         movb    (%r10), %r10b
+; CHECK-NEXT:         testb   %r10b, %r10b
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         addl    $3, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         addl    $3, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_load4
@@ -141,10 +135,10 @@
 ; CHECK-NEXT:         .weak   __asan_check_load8_rn[[RN8]]
 ; CHECK-NEXT:         .hidden __asan_check_load8_rn[[RN8]]
 ; CHECK-NEXT: __asan_check_load8_rn[[RN8]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8{{.*}}
-; CHECK-NEXT:         cmpb    $0, (%r8)
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10{{.*}}
+; CHECK-NEXT:         cmpb    $0, (%r10)
 ; CHECK-NEXT:         jne     [[FAIL:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
@@ -156,10 +150,10 @@
 ; CHECK-NEXT:         .weak   __asan_check_load16_rn[[RN16]]
 ; CHECK-NEXT:         .hidden __asan_check_load16_rn[[RN16]]
 ; CHECK-NEXT: __asan_check_load16_rn[[RN16]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8{{.*}}
-; CHECK-NEXT:         cmpw    $0, (%r8)
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10{{.*}}
+; CHECK-NEXT:         cmpw    $0, (%r10)
 ; CHECK-NEXT:         jne     [[FAIL:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
@@ -171,20 +165,18 @@
 ; CHECK-NEXT:         .weak   __asan_check_store1_rn[[RN1]]
 ; CHECK-NEXT:         .hidden __asan_check_store1_rn[[RN1]]
 ; CHECK-NEXT: __asan_check_store1_rn[[RN1]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8
-; CHECK-NEXT:         movb    (%r8), %r8b
-; CHECK-NEXT:         testb   %r8b, %r8b
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10
+; CHECK-NEXT:         movb    (%r10), %r10b
+; CHECK-NEXT:         testb   %r10b, %r10b
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_store1@PLT
@@ -193,21 +185,19 @@
 ; CHECK-NEXT:         .weak   __asan_check_store2_rn[[RN2]]
 ; CHECK-NEXT:         .hidden __asan_check_store2_rn[[RN2]]
 ; CHECK-NEXT: __asan_check_store2_rn[[RN2]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8
-; CHECK-NEXT:         movb    (%r8), %r8b
-; CHECK-NEXT:         testb   %r8b, %r8b
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10
+; CHECK-NEXT:         movb    (%r10), %r10b
+; CHECK-NEXT:         testb   %r10b, %r10b
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         addl    $1, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         addl    $1, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_store2@PLT
@@ -216,21 +206,19 @@
 ; CHECK-NEXT:         .weak   __asan_check_store4_rn[[RN4]]
 ; CHECK-NEXT:         .hidden __asan_check_store4_rn[[RN4]]
 ; CHECK-NEXT: __asan_check_store4_rn[[RN4]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8
-; CHECK-NEXT:         movb    (%r8), %r8b
-; CHECK-NEXT:         testb   %r8b, %r8b
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10
+; CHECK-NEXT:         movb    (%r10), %r10b
+; CHECK-NEXT:         testb   %r10b, %r10b
 ; CHECK-NEXT:         jne     [[EXTRA:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
 ; CHECK-NEXT: [[EXTRA]]:
-; CHECK-NEXT:         pushq   %rcx
-; CHECK-NEXT:         movq    [[REG]], %rcx
-; CHECK-NEXT:         andl    $7, %ecx
-; CHECK-NEXT:         addl    $3, %ecx
-; CHECK-NEXT:         cmpl    %r8d, %ecx
-; CHECK-NEXT:         popq    %rcx
+; CHECK-NEXT:         movq    [[REG]], %r11
+; CHECK-NEXT:         andl    $7, %r11d
+; CHECK-NEXT:         addl    $3, %r11d
+; CHECK-NEXT:         cmpl    %r10d, %r11d
 ; CHECK-NEXT:         jl      [[RET]]
 ; CHECK-NEXT:         movq    [[REG:.*]], %rdi
 ; CHECK-NEXT:         jmp     __asan_report_store4@PLT
@@ -239,10 +227,10 @@
 ; CHECK-NEXT:         .weak   __asan_check_store8_rn[[RN8]]
 ; CHECK-NEXT:         .hidden __asan_check_store8_rn[[RN8]]
 ; CHECK-NEXT: __asan_check_store8_rn[[RN8]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8{{.*}}
-; CHECK-NEXT:         cmpb    $0, (%r8)
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10{{.*}}
+; CHECK-NEXT:         cmpb    $0, (%r10)
 ; CHECK-NEXT:         jne     [[FAIL:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
@@ -254,10 +242,10 @@
 ; CHECK-NEXT:         .weak   __asan_check_store16_rn[[RN16]]
 ; CHECK-NEXT:         .hidden __asan_check_store16_rn[[RN16]]
 ; CHECK-NEXT: __asan_check_store16_rn[[RN16]]:
-; CHECK-NEXT:         movq    [[REG:.*]], %r8
-; CHECK-NEXT:         shrq    $3, %r8
-; CHECK-NEXT:         orq     $17592186044416, %r8{{.*}}
-; CHECK-NEXT:         cmpw    $0, (%r8)
+; CHECK-NEXT:         movq    [[REG:.*]], %r10
+; CHECK-NEXT:         shrq    $3, %r10
+; CHECK-NEXT:         orq     $17592186044416, %r10{{.*}}
+; CHECK-NEXT:         cmpw    $0, (%r10)
 ; CHECK-NEXT:         jne     [[FAIL:.*]]
 ; CHECK-NEXT: [[RET:.*]]:
 ; CHECK-NEXT:         retq
diff --git a/llvm/test/CodeGen/X86/musttail-varargs.ll b/llvm/test/CodeGen/X86/musttail-varargs.ll
--- a/llvm/test/CodeGen/X86/musttail-varargs.ll
+++ b/llvm/test/CodeGen/X86/musttail-varargs.ll
@@ -82,6 +82,7 @@
 ; LINUX-NEXT:    movq %rbp, %rdx
 ; LINUX-NEXT:    movq %r13, %rcx
 ; LINUX-NEXT:    movq %r12, %r8
+; LINUX-NEXT:    movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload
 ; LINUX-NEXT:    movq %r15, %r9
 ; LINUX-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
 ; LINUX-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
@@ -91,7 +92,6 @@
 ; LINUX-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload
 ; LINUX-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm6 # 16-byte Reload
 ; LINUX-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Reload
-; LINUX-NEXT:    movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload
 ; LINUX-NEXT:    addq $360, %rsp # imm = 0x168
 ; LINUX-NEXT:    .cfi_def_cfa_offset 56
 ; LINUX-NEXT:    popq %rbx
@@ -175,6 +175,7 @@
 ; LINUX-X32-NEXT:    movq %rbp, %rdx
 ; LINUX-X32-NEXT:    movq %r13, %rcx
 ; LINUX-X32-NEXT:    movq %r12, %r8
+; LINUX-X32-NEXT:    movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
 ; LINUX-X32-NEXT:    movq %r15, %r9
 ; LINUX-X32-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; LINUX-X32-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 # 16-byte Reload
@@ -184,7 +185,6 @@
 ; LINUX-X32-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm5 # 16-byte Reload
 ; LINUX-X32-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm6 # 16-byte Reload
 ; LINUX-X32-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm7 # 16-byte Reload
-; LINUX-X32-NEXT:    movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
 ; LINUX-X32-NEXT:    addl $344, %esp # imm = 0x158
 ; LINUX-X32-NEXT:    .cfi_def_cfa_offset 56
 ; LINUX-X32-NEXT:    popq %rbx