Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -4868,6 +4868,36 @@ return false; } } + + // Check the address model by taking the first Imm operand and checking it is + // legal for that addressing mode. + ARMII::AddrMode AddrMode = + (ARMII::AddrMode)(MI.getDesc().TSFlags & ARMII::AddrModeMask); + switch (AddrMode) { + default: + break; + case ARMII::AddrModeT2_i7: + case ARMII::AddrModeT2_i7s2: + case ARMII::AddrModeT2_i7s4: + case ARMII::AddrModeT2_i8: + case ARMII::AddrModeT2_i8pos: + case ARMII::AddrModeT2_i8neg: + case ARMII::AddrModeT2_i8s4: + case ARMII::AddrModeT2_i12: { + uint32_t Imm = 0; + for (auto Op : MI.operands()) { + if (Op.isImm()) { + Imm = Op.getImm(); + break; + } + } + if (!isLegalAddressImm(MI.getOpcode(), Imm, this)) { + ErrInfo = "Incorrect AddrMode Imm for instruction"; + return false; + } + break; + } + } return true; } Index: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp =================================================================== --- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -1451,9 +1451,9 @@ // restore FPSCR from stack and clear bits 0-4, 7, 28-31 // The other bits are program global according to the AAPCS if (passesFPReg) { - BuildMI(MBB, MBBI, DL, TII->get(ARM::t2LDRi8), SpareReg) + BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg) .addReg(ARM::SP) - .addImm(0x40) + .addImm(0x10) .add(predOps(ARMCC::AL)); BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) .addReg(SpareReg) Index: llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir =================================================================== --- llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir +++ llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir @@ -51,23 +51,23 @@ ;CHECK-LABEL: name: CheckAddrModeT2_i8 ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_[[I8:[0-9]+]] - ;CHECK-NEXT: t2STRHi8 $r0, $sp, 248, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRHT $r0, $sp, 248, 14 /* CC::al */, $noreg $r0 = tMOVr $r1, 14, $noreg tBL 14, $noreg, @foo, implicit-def dead $lr, implicit $sp - t2STRHi8 $r0, $sp, 0, 14, $noreg - t2STRHi8 $r0, $sp, 4, 14, $noreg - t2STRHi8 $r0, $sp, 247, 14, $noreg - t2STRHi8 $r0, $sp, 248, 14, $noreg + t2STRHT $r0, $sp, 0, 14, $noreg + t2STRHT $r0, $sp, 4, 14, $noreg + t2STRHT $r0, $sp, 247, 14, $noreg + t2STRHT $r0, $sp, 248, 14, $noreg tBL 14, $noreg, @foo, implicit-def dead $lr, implicit $sp - t2STRHi8 $r0, $sp, 0, 14, $noreg - t2STRHi8 $r0, $sp, 4, 14, $noreg - t2STRHi8 $r0, $sp, 247, 14, $noreg - t2STRHi8 $r0, $sp, 248, 14, $noreg + t2STRHT $r0, $sp, 0, 14, $noreg + t2STRHT $r0, $sp, 4, 14, $noreg + t2STRHT $r0, $sp, 247, 14, $noreg + t2STRHT $r0, $sp, 248, 14, $noreg tBL 14, $noreg, @foo, implicit-def dead $lr, implicit $sp - t2STRHi8 $r0, $sp, 0, 14, $noreg - t2STRHi8 $r0, $sp, 4, 14, $noreg - t2STRHi8 $r0, $sp, 247, 14, $noreg - t2STRHi8 $r0, $sp, 248, 14, $noreg + t2STRHT $r0, $sp, 0, 14, $noreg + t2STRHT $r0, $sp, 4, 14, $noreg + t2STRHT $r0, $sp, 247, 14, $noreg + t2STRHT $r0, $sp, 248, 14, $noreg BX_RET 14, $noreg ... --- @@ -195,9 +195,9 @@ ;CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ;CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -8 ;CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @foo, implicit-def dead $lr, implicit $sp - ;CHECK-NEXT: t2STRHi8 $r0, $sp, 8, 14 /* CC::al */, $noreg - ;CHECK-NEXT: t2STRHi8 $r0, $sp, 12, 14 /* CC::al */, $noreg - ;CHECK-NEXT: t2STRHi8 $r0, $sp, 255, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRHT $r0, $sp, 8, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRHT $r0, $sp, 12, 14 /* CC::al */, $noreg + ;CHECK-NEXT: t2STRHT $r0, $sp, 255, 14 /* CC::al */, $noreg ;CHECK-NEXT: $lr, $sp = t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg ;CHECK: name: OUTLINED_FUNCTION_[[I8S4]]