diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -357,8 +357,10 @@ bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC]; unsigned MinNopLen = HasStdExtC ? 2 : 4; - if ((Count % MinNopLen) != 0) - return false; + // If the count is not 4-byte (or 2 byte if HasStdExtC) aligned, we must be writing data into the text + // section (otherwise we have unaligned instructions, and thus have far + // bigger problems), so just write zeros instead. + OS.write_zeros(Count % MinNopLen); // The canonical nop on RISC-V is addi x0, x0, 0. for (; Count >= 4; Count -= 4) diff --git a/llvm/test/MC/RISCV/align-odd.s b/llvm/test/MC/RISCV/align-odd.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/align-odd.s @@ -0,0 +1,82 @@ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,-relax < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=RV64-C-EXT-NORELAX %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-relax < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=RV64-NORELAX %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=RV32-C-EXT-NORELAX %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=RV32-NORELAX %s + +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+relax < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=RV64-C-EXT-RELAX %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+relax < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=RV64-RELAX %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=RV32-C-EXT-RELAX %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=RV32-RELAX %s + +# RV64-C-EXT-NORELAX: 0: 01 00 +# RV64-C-EXT-NORELAX-NEXT: 2: 00 00 +# RV64-C-EXT-NORELAX-NEXT: 4: 00 00 +# RV64-C-EXT-NORELAX-NEXT: 6: 01 00 +# RV64-C-EXT-NORELAX-NEXT: 8: 2a 95 + +# RV64-NORELAX: 0: 01 00 +# RV64-NORELAX-NEXT: 2: 00 00 +# RV64-NORELAX-NEXT: 4: 00 00 +# RV64-NORELAX-NEXT: 6: 00 00 +# RV64-NORELAX-NEXT: 8: 33 05 a5 00 + +# RV32-C-EXT-NORELAX: 0: 01 00 +# RV32-C-EXT-NORELAX-NEXT: 2: 00 00 +# RV32-C-EXT-NORELAX-NEXT: 4: 00 00 +# RV32-C-EXT-NORELAX-NEXT: 6: 01 00 +# RV32-C-EXT-NORELAX-NEXT: 8: 2a 95 + +# RV32-NORELAX: 0: 01 00 +# RV32-NORELAX-NEXT: 2: 00 00 +# RV32-NORELAX-NEXT: 4: 00 00 +# RV32-NORELAX-NEXT: 6: 00 00 +# RV32-NORELAX-NEXT: 8: 33 05 a5 00 + + +# RV64-C-EXT-RELAX: 0: 01 00 +# RV64-C-EXT-RELAX-NEXT: 2: 00 00 +# RV64-C-EXT-RELAX-NEXT: 4: 00 13 +# RV64-C-EXT-RELAX-NEXT: 6: 00 00 +# RV64-C-EXT-RELAX-NEXT: 8: 00 01 +# RV64-C-EXT-RELAX-NEXT: a: 00 2a +# RV64-C-EXT-RELAX-NEXT: c: 95 + + +# RV64-RELAX: 0: 01 00 +# RV64-RELAX-NEXT: 2: 00 00 +# RV64-RELAX-NEXT: 4: 00 13 +# RV64-RELAX-NEXT: 6: 00 00 +# RV64-RELAX-NEXT: 8: 00 33 +# RV64-RELAX-NEXT: a: 05 a5 +# RV64-RELAX-NEXT: c: 00 + +# RV32-C-EXT-RELAX: 0: 01 00 +# RV32-C-EXT-RELAX-NEXT: 2: 00 00 +# RV32-C-EXT-RELAX-NEXT: 4: 00 13 +# RV32-C-EXT-RELAX-NEXT: 6: 00 00 +# RV32-C-EXT-RELAX-NEXT: 8: 00 01 +# RV32-C-EXT-RELAX-NEXT: a: 00 2a +# RV32-C-EXT-RELAX-NEXT: c: 95 + + +# RV32-RELAX: 0: 01 00 +# RV32-RELAX-NEXT: 2: 00 00 +# RV32-RELAX-NEXT: 4: 00 13 +# RV32-RELAX-NEXT: 6: 00 00 +# RV32-RELAX-NEXT: 8: 00 33 +# RV32-RELAX-NEXT: a: 05 a5 +# RV32-RELAX-NEXT: c: 00 + + +.byte 1 +.word 0 +.p2align 3 +add a0, a0, a0