diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -1584,51 +1584,66 @@ { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, // Mask sign extend has an instruction. - { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, // Mask zero extend is a sext + shift. - { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, + + { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, + { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, + { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, + { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, + { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, + { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, + { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm - { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm - { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb - { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm - { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb - { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm - { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, // widen to zmm - { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb - { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm - { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm - { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm - { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, - { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, - { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, }; static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { @@ -1815,37 +1830,62 @@ static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { // Mask sign extend has an instruction. - { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, - { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 }, // Mask zero extend is a sext + shift. - { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, - { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 }, + + { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, + { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, + { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, + { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, + { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 }, + { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 }, + { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 }, { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, - { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb - { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw - { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb - { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw - { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb - { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw - { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb - { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw - { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb }; static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { diff --git a/llvm/test/Analysis/CostModel/X86/extend.ll b/llvm/test/Analysis/CostModel/X86/extend.ll --- a/llvm/test/Analysis/CostModel/X86/extend.ll +++ b/llvm/test/Analysis/CostModel/X86/extend.ll @@ -1068,17 +1068,17 @@ ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = zext <4 x i1> undef to <4 x i16> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = zext <8 x i1> undef to <8 x i16> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i16 = zext <16 x i1> undef to <16 x i16> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V32i16 = zext <32 x i1> undef to <32 x i16> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64i16 = zext <64 x i1> undef to <64 x i16> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V128i16 = zext <128 x i1> undef to <128 x i16> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32i16 = zext <32 x i1> undef to <32 x i16> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64i16 = zext <64 x i1> undef to <64 x i16> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128i16 = zext <128 x i1> undef to <128 x i16> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = zext i1 undef to i8 ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = zext <2 x i1> undef to <2 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i8 = zext <4 x i1> undef to <4 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i8 = zext <8 x i1> undef to <8 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i8 = zext <16 x i1> undef to <16 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i8 = zext <32 x i1> undef to <32 x i8> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64i8 = zext <64 x i1> undef to <64 x i8> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128i8 = zext <128 x i1> undef to <128 x i8> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64i8 = zext <64 x i1> undef to <64 x i8> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V128i8 = zext <128 x i1> undef to <128 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; BTVER2-LABEL: 'zext_vXi1' @@ -2226,17 +2226,17 @@ ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i16 = sext <4 x i1> undef to <4 x i16> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i16 = sext <8 x i1> undef to <8 x i16> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16i16 = sext <16 x i1> undef to <16 x i16> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32i16 = sext <32 x i1> undef to <32 x i16> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V64i16 = sext <64 x i1> undef to <64 x i16> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128i16 = sext <128 x i1> undef to <128 x i16> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i16 = sext <32 x i1> undef to <32 x i16> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64i16 = sext <64 x i1> undef to <64 x i16> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V128i16 = sext <128 x i1> undef to <128 x i16> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = sext i1 undef to i8 ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i8 = sext <2 x i1> undef to <2 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i8 = sext <4 x i1> undef to <4 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i8 = sext <8 x i1> undef to <8 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16i8 = sext <16 x i1> undef to <16 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32i8 = sext <32 x i1> undef to <32 x i8> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64i8 = sext <64 x i1> undef to <64 x i8> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V128i8 = sext <128 x i1> undef to <128 x i8> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64i8 = sext <64 x i1> undef to <64 x i8> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128i8 = sext <128 x i1> undef to <128 x i8> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; BTVER2-LABEL: 'sext_vXi1' diff --git a/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll b/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll --- a/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll +++ b/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll @@ -326,13 +326,13 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = zext <4 x i1> undef to <4 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = zext <8 x i1> undef to <8 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i16 = zext <16 x i1> undef to <16 x i16> -; SKX256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V32i16 = zext <32 x i1> undef to <32 x i16> +; SKX256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32i16 = zext <32 x i1> undef to <32 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = zext <2 x i1> undef to <2 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i8 = zext <4 x i1> undef to <4 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i8 = zext <8 x i1> undef to <8 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i8 = zext <16 x i1> undef to <16 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i8 = zext <32 x i1> undef to <32 x i8> -; SKX256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64i8 = zext <64 x i1> undef to <64 x i8> +; SKX256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64i8 = zext <64 x i1> undef to <64 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SKX512-LABEL: 'zext256_vXi1' @@ -472,14 +472,14 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i16 = sext <4 x i1> undef to <4 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i16 = sext <8 x i1> undef to <8 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16i16 = sext <16 x i1> undef to <16 x i16> -; SKX256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32i16 = sext <32 x i1> undef to <32 x i16> +; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i16 = sext <32 x i1> undef to <32 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = sext i1 undef to i8 ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i8 = sext <2 x i1> undef to <2 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i8 = sext <4 x i1> undef to <4 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i8 = sext <8 x i1> undef to <8 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16i8 = sext <16 x i1> undef to <16 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32i8 = sext <32 x i1> undef to <32 x i8> -; SKX256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64i8 = sext <64 x i1> undef to <64 x i8> +; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64i8 = sext <64 x i1> undef to <64 x i8> ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SKX512-LABEL: 'sext256_vXi1' @@ -635,14 +635,14 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = trunc <4 x i16> undef to <4 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = trunc <8 x i16> undef to <8 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i16 = trunc <16 x i16> undef to <16 x i1> -; SKX256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1> -; SKX256-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1> +; SKX256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1> +; SKX256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = trunc <2 x i8> undef to <2 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i8 = trunc <4 x i8> undef to <4 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i8 = trunc <8 x i8> undef to <8 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i8 = trunc <16 x i8> undef to <16 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i8 = trunc <32 x i8> undef to <32 x i1> -; SKX256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64i8 = trunc <64 x i8> undef to <64 x i1> +; SKX256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64i8 = trunc <64 x i8> undef to <64 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SKX512-LABEL: 'trunc_vXi1' diff --git a/llvm/test/Analysis/CostModel/X86/shuffle-replication-i1.ll b/llvm/test/Analysis/CostModel/X86/shuffle-replication-i1.ll --- a/llvm/test/Analysis/CostModel/X86/shuffle-replication-i1.ll +++ b/llvm/test/Analysis/CostModel/X86/shuffle-replication-i1.ll @@ -118,10 +118,10 @@ ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <4 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <8 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <16 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <32 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <64 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <128 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <256 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <32 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <64 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <128 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <256 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512VBMIVEC512-LABEL: 'replication_i1_stride2' @@ -141,9 +141,9 @@ ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <8 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <16 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <32 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <64 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <128 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <256 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <64 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <128 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <256 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <2 x i32> zeroinitializer @@ -261,11 +261,11 @@ ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <3 x i32> zeroinitializer ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <6 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <12 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <24 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 103 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <48 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 207 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <96 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 415 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <192 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 830 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <384 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <24 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <48 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <96 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <192 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <384 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512VBMIVEC512-LABEL: 'replication_i1_stride3' @@ -281,13 +281,13 @@ ; ; AVX512VBMIVEC256-LABEL: 'replication_i1_stride3' ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <3 x i32> zeroinitializer -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <6 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <6 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <12 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <24 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <48 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 196 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <96 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 393 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <192 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 786 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <384 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <48 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <96 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <192 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <384 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <3 x i32> zeroinitializer @@ -405,11 +405,11 @@ ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <4 x i32> zeroinitializer ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <8 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <16 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <32 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <64 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <128 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 83 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <256 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 166 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <512 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <32 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <64 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <128 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 68 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <256 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <512 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512VBMIVEC512-LABEL: 'replication_i1_stride4' @@ -428,10 +428,10 @@ ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <8 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <16 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <32 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <64 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <128 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <256 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 62 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <512 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <64 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <128 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <256 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <512 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <4 x i32> zeroinitializer @@ -548,12 +548,12 @@ ; AVX512BWVEC256-LABEL: 'replication_i1_stride5' ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <5 x i32> zeroinitializer ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <10 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <20 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <40 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 171 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <80 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 343 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <160 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 687 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <320 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1374 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <640 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <20 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <40 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <80 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <160 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 108 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <320 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 216 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <640 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512VBMIVEC512-LABEL: 'replication_i1_stride5' @@ -571,11 +571,11 @@ ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <5 x i32> zeroinitializer ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <10 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <20 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 83 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <40 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 164 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <80 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 326 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <160 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 653 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <320 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 1306 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <640 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <40 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <80 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <160 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <320 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <640 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <5 x i32> zeroinitializer @@ -692,12 +692,12 @@ ; AVX512BWVEC256-LABEL: 'replication_i1_stride6' ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <6 x i32> zeroinitializer ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <12 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <24 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 103 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <48 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 205 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <96 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 411 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <192 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 823 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <384 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1646 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <768 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <24 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <48 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <96 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 58 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <192 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 116 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <384 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 232 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <768 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512VBMIVEC512-LABEL: 'replication_i1_stride6' @@ -715,11 +715,11 @@ ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <6 x i32> zeroinitializer ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <12 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <24 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <48 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 196 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <96 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 391 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <192 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 783 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <384 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 1566 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <768 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <48 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <96 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <192 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <384 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <768 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <6 x i32> zeroinitializer @@ -836,12 +836,12 @@ ; AVX512BWVEC256-LABEL: 'replication_i1_stride7' ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <7 x i32> zeroinitializer ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <14 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <28 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 121 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <56 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 239 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <112 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 479 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <224 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 959 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <448 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1918 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <896 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <28 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <56 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <112 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 62 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <224 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 124 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <448 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 248 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <896 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512VBMIVEC512-LABEL: 'replication_i1_stride7' @@ -859,11 +859,11 @@ ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <7 x i32> zeroinitializer ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <14 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <28 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 115 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <56 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 229 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <112 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 456 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <224 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 913 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <448 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 1826 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <896 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <56 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <112 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <224 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <448 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <896 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <7 x i32> zeroinitializer @@ -980,12 +980,12 @@ ; AVX512BWVEC256-LABEL: 'replication_i1_stride8' ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <8 x i32> zeroinitializer ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <16 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <32 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <64 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <128 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <256 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 159 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <512 x i32> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 318 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <1024 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <32 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <64 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <128 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <256 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 132 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <512 x i32> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 264 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <1024 x i32> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512VBMIVEC512-LABEL: 'replication_i1_stride8' @@ -1003,11 +1003,11 @@ ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <8 x i32> zeroinitializer ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf2 = shufflevector <2 x i1> undef, <2 x i1> poison, <16 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %vf4 = shufflevector <4 x i1> undef, <4 x i1> poison, <32 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <64 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <128 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <256 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 59 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <512 x i32> -; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 118 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <1024 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %vf8 = shufflevector <8 x i1> undef, <8 x i1> poison, <64 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %vf16 = shufflevector <16 x i1> undef, <16 x i1> poison, <128 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %vf32 = shufflevector <32 x i1> undef, <32 x i1> poison, <256 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %vf64 = shufflevector <64 x i1> undef, <64 x i1> poison, <512 x i32> +; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 100 for instruction: %vf128 = shufflevector <128 x i1> undef, <128 x i1> poison, <1024 x i32> ; AVX512VBMIVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %vf1 = shufflevector <1 x i1> undef, <1 x i1> poison, <8 x i32> zeroinitializer diff --git a/llvm/test/Analysis/CostModel/X86/trunc.ll b/llvm/test/Analysis/CostModel/X86/trunc.ll --- a/llvm/test/Analysis/CostModel/X86/trunc.ll +++ b/llvm/test/Analysis/CostModel/X86/trunc.ll @@ -3669,7 +3669,7 @@ ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %V1024i32 = trunc <1024 x i32> undef to <1024 x i1> ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i16 = trunc i16 undef to i1 ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i16 = trunc <2 x i16> undef to <2 x i1> -; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V3i16 = trunc <3 x i16> undef to <3 x i1> +; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V3i16 = trunc <3 x i16> undef to <3 x i1> ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = trunc <4 x i16> undef to <4 x i1> ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V5i16 = trunc <5 x i16> undef to <5 x i1> ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V6i16 = trunc <6 x i16> undef to <6 x i1> @@ -3704,7 +3704,7 @@ ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V1024i16 = trunc <1024 x i16> undef to <1024 x i1> ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i8 = trunc i8 undef to i1 ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = trunc <2 x i8> undef to <2 x i1> -; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V3i8 = trunc <3 x i8> undef to <3 x i1> +; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V3i8 = trunc <3 x i8> undef to <3 x i1> ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i8 = trunc <4 x i8> undef to <4 x i1> ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V5i8 = trunc <5 x i8> undef to <5 x i1> ; AVX512BWVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V6i8 = trunc <6 x i8> undef to <6 x i1> @@ -3812,7 +3812,7 @@ ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 368 for instruction: %V1024i32 = trunc <1024 x i32> undef to <1024 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i16 = trunc i16 undef to i1 ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i16 = trunc <2 x i16> undef to <2 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V3i16 = trunc <3 x i16> undef to <3 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V3i16 = trunc <3 x i16> undef to <3 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = trunc <4 x i16> undef to <4 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V5i16 = trunc <5 x i16> undef to <5 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V6i16 = trunc <6 x i16> undef to <6 x i1> @@ -3822,36 +3822,36 @@ ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V12i16 = trunc <12 x i16> undef to <12 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V14i16 = trunc <14 x i16> undef to <14 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i16 = trunc <16 x i16> undef to <16 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V20i16 = trunc <20 x i16> undef to <20 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V24i16 = trunc <24 x i16> undef to <24 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V28i16 = trunc <28 x i16> undef to <28 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V40i16 = trunc <40 x i16> undef to <40 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V48i16 = trunc <48 x i16> undef to <48 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V56i16 = trunc <56 x i16> undef to <56 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V80i16 = trunc <80 x i16> undef to <80 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 224 for instruction: %V112i16 = trunc <112 x i16> undef to <112 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V128i16 = trunc <128 x i16> undef to <128 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V160i16 = trunc <160 x i16> undef to <160 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %V192i16 = trunc <192 x i16> undef to <192 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 448 for instruction: %V224i16 = trunc <224 x i16> undef to <224 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V256i16 = trunc <256 x i16> undef to <256 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %V320i16 = trunc <320 x i16> undef to <320 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %V384i16 = trunc <384 x i16> undef to <384 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 896 for instruction: %V448i16 = trunc <448 x i16> undef to <448 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V512i16 = trunc <512 x i16> undef to <512 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V640i16 = trunc <640 x i16> undef to <640 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1536 for instruction: %V768i16 = trunc <768 x i16> undef to <768 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: %V896i16 = trunc <896 x i16> undef to <896 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %V1024i16 = trunc <1024 x i16> undef to <1024 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V20i16 = trunc <20 x i16> undef to <20 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V24i16 = trunc <24 x i16> undef to <24 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V28i16 = trunc <28 x i16> undef to <28 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V40i16 = trunc <40 x i16> undef to <40 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V48i16 = trunc <48 x i16> undef to <48 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V56i16 = trunc <56 x i16> undef to <56 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V80i16 = trunc <80 x i16> undef to <80 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V112i16 = trunc <112 x i16> undef to <112 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128i16 = trunc <128 x i16> undef to <128 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V160i16 = trunc <160 x i16> undef to <160 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V192i16 = trunc <192 x i16> undef to <192 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V224i16 = trunc <224 x i16> undef to <224 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V256i16 = trunc <256 x i16> undef to <256 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V320i16 = trunc <320 x i16> undef to <320 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V384i16 = trunc <384 x i16> undef to <384 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V448i16 = trunc <448 x i16> undef to <448 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V512i16 = trunc <512 x i16> undef to <512 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V640i16 = trunc <640 x i16> undef to <640 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V768i16 = trunc <768 x i16> undef to <768 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V896i16 = trunc <896 x i16> undef to <896 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V1024i16 = trunc <1024 x i16> undef to <1024 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i8 = trunc i8 undef to i1 ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = trunc <2 x i8> undef to <2 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V3i8 = trunc <3 x i8> undef to <3 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V3i8 = trunc <3 x i8> undef to <3 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i8 = trunc <4 x i8> undef to <4 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V5i8 = trunc <5 x i8> undef to <5 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V6i8 = trunc <6 x i8> undef to <6 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V7i8 = trunc <7 x i8> undef to <7 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V5i8 = trunc <5 x i8> undef to <5 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V6i8 = trunc <6 x i8> undef to <6 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V7i8 = trunc <7 x i8> undef to <7 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i8 = trunc <8 x i8> undef to <8 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V10i8 = trunc <10 x i8> undef to <10 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V12i8 = trunc <12 x i8> undef to <12 x i1> @@ -3861,25 +3861,25 @@ ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V24i8 = trunc <24 x i8> undef to <24 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V28i8 = trunc <28 x i8> undef to <28 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i8 = trunc <32 x i8> undef to <32 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V40i8 = trunc <40 x i8> undef to <40 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V48i8 = trunc <48 x i8> undef to <48 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V56i8 = trunc <56 x i8> undef to <56 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64i8 = trunc <64 x i8> undef to <64 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V80i8 = trunc <80 x i8> undef to <80 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 224 for instruction: %V112i8 = trunc <112 x i8> undef to <112 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128i8 = trunc <128 x i8> undef to <128 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V160i8 = trunc <160 x i8> undef to <160 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %V192i8 = trunc <192 x i8> undef to <192 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 448 for instruction: %V224i8 = trunc <224 x i8> undef to <224 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V256i8 = trunc <256 x i8> undef to <256 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %V320i8 = trunc <320 x i8> undef to <320 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %V384i8 = trunc <384 x i8> undef to <384 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 896 for instruction: %V448i8 = trunc <448 x i8> undef to <448 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V512i8 = trunc <512 x i8> undef to <512 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V640i8 = trunc <640 x i8> undef to <640 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1536 for instruction: %V768i8 = trunc <768 x i8> undef to <768 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: %V896i8 = trunc <896 x i8> undef to <896 x i1> -; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V1024i8 = trunc <1024 x i8> undef to <1024 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V40i8 = trunc <40 x i8> undef to <40 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V48i8 = trunc <48 x i8> undef to <48 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V56i8 = trunc <56 x i8> undef to <56 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64i8 = trunc <64 x i8> undef to <64 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V80i8 = trunc <80 x i8> undef to <80 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V112i8 = trunc <112 x i8> undef to <112 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V128i8 = trunc <128 x i8> undef to <128 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V160i8 = trunc <160 x i8> undef to <160 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V192i8 = trunc <192 x i8> undef to <192 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V224i8 = trunc <224 x i8> undef to <224 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V256i8 = trunc <256 x i8> undef to <256 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V320i8 = trunc <320 x i8> undef to <320 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V384i8 = trunc <384 x i8> undef to <384 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V448i8 = trunc <448 x i8> undef to <448 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V512i8 = trunc <512 x i8> undef to <512 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V640i8 = trunc <640 x i8> undef to <640 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V768i8 = trunc <768 x i8> undef to <768 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V896i8 = trunc <896 x i8> undef to <896 x i1> +; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V1024i8 = trunc <1024 x i8> undef to <1024 x i1> ; AVX512BWVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; BTVER2-LABEL: 'trunc_vXi1'