diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -1632,6 +1632,35 @@ }; static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { + // Mask sign extend has an instruction. + { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, + + // Mask zero extend is a sext + shift. + { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, + + { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, + { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, + { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 }, + { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, @@ -1820,6 +1849,35 @@ }; static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { + // Mask sign extend has an instruction. + { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, + + // Mask zero extend is a sext + shift. + { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, + + { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 }, + { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, + { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, + { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 }, + { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, + { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, diff --git a/llvm/test/Analysis/CostModel/X86/extend.ll b/llvm/test/Analysis/CostModel/X86/extend.ll --- a/llvm/test/Analysis/CostModel/X86/extend.ll +++ b/llvm/test/Analysis/CostModel/X86/extend.ll @@ -946,10 +946,10 @@ ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i64 = zext <2 x i1> undef to <2 x i64> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i64 = zext <4 x i1> undef to <4 x i64> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i64 = zext <8 x i1> undef to <8 x i64> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16i64 = zext <16 x i1> undef to <16 x i64> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32i64 = zext <32 x i1> undef to <32 x i64> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V64i64 = zext <64 x i1> undef to <64 x i64> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V128i64 = zext <128 x i1> undef to <128 x i64> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i64 = zext <16 x i1> undef to <16 x i64> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32i64 = zext <32 x i1> undef to <32 x i64> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64i64 = zext <64 x i1> undef to <64 x i64> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V128i64 = zext <128 x i1> undef to <128 x i64> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = zext i1 undef to i32 ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i32 = zext <2 x i1> undef to <2 x i32> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i32 = zext <4 x i1> undef to <4 x i32> @@ -980,19 +980,19 @@ ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = zext i1 undef to i64 ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i64 = zext <2 x i1> undef to <2 x i64> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i64 = zext <4 x i1> undef to <4 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8i64 = zext <8 x i1> undef to <8 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V16i64 = zext <16 x i1> undef to <16 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V32i64 = zext <32 x i1> undef to <32 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V64i64 = zext <64 x i1> undef to <64 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V128i64 = zext <128 x i1> undef to <128 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8i64 = zext <8 x i1> undef to <8 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16i64 = zext <16 x i1> undef to <16 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32i64 = zext <32 x i1> undef to <32 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V64i64 = zext <64 x i1> undef to <64 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V128i64 = zext <128 x i1> undef to <128 x i64> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = zext i1 undef to i32 ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i32 = zext <2 x i1> undef to <2 x i32> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i32 = zext <4 x i1> undef to <4 x i32> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i32 = zext <8 x i1> undef to <8 x i32> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16i32 = zext <16 x i1> undef to <16 x i32> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32i32 = zext <32 x i1> undef to <32 x i32> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V64i32 = zext <64 x i1> undef to <64 x i32> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V128i32 = zext <128 x i1> undef to <128 x i32> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = zext <16 x i1> undef to <16 x i32> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32i32 = zext <32 x i1> undef to <32 x i32> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64i32 = zext <64 x i1> undef to <64 x i32> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V128i32 = zext <128 x i1> undef to <128 x i32> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = zext i1 undef to i16 ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2i16 = zext <2 x i1> undef to <2 x i16> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4i16 = zext <4 x i1> undef to <4 x i16> @@ -2104,10 +2104,10 @@ ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i64 = sext <2 x i1> undef to <2 x i64> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i64 = sext <4 x i1> undef to <4 x i64> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i64 = sext <8 x i1> undef to <8 x i64> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16i64 = sext <16 x i1> undef to <16 x i64> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32i64 = sext <32 x i1> undef to <32 x i64> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64i64 = sext <64 x i1> undef to <64 x i64> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V128i64 = sext <128 x i1> undef to <128 x i64> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i64 = sext <16 x i1> undef to <16 x i64> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32i64 = sext <32 x i1> undef to <32 x i64> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64i64 = sext <64 x i1> undef to <64 x i64> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128i64 = sext <128 x i1> undef to <128 x i64> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = sext i1 undef to i32 ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i32 = sext <2 x i1> undef to <2 x i32> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i32 = sext <4 x i1> undef to <4 x i32> @@ -2138,19 +2138,19 @@ ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = sext i1 undef to i64 ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i64 = sext <2 x i1> undef to <2 x i64> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i64 = sext <4 x i1> undef to <4 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8i64 = sext <8 x i1> undef to <8 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i64 = sext <16 x i1> undef to <16 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V32i64 = sext <32 x i1> undef to <32 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V64i64 = sext <64 x i1> undef to <64 x i64> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V128i64 = sext <128 x i1> undef to <128 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i64 = sext <8 x i1> undef to <8 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i64 = sext <16 x i1> undef to <16 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32i64 = sext <32 x i1> undef to <32 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64i64 = sext <64 x i1> undef to <64 x i64> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V128i64 = sext <128 x i1> undef to <128 x i64> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = sext i1 undef to i32 ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i32 = sext <2 x i1> undef to <2 x i32> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i32 = sext <4 x i1> undef to <4 x i32> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i32 = sext <8 x i1> undef to <8 x i32> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16i32 = sext <16 x i1> undef to <16 x i32> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32i32 = sext <32 x i1> undef to <32 x i32> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64i32 = sext <64 x i1> undef to <64 x i32> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V128i32 = sext <128 x i1> undef to <128 x i32> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i32 = sext <16 x i1> undef to <16 x i32> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32i32 = sext <32 x i1> undef to <32 x i32> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64i32 = sext <64 x i1> undef to <64 x i32> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128i32 = sext <128 x i1> undef to <128 x i32> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = sext i1 undef to i16 ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2i16 = sext <2 x i1> undef to <2 x i16> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4i16 = sext <4 x i1> undef to <4 x i16> diff --git a/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll b/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll --- a/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll +++ b/llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll @@ -317,11 +317,11 @@ ; SKX256-LABEL: 'zext256_vXi1' ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i64 = zext <2 x i1> undef to <2 x i64> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i64 = zext <4 x i1> undef to <4 x i64> -; SKX256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8i64 = zext <8 x i1> undef to <8 x i64> +; SKX256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8i64 = zext <8 x i1> undef to <8 x i64> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i32 = zext <2 x i1> undef to <2 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i32 = zext <4 x i1> undef to <4 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i32 = zext <8 x i1> undef to <8 x i32> -; SKX256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16i32 = zext <16 x i1> undef to <16 x i32> +; SKX256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = zext <16 x i1> undef to <16 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i16 = zext <2 x i1> undef to <2 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = zext <4 x i1> undef to <4 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = zext <8 x i1> undef to <8 x i16> @@ -461,12 +461,12 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = sext i1 undef to i64 ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i64 = sext <2 x i1> undef to <2 x i64> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i64 = sext <4 x i1> undef to <4 x i64> -; SKX256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8i64 = sext <8 x i1> undef to <8 x i64> +; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i64 = sext <8 x i1> undef to <8 x i64> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = sext i1 undef to i32 ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i32 = sext <2 x i1> undef to <2 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i32 = sext <4 x i1> undef to <4 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i32 = sext <8 x i1> undef to <8 x i32> -; SKX256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16i32 = sext <16 x i1> undef to <16 x i32> +; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i32 = sext <16 x i1> undef to <16 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = sext i1 undef to i16 ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2i16 = sext <2 x i1> undef to <2 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i16 = sext <4 x i1> undef to <4 x i16> @@ -628,9 +628,9 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i32 = trunc <2 x i32> undef to <2 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i32 = trunc <4 x i32> undef to <4 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i32 = trunc <8 x i32> undef to <8 x i1> -; SKX256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16i32 = trunc <16 x i32> undef to <16 x i1> -; SKX256-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32i32 = trunc <32 x i32> undef to <32 x i1> -; SKX256-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V64i32 = trunc <64 x i32> undef to <64 x i1> +; SKX256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = trunc <16 x i32> undef to <16 x i1> +; SKX256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32i32 = trunc <32 x i32> undef to <32 x i1> +; SKX256-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V64i32 = trunc <64 x i32> undef to <64 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i16 = trunc <2 x i16> undef to <2 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = trunc <4 x i16> undef to <4 x i1> ; SKX256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = trunc <8 x i16> undef to <8 x i1> diff --git a/llvm/test/Analysis/CostModel/X86/trunc.ll b/llvm/test/Analysis/CostModel/X86/trunc.ll --- a/llvm/test/Analysis/CostModel/X86/trunc.ll +++ b/llvm/test/Analysis/CostModel/X86/trunc.ll @@ -3319,33 +3319,33 @@ ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V6i64 = trunc <6 x i64> undef to <6 x i1> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V7i64 = trunc <7 x i64> undef to <7 x i1> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V10i64 = trunc <10 x i64> undef to <10 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V12i64 = trunc <12 x i64> undef to <12 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V14i64 = trunc <14 x i64> undef to <14 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V10i64 = trunc <10 x i64> undef to <10 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V12i64 = trunc <12 x i64> undef to <12 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V14i64 = trunc <14 x i64> undef to <14 x i1> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V20i64 = trunc <20 x i64> undef to <20 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V24i64 = trunc <24 x i64> undef to <24 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V28i64 = trunc <28 x i64> undef to <28 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V32i64 = trunc <32 x i64> undef to <32 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V40i64 = trunc <40 x i64> undef to <40 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V48i64 = trunc <48 x i64> undef to <48 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V56i64 = trunc <56 x i64> undef to <56 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V64i64 = trunc <64 x i64> undef to <64 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V80i64 = trunc <80 x i64> undef to <80 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 224 for instruction: %V112i64 = trunc <112 x i64> undef to <112 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V128i64 = trunc <128 x i64> undef to <128 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V160i64 = trunc <160 x i64> undef to <160 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %V192i64 = trunc <192 x i64> undef to <192 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 448 for instruction: %V224i64 = trunc <224 x i64> undef to <224 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %V256i64 = trunc <256 x i64> undef to <256 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %V320i64 = trunc <320 x i64> undef to <320 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %V384i64 = trunc <384 x i64> undef to <384 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 896 for instruction: %V448i64 = trunc <448 x i64> undef to <448 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 352 for instruction: %V512i64 = trunc <512 x i64> undef to <512 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V640i64 = trunc <640 x i64> undef to <640 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1536 for instruction: %V768i64 = trunc <768 x i64> undef to <768 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: %V896i64 = trunc <896 x i64> undef to <896 x i1> -; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 704 for instruction: %V1024i64 = trunc <1024 x i64> undef to <1024 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V20i64 = trunc <20 x i64> undef to <20 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V24i64 = trunc <24 x i64> undef to <24 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V28i64 = trunc <28 x i64> undef to <28 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32i64 = trunc <32 x i64> undef to <32 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V40i64 = trunc <40 x i64> undef to <40 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V48i64 = trunc <48 x i64> undef to <48 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V56i64 = trunc <56 x i64> undef to <56 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64i64 = trunc <64 x i64> undef to <64 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V80i64 = trunc <80 x i64> undef to <80 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V112i64 = trunc <112 x i64> undef to <112 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V128i64 = trunc <128 x i64> undef to <128 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V160i64 = trunc <160 x i64> undef to <160 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V192i64 = trunc <192 x i64> undef to <192 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V224i64 = trunc <224 x i64> undef to <224 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V256i64 = trunc <256 x i64> undef to <256 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V320i64 = trunc <320 x i64> undef to <320 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V384i64 = trunc <384 x i64> undef to <384 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V448i64 = trunc <448 x i64> undef to <448 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V512i64 = trunc <512 x i64> undef to <512 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V640i64 = trunc <640 x i64> undef to <640 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V768i64 = trunc <768 x i64> undef to <768 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V896i64 = trunc <896 x i64> undef to <896 x i1> +; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V1024i64 = trunc <1024 x i64> undef to <1024 x i1> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i32 = trunc i32 undef to i1 ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i32 = trunc <2 x i32> undef to <2 x i1> ; AVX512DQVEC512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V3i32 = trunc <3 x i32> undef to <3 x i1> @@ -3458,37 +3458,37 @@ ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V3i64 = trunc <3 x i64> undef to <3 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V5i64 = trunc <5 x i64> undef to <5 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V6i64 = trunc <6 x i64> undef to <6 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V7i64 = trunc <7 x i64> undef to <7 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V5i64 = trunc <5 x i64> undef to <5 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V6i64 = trunc <6 x i64> undef to <6 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V7i64 = trunc <7 x i64> undef to <7 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V10i64 = trunc <10 x i64> undef to <10 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V12i64 = trunc <12 x i64> undef to <12 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V14i64 = trunc <14 x i64> undef to <14 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V10i64 = trunc <10 x i64> undef to <10 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V12i64 = trunc <12 x i64> undef to <12 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V14i64 = trunc <14 x i64> undef to <14 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V20i64 = trunc <20 x i64> undef to <20 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V24i64 = trunc <24 x i64> undef to <24 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V28i64 = trunc <28 x i64> undef to <28 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V32i64 = trunc <32 x i64> undef to <32 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V40i64 = trunc <40 x i64> undef to <40 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V48i64 = trunc <48 x i64> undef to <48 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V56i64 = trunc <56 x i64> undef to <56 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V64i64 = trunc <64 x i64> undef to <64 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V80i64 = trunc <80 x i64> undef to <80 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 224 for instruction: %V112i64 = trunc <112 x i64> undef to <112 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V128i64 = trunc <128 x i64> undef to <128 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V160i64 = trunc <160 x i64> undef to <160 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %V192i64 = trunc <192 x i64> undef to <192 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 448 for instruction: %V224i64 = trunc <224 x i64> undef to <224 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %V256i64 = trunc <256 x i64> undef to <256 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %V320i64 = trunc <320 x i64> undef to <320 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %V384i64 = trunc <384 x i64> undef to <384 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 896 for instruction: %V448i64 = trunc <448 x i64> undef to <448 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 352 for instruction: %V512i64 = trunc <512 x i64> undef to <512 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V640i64 = trunc <640 x i64> undef to <640 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1536 for instruction: %V768i64 = trunc <768 x i64> undef to <768 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: %V896i64 = trunc <896 x i64> undef to <896 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 704 for instruction: %V1024i64 = trunc <1024 x i64> undef to <1024 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V20i64 = trunc <20 x i64> undef to <20 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V24i64 = trunc <24 x i64> undef to <24 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V28i64 = trunc <28 x i64> undef to <28 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32i64 = trunc <32 x i64> undef to <32 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V40i64 = trunc <40 x i64> undef to <40 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V48i64 = trunc <48 x i64> undef to <48 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V56i64 = trunc <56 x i64> undef to <56 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V64i64 = trunc <64 x i64> undef to <64 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V80i64 = trunc <80 x i64> undef to <80 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V112i64 = trunc <112 x i64> undef to <112 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V128i64 = trunc <128 x i64> undef to <128 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V160i64 = trunc <160 x i64> undef to <160 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V192i64 = trunc <192 x i64> undef to <192 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V224i64 = trunc <224 x i64> undef to <224 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V256i64 = trunc <256 x i64> undef to <256 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V320i64 = trunc <320 x i64> undef to <320 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V384i64 = trunc <384 x i64> undef to <384 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V448i64 = trunc <448 x i64> undef to <448 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V512i64 = trunc <512 x i64> undef to <512 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %V640i64 = trunc <640 x i64> undef to <640 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %V768i64 = trunc <768 x i64> undef to <768 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %V896i64 = trunc <896 x i64> undef to <896 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %V1024i64 = trunc <1024 x i64> undef to <1024 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i32 = trunc i32 undef to i1 ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i32 = trunc <2 x i32> undef to <2 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V3i32 = trunc <3 x i32> undef to <3 x i1> @@ -3497,33 +3497,33 @@ ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V6i32 = trunc <6 x i32> undef to <6 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V7i32 = trunc <7 x i32> undef to <7 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i32 = trunc <8 x i32> undef to <8 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V10i32 = trunc <10 x i32> undef to <10 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V12i32 = trunc <12 x i32> undef to <12 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V14i32 = trunc <14 x i32> undef to <14 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16i32 = trunc <16 x i32> undef to <16 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V20i32 = trunc <20 x i32> undef to <20 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V24i32 = trunc <24 x i32> undef to <24 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V28i32 = trunc <28 x i32> undef to <28 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32i32 = trunc <32 x i32> undef to <32 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V40i32 = trunc <40 x i32> undef to <40 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V48i32 = trunc <48 x i32> undef to <48 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V56i32 = trunc <56 x i32> undef to <56 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V64i32 = trunc <64 x i32> undef to <64 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V80i32 = trunc <80 x i32> undef to <80 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 224 for instruction: %V112i32 = trunc <112 x i32> undef to <112 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V128i32 = trunc <128 x i32> undef to <128 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V160i32 = trunc <160 x i32> undef to <160 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %V192i32 = trunc <192 x i32> undef to <192 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 448 for instruction: %V224i32 = trunc <224 x i32> undef to <224 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V256i32 = trunc <256 x i32> undef to <256 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %V320i32 = trunc <320 x i32> undef to <320 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %V384i32 = trunc <384 x i32> undef to <384 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 896 for instruction: %V448i32 = trunc <448 x i32> undef to <448 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V512i32 = trunc <512 x i32> undef to <512 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V640i32 = trunc <640 x i32> undef to <640 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1536 for instruction: %V768i32 = trunc <768 x i32> undef to <768 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: %V896i32 = trunc <896 x i32> undef to <896 x i1> -; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V1024i32 = trunc <1024 x i32> undef to <1024 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V10i32 = trunc <10 x i32> undef to <10 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V12i32 = trunc <12 x i32> undef to <12 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V14i32 = trunc <14 x i32> undef to <14 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = trunc <16 x i32> undef to <16 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V20i32 = trunc <20 x i32> undef to <20 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V24i32 = trunc <24 x i32> undef to <24 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V28i32 = trunc <28 x i32> undef to <28 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32i32 = trunc <32 x i32> undef to <32 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V40i32 = trunc <40 x i32> undef to <40 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V48i32 = trunc <48 x i32> undef to <48 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V56i32 = trunc <56 x i32> undef to <56 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64i32 = trunc <64 x i32> undef to <64 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V80i32 = trunc <80 x i32> undef to <80 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V112i32 = trunc <112 x i32> undef to <112 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V128i32 = trunc <128 x i32> undef to <128 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V160i32 = trunc <160 x i32> undef to <160 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V192i32 = trunc <192 x i32> undef to <192 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V224i32 = trunc <224 x i32> undef to <224 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %V256i32 = trunc <256 x i32> undef to <256 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V320i32 = trunc <320 x i32> undef to <320 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V384i32 = trunc <384 x i32> undef to <384 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V448i32 = trunc <448 x i32> undef to <448 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V512i32 = trunc <512 x i32> undef to <512 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V640i32 = trunc <640 x i32> undef to <640 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V768i32 = trunc <768 x i32> undef to <768 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V896i32 = trunc <896 x i32> undef to <896 x i1> +; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %V1024i32 = trunc <1024 x i32> undef to <1024 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i16 = trunc i16 undef to i1 ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2i16 = trunc <2 x i16> undef to <2 x i1> ; AVX512DQVEC256-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V3i16 = trunc <3 x i16> undef to <3 x i1>