Index: llvm/lib/Target/Hexagon/BitTracker.cpp =================================================================== --- llvm/lib/Target/Hexagon/BitTracker.cpp +++ llvm/lib/Target/Hexagon/BitTracker.cpp @@ -214,9 +214,9 @@ BT::RegisterCell &BT::RegisterCell::insert(const BT::RegisterCell &RC, const BitMask &M) { uint16_t B = M.first(), E = M.last(), W = width(); - // Sanity: M must be a valid mask for *this. + // M must be a valid mask for *this. assert(B < W && E < W); - // Sanity: the masked part of *this must have the same number of bits + // The masked part of *this must have the same number of bits // as the source. assert(B > E || E-B+1 == RC.width()); // B <= E => E-B+1 = |RC|. assert(B <= E || E+(W-B)+1 == RC.width()); // E < B => E+(W-B)+1 = |RC|. Index: llvm/lib/Target/Hexagon/HexagonBitTracker.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonBitTracker.cpp +++ llvm/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -189,7 +189,7 @@ unsigned NumDefs = 0; - // Sanity verification: there should not be any defs with subregisters. + // Verification check: there should not be any defs with subregisters. for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg() || !MO.isDef()) continue; Index: llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -1254,7 +1254,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, AssignmentMap &IMap) { - // Sanity check: make sure that all extenders in the range [Begin..End) + // Validation check: make sure that all extenders in the range [Begin..End) // share the same root ER. for (unsigned I = Begin; I != End; ++I) assert(ER == ExtRoot(Extenders[I].getOp())); Index: llvm/lib/Target/Hexagon/HexagonGenInsert.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -1501,7 +1501,7 @@ bool Timing = OptTiming, TimingDetail = Timing && OptTimingDetail; bool Changed = false; - // Sanity check: one, but not both. + // Verify: one, but not both. assert(!OptSelectAll0 || !OptSelectHas0); IFMap.clear(); Index: llvm/lib/Target/Hexagon/HexagonGenMux.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -328,7 +328,7 @@ unsigned MxOpc = getMuxOpcode(*MX.SrcT, *MX.SrcF); if (!MxOpc) continue; - // Basic sanity check: since we are deleting instructions, validate the + // Basic validation check: since we are deleting instructions, validate the // iterators. There is a possibility that one of Def1 or Def2 is translated // to "mux" and being considered for other "mux" instructions. if (!MX.At->getParent() || !MX.Def1->getParent() || !MX.Def2->getParent()) Index: llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -411,7 +411,7 @@ NumOps = 2; } - // Some sanity: check that def is in operand #0. + // Check that def is in operand #0. MachineOperand &Op0 = MI->getOperand(0); assert(Op0.isDef()); RegisterSubReg OutR(Op0); Index: llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1123,7 +1123,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L, bool &RecL0used, bool &RecL1used) { - // This is just for sanity. + // This is just for validation.. assert(L->getHeader() && "Loop without a header?"); bool Changed = false; Index: llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -1006,7 +1006,7 @@ static bool isPermutation(ArrayRef Mask) { // Check by adding all numbers only works if there is no overflow. - assert(Mask.size() < 0x00007FFF && "Sanity failure"); + assert(Mask.size() < 0x00007FFF && "Overflow failure"); int Sum = 0; for (int Idx : Mask) { if (Idx == -1) @@ -1217,7 +1217,7 @@ } else if (Seg0 == ~1u) { Seg0 = SegList[0] != Seg1 ? SegList[0] : SegList[1]; } else { - assert(Seg1 == ~1u); // Sanity + assert(Seg1 == ~1u); Seg1 = SegList[0] != Seg0 ? SegList[0] : SegList[1]; } } @@ -1265,7 +1265,7 @@ } else { // BC or DA: this could be done via valign by SegLen. // Do nothing here, because valign (if possible) will be generated - // later on (make sure the Seg0 values are as expected, for sanity). + // later on (make sure the Seg0 values are as expected). assert(Seg0 == 1 || Seg0 == 3); } } @@ -1414,7 +1414,7 @@ return OpRef::undef(getSingleVT(MVT::i8)); unsigned HalfLen = HwLen / 2; - assert(isPowerOf2_32(HalfLen)); // Sanity. + assert(isPowerOf2_32(HalfLen)); // Handle special case where the output is the same half of the input // repeated twice, i.e. if Va = AB, then handle the output of AA or BB. Index: llvm/lib/Target/Hexagon/HexagonISelLowering.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2549,7 +2549,8 @@ // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon // without any coprocessors). if (ElemWidth == 1) { - assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure"); + assert(VecWidth == VecTy.getVectorNumElements() && + "Vector elements should equal vector width size"); assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2); // Check if this is an extract of the lowest bit. if (IdxN) { @@ -2863,8 +2864,7 @@ Scale /= 2; } - // Another sanity check. At this point there should only be two words - // left, and Scale should be 2. + // At this point there should only be two words left, and Scale should be 2. assert(Scale == 2 && Words[IdxW].size() == 2); SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, Index: llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp +++ llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp @@ -749,7 +749,6 @@ WithMaxAlign.ValTy, Adjust); int Diff = Start - (OffAtMax + Adjust); AlignVal = HVC.getConstInt(Diff); - // Sanity. assert(Diff >= 0); assert(static_cast(Diff) < MinNeeded.value()); } else { Index: llvm/test/CodeGen/Hexagon/abi-padding-2.ll =================================================================== --- llvm/test/CodeGen/Hexagon/abi-padding-2.ll +++ llvm/test/CodeGen/Hexagon/abi-padding-2.ll @@ -14,7 +14,7 @@ ; Test that while passing a 7-byte struct on the stack, the ; size of the struct is 16 bytes including padding since its ; largest member is of type long long. This was being handled -; correctly but is a sanity check against any potential future +; correctly but is a check against any potential future ; regressions. ; Index: llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir =================================================================== --- llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir +++ llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir @@ -1,6 +1,6 @@ # RUN: llc < %s -x mir -march=hexagon -run-pass=modulo-schedule-test -pipeliner-experimental-cg=true | FileCheck %s -# Simple check for this sanity test; ensure all instructions are in stage 0 in +# Simple check for this validation test; ensure all instructions are in stage 0 in # the prolog and stage 3 in the epilog. # CHECK-NOT: Stage-3