diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1323,10 +1323,15 @@ def : SVE_1_Op_Pat(NAME # _S)>; def : SVE_1_Op_Pat(NAME # _D)>; + def : SVE_1_Op_Pat(NAME # _D)>; + def : SVE_1_Op_Pat(NAME # _S)>; def : SVE_1_Op_Pat(NAME # _H)>; + def : SVE_1_Op_Pat(NAME # _D)>; def : SVE_1_Op_Pat(NAME # _S)>; def : SVE_1_Op_Pat(NAME # _D)>; + def : SVE_1_Op_Pat(NAME # _D)>; + def : SVE_1_Op_Pat(NAME # _S)>; def : SVE_1_Op_Pat(NAME # _H)>; } diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll --- a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll +++ b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll @@ -118,6 +118,26 @@ ret %res } +define @reverse_nxv2f16( %a) #0 { +; CHECK-LABEL: reverse_nxv2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: rev z0.d, z0.d +; CHECK-NEXT: ret + + %res = call @llvm.experimental.vector.reverse.nxv2f16( %a) + ret %res +} + +define @reverse_nxv4f16( %a) #0 { +; CHECK-LABEL: reverse_nxv4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: rev z0.s, z0.s +; CHECK-NEXT: ret + + %res = call @llvm.experimental.vector.reverse.nxv4f16( %a) + ret %res +} + define @reverse_nxv8f16( %a) #0 { ; CHECK-LABEL: reverse_nxv8f16: ; CHECK: // %bb.0: @@ -128,6 +148,45 @@ ret %res } +define @reverse_nxv2bf16( %a) #1 { +; CHECK-LABEL: reverse_nxv2bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: rev z0.d, z0.d +; CHECK-NEXT: ret + + %res = call @llvm.experimental.vector.reverse.nxv2bf16( %a) + ret %res +} + +define @reverse_nxv4bf16( %a) #1 { +; CHECK-LABEL: reverse_nxv4bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: rev z0.s, z0.s +; CHECK-NEXT: ret + + %res = call @llvm.experimental.vector.reverse.nxv4bf16( %a) + ret %res +} + +define @reverse_nxv8bf16( %a) #1 { +; CHECK-LABEL: reverse_nxv8bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: rev z0.h, z0.h +; CHECK-NEXT: ret + + %res = call @llvm.experimental.vector.reverse.nxv8bf16( %a) + ret %res +} + +define @reverse_nxv2f32( %a) #0 { +; CHECK-LABEL: reverse_nxv2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: rev z0.d, z0.d +; CHECK-NEXT: ret + + %res = call @llvm.experimental.vector.reverse.nxv2f32( %a) ret %res +} + define @reverse_nxv4f32( %a) #0 { ; CHECK-LABEL: reverse_nxv4f32: ; CHECK: // %bb.0: @@ -230,10 +289,17 @@ declare @llvm.experimental.vector.reverse.nxv4i32() declare @llvm.experimental.vector.reverse.nxv8i32() declare @llvm.experimental.vector.reverse.nxv2i64() +declare @llvm.experimental.vector.reverse.nxv2f16() +declare @llvm.experimental.vector.reverse.nxv4f16() declare @llvm.experimental.vector.reverse.nxv8f16() +declare @llvm.experimental.vector.reverse.nxv2bf16() +declare @llvm.experimental.vector.reverse.nxv4bf16() +declare @llvm.experimental.vector.reverse.nxv8bf16() +declare @llvm.experimental.vector.reverse.nxv2f32() declare @llvm.experimental.vector.reverse.nxv4f32() declare @llvm.experimental.vector.reverse.nxv16f32() declare @llvm.experimental.vector.reverse.nxv2f64() attributes #0 = { nounwind "target-features"="+sve" } +attributes #1 = { nounwind "target-features"="+sve,+bf16" }