diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -695,6 +695,72 @@
   return None;
 }
 
+static Optional<Instruction *> instCombineSVEMaskedLD1(InstCombiner &IC,
+                                                       IntrinsicInst &II,
+                                                       const DataLayout &DL) {
+  Type *VecOp = II.getType();
+  Value *PointerOp = II.getOperand(1);
+
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);
+  auto VScalePointer = Builder.CreateBitCast(PointerOp, VecOp->getPointerTo());
+  auto MaskedLoad = Builder.CreateMaskedLoad(VecOp, VScalePointer,
+                                             PointerOp->getPointerAlignment(DL),
+                                             II.getOperand(0));
+  return IC.replaceInstUsesWith(II, MaskedLoad);
+}
+
+static Optional<Instruction *>
+instCombineSVELD1(InstCombiner &IC, IntrinsicInst &II, const DataLayout &DL) {
+  Value *Predicate;
+  if (!match(II.getOperand(0),
+             m_Intrinsic<Intrinsic::aarch64_sve_ptrue>(m_Value(Predicate))))
+    return None;
+  if (!match(Predicate, m_ConstantInt<AArch64SVEPredPattern::all>()))
+    return instCombineSVEMaskedLD1(IC, II, DL);
+
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);
+  auto VScalePointer =
+      Builder.CreateBitCast(II.getOperand(1), II.getType()->getPointerTo());
+  auto Load = Builder.CreateLoad(II.getType(), VScalePointer);
+  return IC.replaceInstUsesWith(II, Load);
+}
+
+static Optional<Instruction *> instCombineSVEST1Masked(InstCombiner &IC,
+                                                       IntrinsicInst &II,
+                                                       const DataLayout &DL) {
+  auto VecOp = II.getOperand(0);
+  auto PointerOp = II.getOperand(2);
+
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);
+  auto VScalePointer =
+      Builder.CreateBitCast(PointerOp, VecOp->getType()->getPointerTo());
+  (void)Builder.CreateMaskedStore(VecOp, VScalePointer,
+                                  PointerOp->getPointerAlignment(DL),
+                                  II.getOperand(1));
+  return IC.eraseInstFromFunction(II);
+}
+
+static Optional<Instruction *>
+instCombineSVEST1(InstCombiner &IC, IntrinsicInst &II, const DataLayout &DL) {
+  Value *Predicate;
+  if (!match(II.getOperand(1),
+             m_Intrinsic<Intrinsic::aarch64_sve_ptrue>(m_Value(Predicate))))
+    return None;
+  if (!match(Predicate, m_ConstantInt<AArch64SVEPredPattern::all>()))
+    return instCombineSVEST1Masked(IC, II, DL);
+
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);
+  auto VecOp = II.getOperand(0);
+  auto VScalePointer =
+      Builder.CreateBitCast(II.getOperand(2), VecOp->getType()->getPointerTo());
+  (void)Builder.CreateStore(VecOp, VScalePointer);
+  return IC.eraseInstFromFunction(II);
+}
+
 static Instruction::BinaryOps intrinsicIDToBinOpCode(unsigned Intrinsic) {
   switch (Intrinsic) {
   case Intrinsic::aarch64_sve_fmul:
@@ -987,6 +1053,10 @@
     return instCombineLD1GatherIndex(IC, II);
   case Intrinsic::aarch64_sve_st1_scatter_index:
     return instCombineST1ScatterIndex(IC, II);
+  case Intrinsic::aarch64_sve_ld1:
+    return instCombineSVELD1(IC, II, DL);
+  case Intrinsic::aarch64_sve_st1:
+    return instCombineSVEST1(IC, II, DL);
   }
 
   return None;
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define <vscale x 4 x i32> @combine_ld1(i32* %ptr) #0 {
+; CHECK-LABEL: @combine_ld1(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[PTR:%.*]] to <vscale x 4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[TMP1]], align 16
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
+;
+  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+  %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %1, i32* %ptr)
+  ret <vscale x 4 x i32> %2
+}
+
+define <vscale x 4 x i32> @combine_ld1_masked(i32* %ptr) #0 {
+; CHECK-LABEL: @combine_ld1_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 16)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32* [[PTR:%.*]] to <vscale x 4 x i32>*
+; CHECK-NEXT:    [[TMP3:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* [[TMP2]], i32 1, <vscale x 4 x i1> [[TMP1]], <vscale x 4 x i32> undef)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP3]]
+;
+  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 16)
+  %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %1, i32* %ptr)
+  ret <vscale x 4 x i32> %2
+}
+
+define void @combine_st1(<vscale x 4 x i32> %vec, i32* %ptr) #0 {
+; CHECK-LABEL: @combine_st1(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[PTR:%.*]] to <vscale x 4 x i32>*
+; CHECK-NEXT:    store <vscale x 4 x i32> [[VEC:%.*]], <vscale x 4 x i32>* [[TMP1]], align 16
+; CHECK-NEXT:    ret void
+;
+  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+  call void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32> %vec, <vscale x 4 x i1> %1, i32* %ptr)
+  ret void
+}
+
+define void @combine_st1_masked(<vscale x 4 x i32> %vec, i32* %ptr) #0 {
+; CHECK-LABEL: @combine_st1_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 16)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32* [[PTR:%.*]] to <vscale x 4 x i32>*
+; CHECK-NEXT:    call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> [[VEC:%.*]], <vscale x 4 x i32>* [[TMP2]], i32 1, <vscale x 4 x i1> [[TMP1]])
+; CHECK-NEXT:    ret void
+;
+  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 16)
+  call void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32> %vec, <vscale x 4 x i1> %1, i32* %ptr)
+  ret void
+}
+
+declare void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
+declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
+declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1>, i32*)
+
+attributes #0 = { "target-features"="+sve" }