diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp --- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp +++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp @@ -379,7 +379,7 @@ int64_t StackAdj = MBBI->getOperand(0).getImm(); X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true); // Replace pseudo with machine iret - unsigned RetOp = STI->is64Bit() ? X86::IRET64 : X86::IRET32; + unsigned RetOp = STI->is64Bit() ? X86::IRETQ : X86::IRETL; // Use UIRET if UINTR is present (except for building kernel) if (STI->is64Bit() && STI->hasUINTR() && MBB.getParent()->getTarget().getCodeModel() != CodeModel::Kernel) diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td --- a/llvm/lib/Target/X86/X86InstrControl.td +++ b/llvm/lib/Target/X86/X86InstrControl.td @@ -48,10 +48,10 @@ // The machine return from interrupt instruction, but sometimes we need to // perform a post-epilogue stack adjustment. Codegen emits the pseudo form // which expands to include an SP adjustment if necessary. - def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, + def IRETW : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize16; - def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; - def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; + def IRETL : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; + def IRETQ : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; let isCodeGenOnly = 1 in def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -541,7 +541,7 @@ PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, XCH_F)>; def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", - "IRET(16|32|64)?")>; + "IRET(L|Q|W)?")>; def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { let Latency = 5; diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -698,7 +698,7 @@ let NumMicroOps = 2; } def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)", - "IRET(16|32|64)")>; + "IRET(L|Q|W)")>; //-- Logic instructions --// diff --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td --- a/llvm/lib/Target/X86/X86ScheduleZnver2.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td @@ -698,7 +698,7 @@ let NumMicroOps = 2; } def : InstRW<[Zn2WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)", - "IRET(16|32|64)")>; + "IRET(L|Q|W)")>; //-- Logic instructions --//