diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -1,6 +1,6 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s -// RUN: %clang -target riscv32-unknown-elf -march=rv32i2p0 -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32i2p1 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s @@ -70,7 +70,7 @@ // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s -// RUN: %clang -target riscv64-unknown-elf -march=rv64i2p0 -### %s \ +// RUN: %clang -target riscv64-unknown-elf -march=rv64i2p1 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64im -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s @@ -307,10 +307,10 @@ // RV32-IMINOR-MISS: error: invalid arch name 'rv32i2p', // RV32-IMINOR-MISS: minor version number missing after 'p' for extension 'i' -// RUN: %clang -target riscv32-unknown-elf -march=rv32i2p1 -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32i2p0 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IMINOR1 %s -// RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported -// RV32-IMINOR1: version number 2.1 for extension 'i' +// RV32-IMINOR1: error: invalid arch name 'rv32i2p0', unsupported +// RV32-IMINOR1: version number 2.0 for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixt2p -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -129,7 +129,8 @@ // march overwrite mcpu's default march // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s -// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c" +// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" +// MCPU-MARCH: "-target-feature" "+m" "-target-feature" "+c" // MCPU-MARCH: "-target-abi" "ilp32" // Check interaction between mcpu and mtune, mtune won't affect arch related diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s --- a/lld/test/ELF/riscv-attributes.s +++ b/lld/test/ELF/riscv-attributes.s @@ -23,11 +23,11 @@ # CHECK-NEXT: Attribute { # CHECK-NEXT: Tag: 5 # CHECK-NEXT: TagName: arch -# CHECK-NEXT: Value: rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0 +# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p0_f2p0_d2p0_c2p0 # CHECK-NEXT: } # CHECK-NEXT: } # CHECK-NEXT: } # CHECK-NEXT: } .attribute 4, 16 -.attribute 5, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" +.attribute 5, "rv64i2p1_m2p0_a2p0_f2p0_d2p0_c2p0" diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -39,13 +39,17 @@ static constexpr StringLiteral AllStdExts = "mafdqlcbjtpvn"; static const RISCVSupportedExtension SupportedExtensions[] = { - {"i", RISCVExtensionVersion{2, 0}}, + {"i", RISCVExtensionVersion{2, 1}}, {"e", RISCVExtensionVersion{1, 9}}, {"m", RISCVExtensionVersion{2, 0}}, {"a", RISCVExtensionVersion{2, 0}}, {"f", RISCVExtensionVersion{2, 0}}, {"d", RISCVExtensionVersion{2, 0}}, {"c", RISCVExtensionVersion{2, 0}}, + + {"zicsr", RISCVExtensionVersion{2, 0}}, + {"zifencei", RISCVExtensionVersion{2, 0}}, + {"zihintpause", RISCVExtensionVersion{2, 0}}, }; static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { @@ -258,8 +262,12 @@ for (auto &Ext : Exts) { StringRef ExtName = Ext.first; - if (ExtName == "i") + if (ExtName == "i") { + Features.push_back("+zicsr"); + Features.push_back("+zifencei"); + Features.push_back("+zihintpause"); continue; + } if (ExtName == "zvlsseg") { Features.push_back("+experimental-v"); diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -176,6 +176,27 @@ AssemblerPredicate<(all_of FeatureStdExtZvamo), "'Zvamo' (Vector AMO Operations)">; +def FeatureStdExtZicsr + : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true", + "'Zicsr' (Control and Status Register)">; +def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, + AssemblerPredicate<(all_of FeatureStdExtZicsr), + "'Zicsr' (Control and Status Register)">; + +def FeatureStdExtZifencei + : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true", + "'Zifencei' (Instruction-Fetch Fence)">; +def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, + AssemblerPredicate<(all_of FeatureStdExtZifencei), + "'Zifencei' (Instruction-Fetch Fence)">; + +def FeatureStdExtZihintpause + : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true", + "'Zihintpause' (Pause Hint)">; +def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, + AssemblerPredicate<(all_of FeatureStdExtZihintpause), + "'Zihintpause' (Pause Hint)">; + def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -558,6 +558,7 @@ let imm12 = {0b1000,0b0011,0b0011}; } +let Predicates = [HasStdExtZifencei] in def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> { let rs1 = 0; let rd = 0; @@ -588,6 +589,7 @@ } } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 +let Predicates = [HasStdExtZicsr] in { def CSRRW : CSR_ir<0b001, "csrrw">; def CSRRS : CSR_ir<0b010, "csrrs">; def CSRRC : CSR_ir<0b011, "csrrc">; @@ -595,6 +597,7 @@ def CSRRWI : CSR_ii<0b101, "csrrwi">; def CSRRSI : CSR_ii<0b110, "csrrsi">; def CSRRCI : CSR_ii<0b111, "csrrci">; +} // Predicates = [HasStdExtZicsr] /// RV64I instructions @@ -779,6 +782,7 @@ def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, TIMEH.Encoding, X0)>; } // Predicates = [IsRV32] +let Predicates = [HasStdExtZicsr] in { def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>; def : InstAlias<"csrw $csr, $rs", (CSRRW X0, csr_sysreg:$csr, GPR:$rs)>; def : InstAlias<"csrs $csr, $rs", (CSRRS X0, csr_sysreg:$csr, GPR:$rs)>; @@ -797,6 +801,7 @@ def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>; def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>; } +} // Predicates = [HasStdExtZicsr] def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>; def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -52,6 +52,9 @@ bool HasStdExtV = false; bool HasStdExtZvlsseg = false; bool HasStdExtZvamo = false; + bool HasStdExtZicsr = false; + bool HasStdExtZifencei = false; + bool HasStdExtZihintpause = false; bool HasStdExtZfhmin = false; bool HasStdExtZfh = false; bool HasRV64 = false; @@ -119,6 +122,9 @@ bool hasStdExtV() const { return HasStdExtV; } bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } bool hasStdExtZvamo() const { return HasStdExtZvamo; } + bool hasStdExtZicsr() const { return HasStdExtZicsr; } + bool hasStdExtZifencei() const { return HasStdExtZifencei; } + bool hasStdExtZihintpause() const { return HasStdExtZihintpause; } bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } bool hasStdExtZfh() const { return HasStdExtZfh; } bool is64Bit() const { return HasRV64; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -39,45 +39,45 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s -; RV32M: .attribute 5, "rv32i2p0_m2p0" -; RV32A: .attribute 5, "rv32i2p0_a2p0" -; RV32F: .attribute 5, "rv32i2p0_f2p0" -; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0" -; RV32C: .attribute 5, "rv32i2p0_c2p0" -; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" -; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin0p1" -; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1" -; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0" -; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0" -; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0" -; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93" -; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93" -; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93" -; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93" -; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" -; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" -; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" -; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvlsseg0p10" +; RV32M: .attribute 5, "rv32i2p1_m2p0" +; RV32A: .attribute 5, "rv32i2p1_a2p0" +; RV32F: .attribute 5, "rv32i2p1_f2p0" +; RV32D: .attribute 5, "rv32i2p1_f2p0_d2p0" +; RV32C: .attribute 5, "rv32i2p1_c2p0" +; RV32V: .attribute 5, "rv32i2p1_v0p10_zvamo0p10_zvlsseg0p10" +; RV32ZFHMIN: .attribute 5, "rv32i2p1_f2p0_zfhmin0p1" +; RV32ZFH: .attribute 5, "rv32i2p1_f2p0_zfh0p1_zfhmin0p1" +; RV32ZBA: .attribute 5, "rv32i2p1_zba1p0" +; RV32ZBB: .attribute 5, "rv32i2p1_zbb1p0" +; RV32ZBC: .attribute 5, "rv32i2p1_zbc1p0" +; RV32ZBE: .attribute 5, "rv32i2p1_zbe0p93" +; RV32ZBF: .attribute 5, "rv32i2p1_zbf0p93" +; RV32ZBM: .attribute 5, "rv32i2p1_zbm0p93" +; RV32ZBP: .attribute 5, "rv32i2p1_zbp0p93" +; RV32ZBR: .attribute 5, "rv32i2p1_zbr0p93" +; RV32ZBS: .attribute 5, "rv32i2p1_zbs1p0" +; RV32ZBT: .attribute 5, "rv32i2p1_zbt0p93" +; RV32COMBINED: .attribute 5, "rv32i2p1_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvlsseg0p10" -; RV64M: .attribute 5, "rv64i2p0_m2p0" -; RV64A: .attribute 5, "rv64i2p0_a2p0" -; RV64F: .attribute 5, "rv64i2p0_f2p0" -; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0" -; RV64C: .attribute 5, "rv64i2p0_c2p0" -; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin0p1" -; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1_zfhmin0p1" -; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0" -; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0" -; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0" -; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93" -; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93" -; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93" -; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93" -; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" -; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" -; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" -; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10" -; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvlsseg0p10" +; RV64M: .attribute 5, "rv64i2p1_m2p0" +; RV64A: .attribute 5, "rv64i2p1_a2p0" +; RV64F: .attribute 5, "rv64i2p1_f2p0" +; RV64D: .attribute 5, "rv64i2p1_f2p0_d2p0" +; RV64C: .attribute 5, "rv64i2p1_c2p0" +; RV64ZFHMIN: .attribute 5, "rv64i2p1_f2p0_zfhmin0p1" +; RV64ZFH: .attribute 5, "rv64i2p1_f2p0_zfh0p1_zfhmin0p1" +; RV64ZBA: .attribute 5, "rv64i2p1_zba1p0" +; RV64ZBB: .attribute 5, "rv64i2p1_zbb1p0" +; RV64ZBC: .attribute 5, "rv64i2p1_zbc1p0" +; RV64ZBE: .attribute 5, "rv64i2p1_zbe0p93" +; RV64ZBF: .attribute 5, "rv64i2p1_zbf0p93" +; RV64ZBM: .attribute 5, "rv64i2p1_zbm0p93" +; RV64ZBP: .attribute 5, "rv64i2p1_zbp0p93" +; RV64ZBR: .attribute 5, "rv64i2p1_zbr0p93" +; RV64ZBS: .attribute 5, "rv64i2p1_zbs1p0" +; RV64ZBT: .attribute 5, "rv64i2p1_zbt0p93" +; RV64V: .attribute 5, "rv64i2p1_v0p10_zvamo0p10_zvlsseg0p10" +; RV64COMBINED: .attribute 5, "rv64i2p1_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvlsseg0p10" define i32 @addi(i32 %a) { diff --git a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll --- a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v -O2 < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IV define @access_fixed_object(i64 *%val) { diff --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll --- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll +++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v -verify-machineinstrs < %s \ ; RUN: | FileCheck %s define void @lmul1() nounwind { diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @bitreverse_nxv1i8( %va) { ; CHECK-LABEL: bitreverse_nxv1i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @bswap_nxv1i16( %va) { ; CHECK-LABEL: bswap_nxv1i16: diff --git a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll --- a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 define fastcc @ret_nxv4i8(* %p) { diff --git a/llvm/test/CodeGen/RISCV/rvv/calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/calling-conv.ll --- a/llvm/test/CodeGen/RISCV/rvv/calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/calling-conv.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV64 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v < %s | FileCheck %s --check-prefix=RV32 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v < %s | FileCheck %s --check-prefix=RV64 ; Check that we correctly scale the split part indirect offsets by VSCALE. define @callee_scalable_vector_split_indirect( %x, %y) { diff --git a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv32 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv64 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s define @extract_nxv8i32_nxv4i32_0( %vec) { ; CHECK-LABEL: extract_nxv8i32_nxv4i32_0: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 - -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 + +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 define @insert_nxv8i32_v2i32_0( %vec, <2 x i32>* %svp) { ; CHECK-LABEL: insert_nxv8i32_v2i32_0: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half>* %m_ptr) nounwind { ; CHECK-LABEL: masked_store_v1f16: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @masked_store_v1i8(<1 x i8>* %val_ptr, <1 x i8>* %a, <1 x i8>* %m_ptr) nounwind { ; CHECK-LABEL: masked_store_v1i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define <2 x i16> @vwmul_v2i16(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: vwmul_v2i16: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK define <2 x i16> @vwmulu_v2i16(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: vwmulu_v2i16: @@ -891,4 +891,3 @@ %g = mul <2 x i64> %e, %f ret <2 x i64> %g } - diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv32 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv64 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s define @insert_nxv8i32_nxv4i32_0( %vec, %subvec) { ; CHECK-LABEL: insert_nxv8i32_nxv4i32_0: diff --git a/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll b/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll --- a/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll +++ b/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -O1 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=1024 < %s | FileCheck %s --check-prefix=RV64-1024 -; RUN: llc -mtriple=riscv64 -O1 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=2048 < %s | FileCheck %s --check-prefix=RV64-2048 +; RUN: llc -mtriple=riscv64 -O1 -mattr=+zicsr,+m,+experimental-v -riscv-v-vector-bits-min=1024 < %s | FileCheck %s --check-prefix=RV64-1024 +; RUN: llc -mtriple=riscv64 -O1 -mattr=+zicsr,+m,+experimental-v -riscv-v-vector-bits-min=2048 < %s | FileCheck %s --check-prefix=RV64-2048 define void @interleave256(<256 x i16>* %agg.result, <128 x i16>* %0, <128 x i16>* %1) { ; RV64-1024-LABEL: interleave256: diff --git a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir --- a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir +++ b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -# RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v -start-before=prologepilog -o - \ +# RUN: llc -mtriple riscv64 -mattr=+zicsr,+m,+experimental-v -start-before=prologepilog -o - \ # RUN: -verify-machineinstrs %s | FileCheck %s --- | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" diff --git a/llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s ; Check that we are able to legalize scalable-vector loads that require widening. diff --git a/llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s | FileCheck %s ; Check that we are able to legalize scalable-vector stores that require widening. diff --git a/llvm/test/CodeGen/RISCV/rvv/localvar.ll b/llvm/test/CodeGen/RISCV/rvv/localvar.ll --- a/llvm/test/CodeGen/RISCV/rvv/localvar.ll +++ b/llvm/test/CodeGen/RISCV/rvv/localvar.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IV define void @local_var_mf8() { diff --git a/llvm/test/CodeGen/RISCV/rvv/memory-args.ll b/llvm/test/CodeGen/RISCV/rvv/memory-args.ll --- a/llvm/test/CodeGen/RISCV/rvv/memory-args.ll +++ b/llvm/test/CodeGen/RISCV/rvv/memory-args.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v -O2 < %s \ ; RUN: | FileCheck %s -check-prefix=RV64IV declare @llvm.riscv.vmacc.nxv64i8.nxv64i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 declare @llvm.masked.gather.nxv1i8.nxv1p0i8(, i32, , ) diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 declare void @llvm.masked.scatter.nxv1i8.nxv1p0i8(, , i32, ) diff --git a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll --- a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-UNKNOWN -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-256 -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-512 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-UNKNOWN -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-256 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-512 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-UNKNOWN +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-256 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-512 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v,+f,+d,+experimental-zfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-UNKNOWN +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-256 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v,+f,+d,+experimental-zfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-512 ; ; VECTOR_REVERSE - masks diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll --- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -O0 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v,+d -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -O2 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v,+d -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll --- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -O0 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -O2 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s define @spill_lmul_mf2( %va) nounwind { diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll --- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -mattr=+m -O0 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v,+m -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -mattr=+m -O2 < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v,+m -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s define @spill_zvlsseg_nxv1i32(i32* %base, i32 %vl) nounwind { diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll --- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -mattr=+d -O0 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v,+d -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -mattr=+d -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v,+d -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll --- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -O0 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s define @spill_lmul_1( %va) nounwind { diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll --- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+m -O0 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v,+m -O0 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+m -O2 < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v,+m -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s define @spill_zvlsseg_nxv1i32(i32* %base, i64 %vl) nounwind { diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll --- a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+m -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v,+m -verify-machineinstrs < %s | FileCheck %s define void @rvv_vla(i64 %n, i64 %i) nounwind { ; CHECK-LABEL: rvv_vla: diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll --- a/llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v -verify-machineinstrs \ ; RUN: < %s | FileCheck %s define dso_local void @lots_args(i32 signext %x0, i32 signext %x1, %v0, i32 signext %x2, i32 signext %x3, i32 signext %x4, i32 signext %x5, i32 signext %x6, i32 %x7, i32 %x8, i32 %x9) #0 { diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll --- a/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+m,+experimental-v < %s \ +; RUN: llc -mtriple riscv32 -mattr=+zicsr,+m,+experimental-v < %s \ ; RUN: | FileCheck %s define i32 @vscale_zero() nounwind { diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll --- a/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v < %s \ +; RUN: llc -mtriple riscv64 -mattr=+zicsr,+m,+experimental-v < %s \ ; RUN: | FileCheck %s -check-prefix=RV64 -; RUN: llc -mtriple riscv32 -mattr=+m,+experimental-v < %s \ +; RUN: llc -mtriple riscv32 -mattr=+zicsr,+m,+experimental-v < %s \ ; RUN: | FileCheck %s -check-prefix=RV32 diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; FIXME: The scalar/vector operations ('fv' tests) should swap operands and diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; FIXME: The scalar/vector operations ('fv' tests) should swap operands and diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s define @icmp_eq_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s define @icmp_eq_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll --- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-v,+f \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v,+f \ ; RUN: -riscv-v-vector-bits-min=128 | FileCheck %s define void @sink_splat_mul(i32* nocapture %a, i32 signext %x) { diff --git a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 declare @llvm.experimental.stepvector.nxv1i8() diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.vp.add.nxv8i7(, , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare { , i32 } @llvm.riscv.vleff.nxv1i64( *, diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare { , i64 } @llvm.riscv.vleff.nxv1i64( *, diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+d,+experimental-zvlsseg,+experimental-zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+d,+experimental-zvlsseg,+experimental-zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) @@ -5236,4 +5236,3 @@ store i32 %2, i32* %outvl ret %1 } - diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+d,+experimental-zvlsseg,+experimental-zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+d,+experimental-zvlsseg,+experimental-zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) @@ -5678,4 +5678,3 @@ store i64 %2, i64* %outvl ret %1 } - diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfmerge_vv_nxv1f16( %va, %vb, %cond) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfmerge_vv_nxv1f16( %va, %vb, %cond) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+experimental-v \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+f,+d,+a,+c,+experimental-v \ ; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s ; The following tests check whether inserting VSETVLI avoids inserting diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir --- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir +++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -# RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -o - %s \ +# RUN: llc -mtriple=riscv32 -mattr=+zicsr,+m,+experimental-v -o - %s \ # RUN: -start-before=prologepilog | FileCheck %s # # This test checks that we are assigning the right stack slot to GPRs and to diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir --- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir +++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -# RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -o - %s \ +# RUN: llc -mtriple=riscv64 -mattr=+zicsr,+m,+experimental-v -o - %s \ # RUN: -start-before=prologepilog | FileCheck %s # # This test checks that we are assigning the right stack slot to GPRs and to diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll --- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+d,+experimental-zvlsseg,+experimental-zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -3,77 +3,71 @@ # RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s # RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s -.attribute arch, "rv32i" -# CHECK: attribute 5, "rv32i2p0" +.attribute arch, "rv32i2p1" +# CHECK: attribute 5, "rv32i2p1" -.attribute arch, "rv32i2" -# CHECK: attribute 5, "rv32i2p0" +.attribute arch, "rv32i2p1_m2" +# CHECK: attribute 5, "rv32i2p1_m2p0" -.attribute arch, "rv32i2p0" -# CHECK: attribute 5, "rv32i2p0" - -.attribute arch, "rv32i2_m2" -# CHECK: attribute 5, "rv32i2p0_m2p0" - -.attribute arch, "rv32i2_ma" -# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0" +.attribute arch, "rv32i2p1_ma" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p0" .attribute arch, "rv32g" -# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p0_f2p0_d2p0" .attribute arch, "rv32imafdc" -# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p0_f2p0_d2p0_c2p0" -.attribute arch, "rv32i2p0_mafdc" -# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" +.attribute arch, "rv32i2p1_mafdc" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p0_f2p0_d2p0_c2p0" .attribute arch, "rv32ima2p0_fdc" -# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p0_f2p0_d2p0_c2p0" .attribute arch, "rv32ima2p0_fdc" -# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p0_f2p0_d2p0_c2p0" .attribute arch, "rv32iv" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p1_v0p10_zvlsseg0p10" .attribute arch, "rv32izba" -# CHECK: attribute 5, "rv32i2p0_zba1p0" +# CHECK: attribute 5, "rv32i2p1_zba1p0" .attribute arch, "rv32izbb" -# CHECK: attribute 5, "rv32i2p0_zbb1p0" +# CHECK: attribute 5, "rv32i2p1_zbb1p0" .attribute arch, "rv32izbc" -# CHECK: attribute 5, "rv32i2p0_zbc1p0" +# CHECK: attribute 5, "rv32i2p1_zbc1p0" .attribute arch, "rv32izbe" -# CHECK: attribute 5, "rv32i2p0_zbe0p93" +# CHECK: attribute 5, "rv32i2p1_zbe0p93" .attribute arch, "rv32izbf" -# CHECK: attribute 5, "rv32i2p0_zbf0p93" +# CHECK: attribute 5, "rv32i2p1_zbf0p93" .attribute arch, "rv32izbm" -# CHECK: attribute 5, "rv32i2p0_zbm0p93" +# CHECK: attribute 5, "rv32i2p1_zbm0p93" .attribute arch, "rv32izbp" -# CHECK: attribute 5, "rv32i2p0_zbp0p93" +# CHECK: attribute 5, "rv32i2p1_zbp0p93" .attribute arch, "rv32izbr" -# CHECK: attribute 5, "rv32i2p0_zbr0p93" +# CHECK: attribute 5, "rv32i2p1_zbr0p93" .attribute arch, "rv32izbs" -# CHECK: attribute 5, "rv32i2p0_zbs1p0" +# CHECK: attribute 5, "rv32i2p1_zbs1p0" .attribute arch, "rv32izbt" -# CHECK: attribute 5, "rv32i2p0_zbt0p93" +# CHECK: attribute 5, "rv32i2p1_zbt0p93" .attribute arch, "rv32ifzfhmin" -# CHECK: attribute 5, "rv32i2p0_f2p0_zfhmin0p1" +# CHECK: attribute 5, "rv32i2p1_f2p0_zfhmin0p1" .attribute arch, "rv32ifzfh" -# CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1" +# CHECK: attribute 5, "rv32i2p1_f2p0_zfh0p1_zfhmin0p1" .attribute arch, "rv32ivzvamo_zvlsseg" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p1_v0p10_zvamo0p10_zvlsseg0p10" .attribute arch, "rv32iv_zvamo0p10_zvlsseg" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p1_v0p10_zvamo0p10_zvlsseg0p10" diff --git a/llvm/test/MC/RISCV/attribute-with-insts.s b/llvm/test/MC/RISCV/attribute-with-insts.s --- a/llvm/test/MC/RISCV/attribute-with-insts.s +++ b/llvm/test/MC/RISCV/attribute-with-insts.s @@ -10,7 +10,7 @@ # RUN: | llvm-objdump --triple=riscv64 -d -M no-aliases - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" +.attribute arch, "rv64i2p1_m2p0_a2p0_f2p0_d2p0_c2p0" # CHECK-INST: lr.w t0, (t1) lr.w t0, (t1) diff --git a/llvm/test/MC/RISCV/attribute-with-option.s b/llvm/test/MC/RISCV/attribute-with-option.s --- a/llvm/test/MC/RISCV/attribute-with-option.s +++ b/llvm/test/MC/RISCV/attribute-with-option.s @@ -9,7 +9,7 @@ # RUN: llvm-mc %s -triple=riscv32 -mattr=+e -filetype=obj -o - \ # RUN: | llvm-readobj -A - | FileCheck %s -.attribute arch, "rv32i2p0" +.attribute arch, "rv32i2p1" ## Invalid operand for RV32E, because x16 is an invalid register for RV32E. ## Use RV32I to assemble, since it will not trigger an assembly error. lui x16, 1 @@ -18,4 +18,4 @@ ## option. # CHECK: Tag: 5 # CHECK-NEXT: TagName: arch -# CHECK-NEXT: Value: rv32i2p0 +# CHECK-NEXT: Value: rv32i2p1 diff --git a/llvm/test/MC/RISCV/attribute.s b/llvm/test/MC/RISCV/attribute.s --- a/llvm/test/MC/RISCV/attribute.s +++ b/llvm/test/MC/RISCV/attribute.s @@ -6,8 +6,8 @@ .attribute stack_align, 16 # CHECK: attribute 4, 16 -.attribute arch, "rv32i2p0_m2p0_a2p0_c2p0" -# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_c2p0" +.attribute arch, "rv32i2p1_m2p0_a2p0_c2p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p0_c2p0" .attribute unaligned_access, 0 # CHECK: attribute 6, 0 diff --git a/llvm/test/MC/RISCV/csr-aliases.s b/llvm/test/MC/RISCV/csr-aliases.s --- a/llvm/test/MC/RISCV/csr-aliases.s +++ b/llvm/test/MC/RISCV/csr-aliases.s @@ -1,39 +1,39 @@ -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f -M no-aliases - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,-f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \ -# RUN: | llvm-objdump -d --mattr=-f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,-f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,-f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=-f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,-f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f -M no-aliases - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,-f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \ -# RUN: | llvm-objdump -d --mattr=-f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,-f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,-f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=-f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,-f - \ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s @@ -114,4 +114,3 @@ # CHECK-EXT-F: fsflagsi 31 # CHECK-EXT-F-OFF: csrwi fflags, 31 csrrwi zero, 1, 31 - diff --git a/llvm/test/MC/RISCV/deprecated-csr-names.s b/llvm/test/MC/RISCV/deprecated-csr-names.s --- a/llvm/test/MC/RISCV/deprecated-csr-names.s +++ b/llvm/test/MC/RISCV/deprecated-csr-names.s @@ -1,16 +1,16 @@ -# RUN: llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding %s \ # RUN: | FileCheck -check-prefixes CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype obj -triple riscv32 %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype obj -triple riscv32 -mattr=+zicsr %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s -# RUN: llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding %s \ +# RUN: llvm-mc -triple riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding %s \ # RUN: | FileCheck -check-prefixes CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype obj -triple riscv64 %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype obj -triple riscv64 -mattr=+zicsr %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s -# RUN: llvm-mc -triple riscv32 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s +# RUN: llvm-mc -triple riscv32 -mattr=+zicsr %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s # sbadaddr # name diff --git a/llvm/test/MC/RISCV/invalid-attribute.s b/llvm/test/MC/RISCV/invalid-attribute.s --- a/llvm/test/MC/RISCV/invalid-attribute.s +++ b/llvm/test/MC/RISCV/invalid-attribute.s @@ -9,8 +9,8 @@ .attribute arch, "foo" # CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g} or rv64{i,g} -.attribute arch, "rv32i2p0_y2p0" -# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p0_y2p0', invalid standard user-level extension 'y' +.attribute arch, "rv32i2p1_y2p0" +# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_y2p0', invalid standard user-level extension 'y' .attribute stack_align, "16" # CHECK: [[@LINE-1]]:25: error: expected numeric constant diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -1,13 +1,13 @@ -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s # -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s ################################## diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s --- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s ###################################### @@ -471,4 +471,3 @@ csrrs t1, mhpmcounter31h, zero # uimm12 csrrs t2, 0xB9F, zero - diff --git a/llvm/test/MC/RISCV/rv32-user-csr-names.s b/llvm/test/MC/RISCV/rv32-user-csr-names.s --- a/llvm/test/MC/RISCV/rv32-user-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-user-csr-names.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s ################################## diff --git a/llvm/test/MC/RISCV/rv32e-valid.s b/llvm/test/MC/RISCV/rv32e-valid.s --- a/llvm/test/MC/RISCV/rv32e-valid.s +++ b/llvm/test/MC/RISCV/rv32e-valid.s @@ -95,8 +95,6 @@ fence iorw, iorw # CHECK-ASM-AND-OBJ: fence.tso fence.tso -# CHECK-ASM-AND-OBJ: fence.i -fence.i # CHECK-ASM-AND-OBJ: ecall ecall @@ -104,18 +102,3 @@ ebreak # CHECK-ASM-AND-OBJ: unimp unimp - -# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 -csrrw t0, 0xfff, t1 -# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero -csrrs s0, 0xc00, x0 -# CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5 -csrrs s0, 0x001, a5 -# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra -csrrc sp, 0x000, ra -# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 -csrrwi a5, 0x000, 0 -# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 -csrrsi t2, 0xfff, 31 -# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5 -csrrci t1, 0x140, 5 diff --git a/llvm/test/MC/RISCV/rv32i-aliases-valid.s b/llvm/test/MC/RISCV/rv32i-aliases-valid.s --- a/llvm/test/MC/RISCV/rv32i-aliases-valid.s +++ b/llvm/test/MC/RISCV/rv32i-aliases-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr \ # RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-EXPAND,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s # The following check prefixes are used in this test: diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -12,23 +12,11 @@ slli a0, a0, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] srli a0, a0, -1 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] srai a0, a0, -19 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] -csrrwi a1, 0x1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] -csrrsi t1, 999, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] -csrrci x0, 43, -90 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] ## simm12 ori a0, a1, -2049 # CHECK: :[[@LINE]]:13: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] andi ra, sp, 2048 # CHECK: :[[@LINE]]:14: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] -## uimm12 -csrrw a0, -1, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] -csrrs a0, 4096, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] -csrrs a0, -0xf, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] -csrrc a0, 0x1000, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] -csrrwi a0, -50, 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] -csrrsi a0, 4097, a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] -csrrci a0, 0xffff, a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] - ## simm13_lsb0 beq t0, t1, -4098 # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] bne t0, t1, -4097 # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] @@ -60,11 +48,6 @@ slli a0, a0, %lo(1) # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] srli a0, a0, %lo(a) # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] srai a0, a0, %hi(2) # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] -csrrwi a1, 0x1, %hi(b) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] -csrrsi t1, 999, %pcrel_hi(3) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] -csrrci x0, 43, %pcrel_hi(c) # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -csrrsi t1, 999, %pcrel_lo(4) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] -csrrci x0, 43, %pcrel_lo(d) # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] ## simm12 ori a0, a1, %hi(foo) # CHECK: :[[@LINE]]:13: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] @@ -73,26 +56,6 @@ add a1, a2, (a3) # CHECK: :[[@LINE]]:13: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] add a1, a2, foo # CHECK: :[[@LINE]]:13: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] -## uimm12 -csrrw a0, %lo(1), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] -csrrs a0, %lo(a), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] -csrrs a0, %hi(2), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] -csrrc a0, %hi(b), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] -csrrwi a0, %pcrel_hi(3), 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] -csrrsi a0, %pcrel_hi(c), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] -csrrwi a0, %pcrel_lo(4), 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] -csrrsi a0, %pcrel_lo(d), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] - -## named csr in place of uimm12 -csrrw a0, foos, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] -csrrs a0, mstatusx, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] -csrrs a0, xmstatus, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] -csrrc a0, m12status, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] -csrrwi a0, mstatus12, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] -csrrsi a0, mhpm12counter, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] -csrrwi a0, mhpmcounter32, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] -csrrsi a0, A, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] - ## simm13_lsb0 beq t0, t1, %lo(1) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] bne t0, t1, %lo(a) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s --- a/llvm/test/MC/RISCV/rv32i-valid.s +++ b/llvm/test/MC/RISCV/rv32i-valid.s @@ -330,10 +330,6 @@ # CHECK-ASM: encoding: [0x0f,0x00,0x30,0x83] fence.tso -# CHECK-ASM-AND-OBJ: fence.i -# CHECK-ASM: encoding: [0x0f,0x10,0x00,0x00] -fence.i - # CHECK-ASM-AND-OBJ: ecall # CHECK-ASM: encoding: [0x73,0x00,0x00,0x00] ecall @@ -345,31 +341,3 @@ unimp .equ CONST, 16 - -# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 -# CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff] -csrrw t0, 0xfff, t1 -# CHECK-ASM-AND-OBJ: csrrw s0, 4095, s1 -# CHECK-ASM: encoding: [0x73,0x94,0xf4,0xff] -csrrw s0, ~(-4096), s1 -# CHECK-ASM-AND-OBJ: csrrw s0, fflags, s1 -# CHECK-ASM: encoding: [0x73,0x94,0x14,0x00] -csrrw s0, !0, s1 -# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero -# CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0] -csrrs s0, 0xc00, x0 -# CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5 -# CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00] -csrrs s3, 0x001, s5 -# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra -# CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00] -csrrc sp, 0x000, ra -# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 -# CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00] -csrrwi a5, 0x000, 0 -# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 -# CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff] -csrrsi t2, 0xfff, 31 -# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5 -# CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14] -csrrci t1, 0x140, 5 diff --git a/llvm/test/MC/RISCV/rv32zicsr-invalid.s b/llvm/test/MC/RISCV/rv32zicsr-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zicsr-invalid.s @@ -0,0 +1,44 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+zicsr < %s 2>&1 | FileCheck %s + +# Out of range immediates +## uimm5 +csrrwi a1, 0x1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] +csrrsi t1, 999, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] +csrrci x0, 43, -90 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] + +## uimm12 +csrrw a0, -1, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] +csrrs a0, 4096, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] +csrrs a0, -0xf, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] +csrrc a0, 0x1000, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] +csrrwi a0, -50, 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] +csrrsi a0, 4097, a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] +csrrci a0, 0xffff, a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] + +# Illegal operand modifier +## uimm5 +csrrwi a1, 0x1, %hi(b) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] +csrrsi t1, 999, %pcrel_hi(3) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] +csrrci x0, 43, %pcrel_hi(c) # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] +csrrsi t1, 999, %pcrel_lo(4) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] +csrrci x0, 43, %pcrel_lo(d) # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] + +## uimm12 +csrrw a0, %lo(1), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] +csrrs a0, %lo(a), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] +csrrs a0, %hi(2), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] +csrrc a0, %hi(b), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] +csrrwi a0, %pcrel_hi(3), 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] +csrrsi a0, %pcrel_hi(c), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] +csrrwi a0, %pcrel_lo(4), 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] +csrrsi a0, %pcrel_lo(d), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] + +## named csr in place of uimm12 +csrrw a0, foos, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrs a0, mstatusx, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrs a0, xmstatus, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrc a0, m12status, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrwi a0, mstatus12, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrsi a0, mhpm12counter, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrwi a0, mhpmcounter32, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrsi a0, A, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] diff --git a/llvm/test/MC/RISCV/rv32zicsr-valid.s b/llvm/test/MC/RISCV/rv32zicsr-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zicsr-valid.s @@ -0,0 +1,32 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 +# CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff] +csrrw t0, 0xfff, t1 +# CHECK-ASM-AND-OBJ: csrrw s0, 4095, s1 +# CHECK-ASM: encoding: [0x73,0x94,0xf4,0xff] +csrrw s0, ~(-4096), s1 +# CHECK-ASM-AND-OBJ: csrrw s0, fflags, s1 +# CHECK-ASM: encoding: [0x73,0x94,0x14,0x00] +csrrw s0, !0, s1 +# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero +# CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0] +csrrs s0, 0xc00, x0 +# CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5 +# CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00] +csrrs s3, 0x001, s5 +# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra +# CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00] +csrrc sp, 0x000, ra +# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 +# CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00] +csrrwi a5, 0x000, 0 +# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 +# CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff] +csrrsi t2, 0xfff, 31 +# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5 +# CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14] +csrrci t1, 0x140, 5 diff --git a/llvm/test/MC/RISCV/rv32zifencei-valid.s b/llvm/test/MC/RISCV/rv32zifencei-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zifencei-valid.s @@ -0,0 +1,8 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zifencei -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple riscv64 -mattr=+zifencei -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: fence.i +# CHECK-ASM: encoding: [0x0f,0x10,0x00,0x00] +fence.i diff --git a/llvm/test/MC/RISCV/rv64-machine-csr-names.s b/llvm/test/MC/RISCV/rv64-machine-csr-names.s --- a/llvm/test/MC/RISCV/rv64-machine-csr-names.s +++ b/llvm/test/MC/RISCV/rv64-machine-csr-names.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s # These machine mode CSR register names are RV32 only, but RV64 diff --git a/llvm/test/MC/RISCV/rv64-user-csr-names.s b/llvm/test/MC/RISCV/rv64-user-csr-names.s --- a/llvm/test/MC/RISCV/rv64-user-csr-names.s +++ b/llvm/test/MC/RISCV/rv64-user-csr-names.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s # These user mode CSR register names are RV32 only, but RV64 diff --git a/llvm/test/MC/RISCV/rvf-aliases-valid.s b/llvm/test/MC/RISCV/rvf-aliases-valid.s --- a/llvm/test/MC/RISCV/rvf-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvf-aliases-valid.s @@ -1,22 +1,22 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr,+f -riscv-no-aliases \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+f \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr,+f \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr,+f -riscv-no-aliases \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+f \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr,+f \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f -M no-aliases - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f -M no-aliases - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s ##===----------------------------------------------------------------------===## diff --git a/llvm/test/MC/RISCV/rvf-user-csr-names.s b/llvm/test/MC/RISCV/rvf-user-csr-names.s --- a/llvm/test/MC/RISCV/rvf-user-csr-names.s +++ b/llvm/test/MC/RISCV/rvf-user-csr-names.s @@ -1,19 +1,19 @@ -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+zicsr,+f -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s # -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+zicsr,+f -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d --mattr=+f - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+f - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+f < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s ################################## @@ -67,5 +67,3 @@ csrrs t1, fcsr, zero # uimm12 csrrs t2, 0x003, zero - - diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s --- a/llvm/test/MC/RISCV/rvi-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -1,22 +1,22 @@ -# RUN: llvm-mc %s -triple=riscv32 -M no-aliases \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -M no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS %s -# RUN: llvm-mc %s -triple=riscv32 \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr \ # RUN: | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -M no-aliases \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -M no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS %s -# RUN: llvm-mc %s -triple=riscv64 \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr \ # RUN: | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -d -r -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -d -r -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s # The following check prefixes are used in this test: @@ -207,49 +207,6 @@ # CHECK-S-OBJ: rdtime s9 rdtime x25 -# CHECK-S-OBJ-NOALIAS: csrrs s0, 336, zero -# CHECK-S-OBJ: csrr s0, 336 -csrr x8, 0x150 -# CHECK-S-OBJ-NOALIAS: csrrw zero, sscratch, s1 -# CHECK-S-OBJ: csrw sscratch, s1 -csrw 0x140, x9 -# CHECK-S-OBJ-NOALIAS: csrrs zero, 4095, s6 -# CHECK-S-OBJ: csrs 4095, s6 -csrs 0xfff, x22 -# CHECK-S-OBJ-NOALIAS: csrrc zero, 4095, s7 -# CHECK-S-OBJ: csrc 4095, s7 -csrc 0xfff, x23 - -# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 15 -# CHECK-S-OBJ: csrwi 336, 15 -csrwi 0x150, 0xf -# CHECK-S-OBJ-NOALIAS: csrrsi zero, 4095, 16 -# CHECK-S-OBJ: csrsi 4095, 16 -csrsi 0xfff, 0x10 -# CHECK-S-OBJ-NOALIAS: csrrci zero, sscratch, 17 -# CHECK-S-OBJ: csrci sscratch, 17 -csrci 0x140, 0x11 - -# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 7 -# CHECK-S-OBJ: csrwi 336, 7 -csrw 0x150, 7 -# CHECK-S-OBJ-NOALIAS: csrrsi zero, 336, 7 -# CHECK-S-OBJ: csrsi 336, 7 -csrs 0x150, 7 -# CHECK-S-OBJ-NOALIAS: csrrci zero, 336, 7 -# CHECK-S-OBJ: csrci 336, 7 -csrc 0x150, 7 - -# CHECK-S-OBJ-NOALIAS: csrrwi t0, 336, 15 -# CHECK-S-OBJ: csrrwi t0, 336, 15 -csrrw t0, 0x150, 0xf -# CHECK-S-OBJ-NOALIAS: csrrsi t0, 4095, 16 -# CHECK-S-OBJ: csrrsi t0, 4095, 16 -csrrs t0, 0xfff, 0x10 -# CHECK-S-OBJ-NOALIAS: csrrci t0, sscratch, 17 -# CHECK-S-OBJ: csrrci t0, sscratch, 17 -csrrc t0, 0x140, 0x11 - # CHECK-S-OBJ-NOALIAS: sfence.vma zero, zero # CHECK-S-OBJ: sfence.vma sfence.vma diff --git a/llvm/test/MC/RISCV/rvv-user-csr-names.s b/llvm/test/MC/RISCV/rvv-user-csr-names.s --- a/llvm/test/MC/RISCV/rvv-user-csr-names.s +++ b/llvm/test/MC/RISCV/rvv-user-csr-names.s @@ -1,13 +1,13 @@ -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+zicsr,+f -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+v < %s \ -# RUN: | llvm-objdump -d --mattr=+v - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr,+v < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+v - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s # -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+zicsr,+f -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+v < %s \ -# RUN: | llvm-objdump -d --mattr=+v - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr,+v < %s \ +# RUN: | llvm-objdump -d --mattr=+zicsr,+v - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s ################################## diff --git a/llvm/test/MC/RISCV/rvzicsr-aliases-valid.s b/llvm/test/MC/RISCV/rvzicsr-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvzicsr-aliases-valid.s @@ -0,0 +1,55 @@ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r -M no-aliases - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r -M no-aliases - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s + +# CHECK-OBJ-NOALIAS: csrrs s0, 336, zero +# CHECK-OBJ: csrr s0, 336 +csrr x8, 0x150 +# CHECK-OBJ-NOALIAS: csrrw zero, sscratch, s1 +# CHECK-OBJ: csrw sscratch, s1 +csrw 0x140, x9 +# CHECK-OBJ-NOALIAS: csrrs zero, 4095, s6 +# CHECK-OBJ: csrs 4095, s6 +csrs 0xfff, x22 +# CHECK-OBJ-NOALIAS: csrrc zero, 4095, s7 +# CHECK-OBJ: csrc 4095, s7 +csrc 0xfff, x23 + +# CHECK-OBJ-NOALIAS: csrrwi zero, 336, 15 +# CHECK-OBJ: csrwi 336, 15 +csrwi 0x150, 0xf +# CHECK-OBJ-NOALIAS: csrrsi zero, 4095, 16 +# CHECK-OBJ: csrsi 4095, 16 +csrsi 0xfff, 0x10 +# CHECK-OBJ-NOALIAS: csrrci zero, sscratch, 17 +# CHECK-OBJ: csrci sscratch, 17 +csrci 0x140, 0x11 + +# CHECK-OBJ-NOALIAS: csrrwi zero, 336, 7 +# CHECK-OBJ: csrwi 336, 7 +csrw 0x150, 7 +# CHECK-OBJ-NOALIAS: csrrsi zero, 336, 7 +# CHECK-OBJ: csrsi 336, 7 +csrs 0x150, 7 +# CHECK-OBJ-NOALIAS: csrrci zero, 336, 7 +# CHECK-OBJ: csrci 336, 7 +csrc 0x150, 7 + +# CHECK-OBJ-NOALIAS: csrrwi t0, 336, 15 +# CHECK-OBJ: csrrwi t0, 336, 15 +csrrw t0, 0x150, 0xf +# CHECK-OBJ-NOALIAS: csrrsi t0, 4095, 16 +# CHECK-OBJ: csrrsi t0, 4095, 16 +csrrs t0, 0xfff, 0x10 +# CHECK-OBJ-NOALIAS: csrrci t0, sscratch, 17 +# CHECK-OBJ: csrrci t0, sscratch, 17 +csrrc t0, 0x140, 0x11 diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s --- a/llvm/test/MC/RISCV/supervisor-csr-names.s +++ b/llvm/test/MC/RISCV/supervisor-csr-names.s @@ -1,13 +1,13 @@ -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s # -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s ################################## diff --git a/llvm/test/MC/RISCV/user-csr-names.s b/llvm/test/MC/RISCV/user-csr-names.s --- a/llvm/test/MC/RISCV/user-csr-names.s +++ b/llvm/test/MC/RISCV/user-csr-names.s @@ -1,13 +1,13 @@ -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s # -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -d - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr < %s \ +# RUN: | llvm-objdump --mattr=+zicsr -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s ################################## diff --git a/llvm/test/tools/llvm-objdump/ELF/RISCV/unknown-arch-attr.test b/llvm/test/tools/llvm-objdump/ELF/RISCV/unknown-arch-attr.test --- a/llvm/test/tools/llvm-objdump/ELF/RISCV/unknown-arch-attr.test +++ b/llvm/test/tools/llvm-objdump/ELF/RISCV/unknown-arch-attr.test @@ -3,7 +3,7 @@ ## The expected behavior is to ignore the unrecognized arch feature and ## continue to process the following arch features. ## -## The object file has the "rv32i2p0_x1p0_m2p0" arch feature. "x1p0" is an +## The object file has the "rv32i2p1_x1p0_m2p0" arch feature. "x1p0" is an ## unrecognized architecture extension. llvm-objdump will ignore it and decode ## "mul" instruction correctly according to "m2p0" in the arch feature. ## @@ -34,5 +34,5 @@ Content: 3385C502 - Name: .riscv.attributes Type: SHT_RISCV_ATTRIBUTES -## The content is the encoding of the arch feature "rv32i2p0_x1p0_m2p0" +## The content is the encoding of the arch feature "rv32i2p1_x1p0_m2p0" Content: 412300000072697363760001190000000572763332693270305F783170305F6D32703000 diff --git a/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s b/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s --- a/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s +++ b/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s @@ -17,10 +17,10 @@ # CHECK-OBJ-NEXT: TagName: stack_align # CHECK-OBJ-NEXT: Description: Stack alignment is 16-bytes -.attribute Tag_arch, "rv32i2p0_m2p0_a2p0_c2p0" +.attribute Tag_arch, "rv32i2p1_m2p0_a2p0_c2p0" # CHECK-OBJ: Tag: 5 # CHECK-OBJ-NEXT: TagName: arch -# CHECK-OBJ-NEXT: Value: rv32i2p0_m2p0_a2p0_c2p0 +# CHECK-OBJ-NEXT: Value: rv32i2p1_m2p0_a2p0_c2p0 .attribute Tag_unaligned_access, 0 # CHECK-OBJ: Tag: 6