diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -65,6 +65,8 @@
     {"zvlsseg", RISCVExtensionVersion{0, 10}},
 
     {"zfh", RISCVExtensionVersion{0, 1}},
+
+    {"zifencei", RISCVExtensionVersion{2, 0}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -168,6 +168,13 @@
                                AssemblerPredicate<(all_of FeatureStdExtZvamo),
                                "'Zvamo' (Vector AMO Operations)">;
 
+def FeatureStdExtZifencei
+    : SubtargetFeature<"experimental-zifencei", "HasStdExtZifencei", "true",
+                       "'Zifencei' (Instruction-Fetch Fence)">;
+def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
+                               AssemblerPredicate<(all_of FeatureStdExtZifencei),
+                               "'Zifencei' (Instruction-Fetch Fence)">;
+
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -558,6 +558,7 @@
   let imm12 = {0b1000,0b0011,0b0011};
 }
 
+let Predicates = [HasStdExtZifencei] in
 def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> {
   let rs1 = 0;
   let rd = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -52,6 +52,7 @@
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
+  bool HasStdExtZifencei = false;
   bool HasStdExtZfh = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -118,6 +119,7 @@
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
+  bool hasStdExtZifencei() const { return HasStdExtZifencei; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
diff --git a/llvm/test/MC/RISCV/rv32e-valid.s b/llvm/test/MC/RISCV/rv32e-valid.s
--- a/llvm/test/MC/RISCV/rv32e-valid.s
+++ b/llvm/test/MC/RISCV/rv32e-valid.s
@@ -95,8 +95,6 @@
 fence iorw, iorw
 # CHECK-ASM-AND-OBJ: fence.tso
 fence.tso
-# CHECK-ASM-AND-OBJ: fence.i
-fence.i
 
 # CHECK-ASM-AND-OBJ: ecall
 ecall
diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s
--- a/llvm/test/MC/RISCV/rv32i-valid.s
+++ b/llvm/test/MC/RISCV/rv32i-valid.s
@@ -330,10 +330,6 @@
 # CHECK-ASM: encoding: [0x0f,0x00,0x30,0x83]
 fence.tso
 
-# CHECK-ASM-AND-OBJ: fence.i
-# CHECK-ASM: encoding: [0x0f,0x10,0x00,0x00]
-fence.i
-
 # CHECK-ASM-AND-OBJ: ecall
 # CHECK-ASM: encoding: [0x73,0x00,0x00,0x00]
 ecall
diff --git a/llvm/test/MC/RISCV/rv32zifencei-valid.s b/llvm/test/MC/RISCV/rv32zifencei-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zifencei-valid.s
@@ -0,0 +1,8 @@
+# RUN: llvm-mc %s -triple=riscv32  -mattr=+experimental-zifencei -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple riscv64 -mattr=+experimental-zifencei -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fence.i
+# CHECK-ASM: encoding: [0x0f,0x10,0x00,0x00]
+fence.i