Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3766,6 +3766,19 @@
             (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
   def : Pat<(i64 (to_int_sat f64:$Rn, i64)),
             (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
+
+  def : Pat<(i32 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i32:$scale), i32)),
+            (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
+  def : Pat<(i64 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i64:$scale), i64)),
+            (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
+  def : Pat<(i32 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i32:$scale), i32)),
+            (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
+  def : Pat<(i64 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i64:$scale), i64)),
+            (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
+  def : Pat<(i32 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i32:$scale), i32)),
+            (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
+  def : Pat<(i64 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i64:$scale), i64)),
+            (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
 }
 
 defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
Index: llvm/test/CodeGen/AArch64/fcvt-fixed.ll
===================================================================
--- llvm/test/CodeGen/AArch64/fcvt-fixed.ll
+++ llvm/test/CodeGen/AArch64/fcvt-fixed.ll
@@ -324,10 +324,7 @@
 define i32 @fcvtzs_sat_f32_i32_7(float %flt) {
 ; CHECK-LABEL: fcvtzs_sat_f32_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1124073472
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    fcvtzs w0, s0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
@@ -337,10 +334,7 @@
 define i32 @fcvtzs_sat_f32_i32_32(float %flt) {
 ; CHECK-LABEL: fcvtzs_sat_f32_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1333788672
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    fcvtzs w0, s0, #32
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 4294967296.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
@@ -350,10 +344,7 @@
 define i64 @fcvtzs_sat_f32_i64_64(float %flt) {
 ; CHECK-LABEL: fcvtzs_sat_f32_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1602224128
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzs x0, s0
+; CHECK-NEXT:    fcvtzs x0, s0, #64
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 18446744073709551616.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix)
@@ -363,10 +354,7 @@
 define i32 @fcvtzs_sat_f64_i32_7(double %dbl) {
 ; CHECK-LABEL: fcvtzs_sat_f64_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4638707616191610880
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzs w0, d0
+; CHECK-NEXT:    fcvtzs w0, d0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
@@ -376,10 +364,7 @@
 define i32 @fcvtzs_sat_f64_i32_32(double %dbl) {
 ; CHECK-LABEL: fcvtzs_sat_f64_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4751297606875873280
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzs w0, d0
+; CHECK-NEXT:    fcvtzs w0, d0, #32
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 4294967296.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
@@ -389,10 +374,7 @@
 define i64 @fcvtzs_sat_f64_i64_7(double %dbl) {
 ; CHECK-LABEL: fcvtzs_sat_f64_i64_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4638707616191610880
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzs x0, d0
+; CHECK-NEXT:    fcvtzs x0, d0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
@@ -402,10 +384,7 @@
 define i64 @fcvtzs_sat_f64_i64_64(double %dbl) {
 ; CHECK-LABEL: fcvtzs_sat_f64_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4895412794951729152
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzs x0, d0
+; CHECK-NEXT:    fcvtzs x0, d0, #64
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
@@ -422,10 +401,7 @@
 define i32 @fcvtzu_sat_f32_i32_7(float %flt) {
 ; CHECK-LABEL: fcvtzu_sat_f32_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1124073472
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w0, s0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
@@ -435,10 +411,7 @@
 define i32 @fcvtzu_sat_f32_i32_32(float %flt) {
 ; CHECK-LABEL: fcvtzu_sat_f32_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1333788672
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w0, s0, #32
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 4294967296.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
@@ -448,10 +421,7 @@
 define i64 @fcvtzu_sat_f32_i64_64(float %flt) {
 ; CHECK-LABEL: fcvtzu_sat_f32_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1602224128
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzu x0, s0
+; CHECK-NEXT:    fcvtzu x0, s0, #64
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 18446744073709551616.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix)
@@ -461,10 +431,7 @@
 define i32 @fcvtzu_sat_f64_i32_7(double %dbl) {
 ; CHECK-LABEL: fcvtzu_sat_f64_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4638707616191610880
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    fcvtzu w0, d0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
@@ -474,10 +441,7 @@
 define i32 @fcvtzu_sat_f64_i32_32(double %dbl) {
 ; CHECK-LABEL: fcvtzu_sat_f64_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4751297606875873280
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    fcvtzu w0, d0, #32
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 4294967296.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
@@ -487,10 +451,7 @@
 define i64 @fcvtzu_sat_f64_i64_7(double %dbl) {
 ; CHECK-LABEL: fcvtzu_sat_f64_i64_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4638707616191610880
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzu x0, d0
+; CHECK-NEXT:    fcvtzu x0, d0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
@@ -500,10 +461,7 @@
 define i64 @fcvtzu_sat_f64_i64_64(double %dbl) {
 ; CHECK-LABEL: fcvtzu_sat_f64_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4895412794951729152
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzu x0, d0
+; CHECK-NEXT:    fcvtzu x0, d0, #64
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)