diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1066,7 +1066,7 @@
                        [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
                          imm32SExt16:$DM))]>;
   let isCodeGenOnly = 1 in
-  def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
+  def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsrc:$XA, u2imm:$DM),
                              "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
   def XXSEL : XX4Form<60, 3,
                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
@@ -2842,17 +2842,17 @@
 def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),
           (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>;
 def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)),
-          (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>;
+          (v2i64 (XXPERMDIs (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 0))>;
 def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)),
-          (v2i64 (XXPERMDIs (LFIWAX ForceXForm:$A), 0))>;
+          (v2i64 (XXPERMDIs (SUBREG_TO_REG (i64 1), (LFIWAX ForceXForm:$A), sub_64), 0))>;
 
 // Build vectors of floating point converted to i64.
-def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
-          (v2i64 (XXPERMDIs
-                   (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;
-def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),
-          (v2i64 (XXPERMDIs
-                   (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>;
+def: Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
+      (v2i64 (XXPERMDIs 
+               (SUBREG_TO_REG (i64 1), (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), sub_64), 0))>;
+def: Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),
+      (v2i64 (XXPERMDIs
+               (SUBREG_TO_REG (i64 1), (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), sub_64), 0))>;
 defm : ScalToVecWPermute<
   v2i64, DblToLongLoad.A,
   (XVCVDPSXDS (LXVDSX ForceXForm:$A)), (XVCVDPSXDS (LXVDSX ForceXForm:$A))>;
@@ -3139,12 +3139,12 @@
   (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, FltToLongLoad.A,
-  (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A),
                                                         VSFRC)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, FltToULongLoad.A,
-  (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A),
                                                         VSFRC)), sub_64)>;
 } // HasVSX, NoP9Vector
@@ -3154,11 +3154,11 @@
 // Load-and-splat using only X-Form VSX loads.
 defm : ScalToVecWPermute<
   v2i64, (i64 (load ForceXForm:$src)),
-  (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2f64, (f64 (load ForceXForm:$src)),
-  (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
 } // HasVSX, NoP9Vector, IsLittleEndian
 
@@ -3431,22 +3431,22 @@
 //         zero-extending i32 to i64 (zext i32 -> i64).
 defm : ScalToVecWPermute<
   v2i64, (i64 (sextloadi32 ForceXForm:$src)),
-  (XXPERMDIs (LIWAX ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64)>;
 
 defm : ScalToVecWPermute<
   v2i64, (i64 (zextloadi32 ForceXForm:$src)),
-  (XXPERMDIs (LIWZX ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
 
 defm : ScalToVecWPermute<
   v4i32, (i32 (load ForceXForm:$src)),
-  (XXPERMDIs (LIWZX ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
 
 defm : ScalToVecWPermute<
   v4f32, (f32 (load ForceXForm:$src)),
-  (XXPERMDIs (LIWZX ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
 
 def : Pat<DWToSPExtractConv.BVU,
@@ -3895,7 +3895,7 @@
                          (XXSPLTWs (LXSIBZX ForceXForm:$src), 1),
                          (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64,
-                         (XXPERMDIs (LXSIBZX ForceXForm:$src), 0),
+                         (XXPERMDIs (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64), 0),
                          (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v4i32, ScalarLoads.SELi8,
@@ -3903,7 +3903,7 @@
   (SUBREG_TO_REG (i64 1), (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, ScalarLoads.SELi8i64,
-  (XXPERMDIs (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>;
 
 // Build vectors from i16 loads
@@ -3913,7 +3913,7 @@
   (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, ScalarLoads.ZELi16i64,
-  (XXPERMDIs (LXSIHZX ForceXForm:$src), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v4i32, ScalarLoads.SELi16,
@@ -3921,7 +3921,7 @@
   (SUBREG_TO_REG (i64 1), (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, ScalarLoads.SELi16i64,
-  (XXPERMDIs (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
 
 // Load/convert and convert/store patterns for f16.
@@ -4095,13 +4095,13 @@
   (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, FltToLongLoadP9.A,
-  (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64), 0),
   (SUBREG_TO_REG
      (i64 1),
      (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, FltToULongLoadP9.A,
-  (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64), 0),
   (SUBREG_TO_REG
      (i64 1),
      (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>;
@@ -4584,19 +4584,19 @@
 
 defm : ScalToVecWPermute<
   v2i64, (i64 (load DSForm:$src)),
-  (XXPERMDIs (DFLOADf64 DSForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, (i64 (load XForm:$src)),
-  (XXPERMDIs (XFLOADf64 XForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2f64, (f64 (load DSForm:$src)),
-  (XXPERMDIs (DFLOADf64 DSForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2f64, (f64 (load XForm:$src)),
-  (XXPERMDIs (XFLOADf64 XForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;
 
 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src),
@@ -5092,9 +5092,9 @@
   def : InstAlias<"xxspltd $XT, $XB, 1",
                   (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
   def : InstAlias<"xxspltd $XT, $XB, 0",
-                  (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>;
+                  (XXPERMDIs vsrc:$XT, vsrc:$XB, 0)>;
   def : InstAlias<"xxspltd $XT, $XB, 1",
-                  (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>;
+                  (XXPERMDIs vsrc:$XT, vsrc:$XB, 3)>;
 }
 
 def : InstAlias<"xxmrghd $XT, $XA, $XB",
@@ -5104,7 +5104,7 @@
 def : InstAlias<"xxswapd $XT, $XB",
                 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
 def : InstAlias<"xxswapd $XT, $XB",
-                (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>;
+                (XXPERMDIs vsrc:$XT, vsrc:$XB, 2)>;
 def : InstAlias<"mfvrd $rA, $XT",
                 (MFVRD g8rc:$rA, vrrc:$XT), 0>;
 def : InstAlias<"mffprd $rA, $src",
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -4534,25 +4534,25 @@
 ; P9BE-LABEL: spltRegValConvftoll:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    xscvdpsxds f0, f1
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltRegValConvftoll:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    xscvdpsxds f0, f1
-; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltRegValConvftoll:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    xscvdpsxds f0, f1
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltRegValConvftoll:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xscvdpsxds f0, f1
-; P8LE-NEXT:    xxspltd v2, f0, 0
+; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 entry:
   %conv = fptosi float %val to i64
@@ -4566,7 +4566,7 @@
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfs f0, 0(r3)
 ; P9BE-NEXT:    xscvdpsxds f0, f0
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltMemValConvftoll:
@@ -4580,7 +4580,7 @@
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfsx f0, 0, r3
 ; P8BE-NEXT:    xscvdpsxds f0, f0
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltMemValConvftoll:
@@ -5722,25 +5722,25 @@
 ; P9BE-LABEL: spltRegValConvftoull:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    xscvdpuxds f0, f1
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltRegValConvftoull:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    xscvdpuxds f0, f1
-; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltRegValConvftoull:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    xscvdpuxds f0, f1
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltRegValConvftoull:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xscvdpuxds f0, f1
-; P8LE-NEXT:    xxspltd v2, f0, 0
+; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 entry:
   %conv = fptoui float %val to i64
@@ -5754,7 +5754,7 @@
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfs f0, 0(r3)
 ; P9BE-NEXT:    xscvdpuxds f0, f0
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltMemValConvftoull:
@@ -5768,7 +5768,7 @@
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfsx f0, 0, r3
 ; P8BE-NEXT:    xscvdpuxds f0, f0
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltMemValConvftoull:
diff --git a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
--- a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
+++ b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
@@ -643,7 +643,7 @@
 ; CHECK-P8-NEXT:    sldi r4, r4, 2
 ; CHECK-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P8-NEXT:    lfiwzx f0, r3, r4
-; CHECK-P8-NEXT:    xxspltd v2, f0, 0
+; CHECK-P8-NEXT:    xxspltd v2, vs0, 0
 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
@@ -652,7 +652,7 @@
 ; CHECK-P9-NEXT:    sldi r4, r4, 2
 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    lfiwzx f0, r3, r4
-; CHECK-P9-NEXT:    xxspltd v2, f0, 0
+; CHECK-P9-NEXT:    xxspltd v2, vs0, 0
 ; CHECK-P9-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
@@ -680,7 +680,7 @@
 ; CHECK-P7-NEXT:    sldi r4, r4, 2
 ; CHECK-P7-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P7-NEXT:    lfiwzx f0, r3, r4
-; CHECK-P7-NEXT:    xxspltd v2, f0, 0
+; CHECK-P7-NEXT:    xxspltd v2, vs0, 0
 ; CHECK-P7-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P7-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/load-and-splat.ll b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
--- a/llvm/test/CodeGen/PowerPC/load-and-splat.ll
+++ b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
@@ -143,21 +143,21 @@
 ; P9-LABEL: test5:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lfiwax f0, 0, r4
-; P9-NEXT:    xxspltd vs0, f0, 0
+; P9-NEXT:    xxspltd vs0, vs0, 0
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test5:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwax f0, 0, r4
-; P8-NEXT:    xxspltd vs0, f0, 0
+; P8-NEXT:    xxspltd vs0, vs0, 0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test5:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    lfiwax f0, 0, r4
-; P7-NEXT:    xxspltd vs0, f0, 0
+; P7-NEXT:    xxspltd vs0, vs0, 0
 ; P7-NEXT:    stxvd2x vs0, 0, r3
 ; P7-NEXT:    blr
 entry:
@@ -174,21 +174,21 @@
 ; P9-LABEL: test6:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lfiwzx f0, 0, r4
-; P9-NEXT:    xxspltd vs0, f0, 0
+; P9-NEXT:    xxspltd vs0, vs0, 0
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test6:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwzx f0, 0, r4
-; P8-NEXT:    xxspltd vs0, f0, 0
+; P8-NEXT:    xxspltd vs0, vs0, 0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test6:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    lfiwzx f0, 0, r4
-; P7-NEXT:    xxspltd vs0, f0, 0
+; P7-NEXT:    xxspltd vs0, vs0, 0
 ; P7-NEXT:    stxvd2x vs0, 0, r3
 ; P7-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
--- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
@@ -204,25 +204,25 @@
 ; P9LE-LABEL: s2v_test6:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test6:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfiwax f0, 0, r3
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test6:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxspltd v2, f0, 0
+; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test6:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwax f0, 0, r3
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 
 
@@ -240,25 +240,25 @@
 ; P9LE-LABEL: s2v_test7:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test7:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfiwax f0, 0, r3
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test7:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxspltd v2, f0, 0
+; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test7:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwax f0, 0, r3
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr