diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -101,6 +101,11 @@ extern cl::opt ForceTopDown; extern cl::opt ForceBottomUp; extern cl::opt VerifyScheduling; +#ifndef NDEBUG +extern cl::opt ViewMISchedDAGs; +#else +extern const bool ViewMISchedDAGs; +#endif class AAResults; class LiveIntervals; diff --git a/llvm/include/llvm/CodeGen/VLIWMachineScheduler.h b/llvm/include/llvm/CodeGen/VLIWMachineScheduler.h --- a/llvm/include/llvm/CodeGen/VLIWMachineScheduler.h +++ b/llvm/include/llvm/CodeGen/VLIWMachineScheduler.h @@ -11,23 +11,22 @@ #ifndef LLVM_CODEGEN_VLIWMACHINESCHEDULER_H #define LLVM_CODEGEN_VLIWMACHINESCHEDULER_H +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Twine.h" -#include "llvm/CodeGen/DFAPacketizer.h" #include "llvm/CodeGen/MachineScheduler.h" -#include "llvm/CodeGen/RegisterClassInfo.h" -#include "llvm/CodeGen/ScheduleHazardRecognizer.h" -#include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetSchedule.h" -#include "llvm/CodeGen/TargetSubtargetInfo.h" -#include #include #include #include -#include namespace llvm { +class DFAPacketizer; +class RegisterClassInfo; +class ScheduleHazardRecognizer; class SUnit; +class TargetInstrInfo; +class TargetSubtargetInfo; class VLIWResourceModel { protected: @@ -42,33 +41,17 @@ /// Local packet/bundle model. Purely /// internal to the MI scheduler at the time. - std::vector Packet; + SmallVector Packet; /// Total packets created. unsigned TotalPackets = 0; public: - VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM) - : TII(STI.getInstrInfo()), SchedModel(SM) { - ResourcesModel = createPacketizer(STI); + VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM); - // This hard requirement could be relaxed, - // but for now do not let it proceed. - assert(ResourcesModel && "Unimplemented CreateTargetScheduleState."); + virtual ~VLIWResourceModel(); - Packet.reserve(SchedModel->getIssueWidth()); - Packet.clear(); - ResourcesModel->clearResources(); - } - - virtual ~VLIWResourceModel() { - delete ResourcesModel; - } - - virtual void reset() { - Packet.clear(); - ResourcesModel->clearResources(); - } + virtual void reset(); virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu); virtual bool isResourceAvailable(SUnit *SU, bool IsTop); @@ -78,10 +61,7 @@ bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); } protected: - virtual DFAPacketizer *createPacketizer(const TargetSubtargetInfo &STI) - const { - return STI.getInstrInfo()->CreateTargetScheduleState(STI); - } + virtual DFAPacketizer *createPacketizer(const TargetSubtargetInfo &STI) const; }; /// Extend the standard ScheduleDAGMILive to provide more context and override @@ -123,8 +103,15 @@ }; /// Represent the type of SchedCandidate found within a single queue. enum CandResult { - NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure, - BestCost, Weak}; + NoCand, + NodeOrder, + SingleExcess, + SingleCritical, + SingleMax, + MultiPressure, + BestCost, + Weak + }; // Constants used to denote relative importance of // heuristic components for cost computation. @@ -160,13 +147,10 @@ /// Pending queues extend the ready queues with the same ID and the /// PendingFlag set. VLIWSchedBoundary(unsigned ID, const Twine &Name) - : Available(ID, Name+".A"), - Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P") {} + : Available(ID, Name + ".A"), + Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name + ".P") {} - ~VLIWSchedBoundary() { - delete ResourceModel; - delete HazardRec; - } + ~VLIWSchedBoundary(); void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) { DAG = dag; @@ -228,15 +212,11 @@ VLIWSchedBoundary Bot; /// List of pressure sets that have a high pressure level in the region. - std::vector HighPressureSets; + SmallVector HighPressureSets; public: /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both) - enum { - TopQID = 1, - BotQID = 2, - LogMaxQID = 2 - }; + enum { TopQID = 1, BotQID = 2, LogMaxQID = 2 }; ConvergingVLIWScheduler() : Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {} virtual ~ConvergingVLIWScheduler() = default; @@ -257,16 +237,17 @@ } protected: - virtual VLIWResourceModel *createVLIWResourceModel( - const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const; + virtual VLIWResourceModel * + createVLIWResourceModel(const TargetSubtargetInfo &STI, + const TargetSchedModel *SchedModel) const; SUnit *pickNodeBidrectional(bool &IsTopNode); int pressureChange(const SUnit *SU, bool isBotUp); - virtual int SchedulingCost(ReadyQueue &Q, - SUnit *SU, SchedCandidate &Candidate, - RegPressureDelta &Delta, bool verbose); + virtual int SchedulingCost(ReadyQueue &Q, SUnit *SU, + SchedCandidate &Candidate, RegPressureDelta &Delta, + bool verbose); CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -90,12 +90,17 @@ "verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling")); +#ifndef NDEBUG +cl::opt ViewMISchedDAGs( + "view-misched-dags", cl::Hidden, + cl::desc("Pop up a window to show MISched dags after they are processed")); +#else +const bool ViewMISchedDAGs = false; +#endif // NDEBUG + } // end namespace llvm #ifndef NDEBUG -cl::opt ViewMISchedDAGs("view-misched-dags", cl::Hidden, - cl::desc("Pop up a window to show MISched dags after they are processed")); - /// In some situations a few uninteresting nodes depend on nearly all other /// nodes in the graph, provide a cutoff to hide them. static cl::opt ViewMISchedCutoff("view-misched-cutoff", cl::Hidden, @@ -111,7 +116,6 @@ static cl::opt PrintDAGs("misched-print-dags", cl::Hidden, cl::desc("Print schedule DAGs")); #else -const bool ViewMISchedDAGs = false; static const bool PrintDAGs = false; #endif // NDEBUG diff --git a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp --- a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp +++ b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/VLIWMachineScheduler.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/DFAPacketizer.h" #include "llvm/CodeGen/MachineBasicBlock.h" @@ -19,7 +20,6 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterPressure.h" -#include "llvm/CodeGen/VLIWMachineScheduler.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/ScheduleHazardRecognizer.h" #include "llvm/CodeGen/TargetInstrInfo.h" @@ -42,31 +42,48 @@ #define DEBUG_TYPE "machine-scheduler" -static cl::opt IgnoreBBRegPressure("ignore-bb-reg-pressure", - cl::Hidden, cl::ZeroOrMore, cl::init(false)); +static cl::opt IgnoreBBRegPressure("ignore-bb-reg-pressure", cl::Hidden, + cl::ZeroOrMore, cl::init(false)); -static cl::opt UseNewerCandidate("use-newer-candidate", - cl::Hidden, cl::ZeroOrMore, cl::init(true)); +static cl::opt UseNewerCandidate("use-newer-candidate", cl::Hidden, + cl::ZeroOrMore, cl::init(true)); static cl::opt SchedDebugVerboseLevel("misched-verbose-level", - cl::Hidden, cl::ZeroOrMore, cl::init(1)); + cl::Hidden, cl::ZeroOrMore, + cl::init(1)); // Check if the scheduler should penalize instructions that are available to // early due to a zero-latency dependence. static cl::opt CheckEarlyAvail("check-early-avail", cl::Hidden, - cl::ZeroOrMore, cl::init(true)); + cl::ZeroOrMore, cl::init(true)); // This value is used to determine if a register class is a high pressure set. // We compute the maximum number of registers needed and divided by the total // available. Then, we compare the result to this value. static cl::opt RPThreshold("vliw-misched-reg-pressure", cl::Hidden, - cl::init(0.75f), cl::desc("High register pressure threhold.")); + cl::init(0.75f), + cl::desc("High register pressure threhold.")); -#ifndef NDEBUG -extern cl::opt ViewMISchedDAGs; -#else -const bool ViewMISchedDAGs = false; -#endif // NDEBUG +VLIWResourceModel::VLIWResourceModel(const TargetSubtargetInfo &STI, + const TargetSchedModel *SM) + : TII(STI.getInstrInfo()), SchedModel(SM) { + ResourcesModel = createPacketizer(STI); + + // This hard requirement could be relaxed, + // but for now do not let it proceed. + assert(ResourcesModel && "Unimplemented CreateTargetScheduleState."); + + Packet.reserve(SchedModel->getIssueWidth()); + Packet.clear(); + ResourcesModel->clearResources(); +} + +void VLIWResourceModel::reset() { + Packet.clear(); + ResourcesModel->clearResources(); +} + +VLIWResourceModel::~VLIWResourceModel() { delete ResourcesModel; } /// Return true if there is a dependence between SUd and SUu. bool VLIWResourceModel::hasDependence(const SUnit *SUd, const SUnit *SUu) { @@ -175,6 +192,11 @@ return startNewCycle; } +DFAPacketizer * +VLIWResourceModel::createPacketizer(const TargetSubtargetInfo &STI) const { + return STI.getInstrInfo()->CreateTargetScheduleState(STI); +} + /// schedule - Called back from MachineScheduler::runOnMachineFunction /// after setting up the current scheduling region. [RegionBegin, RegionEnd) /// only includes instructions that have DAG nodes, not scheduling boundaries. @@ -191,7 +213,7 @@ // Postprocess the DAG to add platform-specific artificial dependencies. postprocessDAG(); - SmallVector TopRoots, BotRoots; + SmallVector TopRoots, BotRoots; findRootsAndBiasEdges(TopRoots, BotRoots); // Initialize the strategy before modifying the DAG. @@ -208,7 +230,8 @@ SUnits[su].getDepth(); dbgs() << "Max Depth " << maxD << "\n";); LLVM_DEBUG(dump()); - if (ViewMISchedDAGs) viewGraph(); + if (ViewMISchedDAGs) + viewGraph(); initQueues(TopRoots, BotRoots); @@ -217,7 +240,8 @@ LLVM_DEBUG( dbgs() << "** VLIWMachineScheduler::schedule picking next node\n"); SUnit *SU = SchedImpl->pickNode(IsTopNode); - if (!SU) break; + if (!SU) + break; if (!checkSchedLimit()) break; @@ -242,7 +266,7 @@ } void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) { - DAG = static_cast(dag); + DAG = static_cast(dag); SchedModel = DAG->getSchedModel(); Top.init(DAG, SchedModel); @@ -264,12 +288,12 @@ Bot.ResourceModel = createVLIWResourceModel(STI, DAG->getSchedModel()); const std::vector &MaxPressure = - DAG->getRegPressure().MaxSetPressure; + DAG->getRegPressure().MaxSetPressure; HighPressureSets.assign(MaxPressure.size(), 0); for (unsigned i = 0, e = MaxPressure.size(); i < e; ++i) { unsigned Limit = DAG->getRegClassInfo()->getRegPressureSetLimit(i); HighPressureSets[i] = - ((float) MaxPressure[i] > ((float) Limit * RPThreshold)); + ((float)MaxPressure[i] > ((float)Limit * RPThreshold)); } assert((!ForceTopDown || !ForceBottomUp) && @@ -277,8 +301,7 @@ } VLIWResourceModel *ConvergingVLIWScheduler::createVLIWResourceModel( - const TargetSubtargetInfo &STI, - const TargetSchedModel *SchedModel) const { + const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { return new VLIWResourceModel(STI, SchedModel); } @@ -300,8 +323,8 @@ void ConvergingVLIWScheduler::releaseBottomNode(SUnit *SU) { assert(SU->getInstr() && "Scheduled SUnit must have instr"); - for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) { + for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; + ++I) { unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; unsigned MinLatency = I->getLatency(); #ifndef NDEBUG @@ -315,6 +338,11 @@ Bot.releaseNode(SU, SU->BotReadyCycle); } +ConvergingVLIWScheduler::VLIWSchedBoundary::~VLIWSchedBoundary() { + delete ResourceModel; + delete HazardRec; +} + /// Does this SU have a hazard within the current instruction group. /// /// The scheduler supports two modes of hazard recognition. The first is the @@ -339,8 +367,8 @@ return false; } -void ConvergingVLIWScheduler::VLIWSchedBoundary::releaseNode(SUnit *SU, - unsigned ReadyCycle) { +void ConvergingVLIWScheduler::VLIWSchedBoundary::releaseNode( + SUnit *SU, unsigned ReadyCycle) { if (ReadyCycle < MinReadyCycle) MinReadyCycle = ReadyCycle; @@ -403,8 +431,7 @@ if (startNewCycle) { LLVM_DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n'); bumpCycle(); - } - else + } else LLVM_DEBUG(dbgs() << "*** IssueCount " << IssueCount << " at cycle " << CurrCycle << '\n'); } @@ -419,7 +446,7 @@ // Check to see if any of the pending instructions are ready to issue. If // so, add them to the available queue. for (unsigned i = 0, e = Pending.size(); i != e; ++i) { - SUnit *SU = *(Pending.begin()+i); + SUnit *SU = *(Pending.begin() + i); unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle; if (ReadyCycle < MinReadyCycle) @@ -432,8 +459,9 @@ continue; Available.push(SU); - Pending.remove(Pending.begin()+i); - --i; --e; + Pending.remove(Pending.begin() + i); + --i; + --e; } CheckPending = false; } @@ -460,12 +488,13 @@ return true; if (Available.size() == 1 && Pending.size() > 0) return !ResourceModel->isResourceAvailable(*Available.begin(), isTop()) || - getWeakLeft(*Available.begin(), isTop()) != 0; + getWeakLeft(*Available.begin(), isTop()) != 0; return false; }; for (unsigned i = 0; AdvanceCycle(); ++i) { assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) && - "permanent hazard"); (void)i; + "permanent hazard"); + (void)i; ResourceModel->reserveResources(nullptr, isTop()); bumpCycle(); releasePending(); @@ -477,7 +506,8 @@ #ifndef NDEBUG void ConvergingVLIWScheduler::traceCandidate(const char *Label, - const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P) { + const ReadyQueue &Q, SUnit *SU, + int Cost, PressureChange P) { dbgs() << Label << " " << Q.getName() << " "; if (P.isValid()) dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":" @@ -490,8 +520,8 @@ // Very detailed queue dump, to be used with higher verbosity levels. void ConvergingVLIWScheduler::readyQueueVerboseDump( - const RegPressureTracker &RPTracker, SchedCandidate &Candidate, - ReadyQueue &Q) { + const RegPressureTracker &RPTracker, SchedCandidate &Candidate, + ReadyQueue &Q) { RegPressureTracker &TempTracker = const_cast(RPTracker); dbgs() << ">>> " << Q.getName() << "\n"; @@ -652,12 +682,12 @@ // Factor in reg pressure as a heuristic. if (!IgnoreBBRegPressure) { // Decrease priority by the amount that register pressure exceeds the limit. - ResCount -= (Delta.Excess.getUnitInc()*PriorityOne); + ResCount -= (Delta.Excess.getUnitInc() * PriorityOne); // Decrease priority if register pressure exceeds the limit. - ResCount -= (Delta.CriticalMax.getUnitInc()*PriorityOne); + ResCount -= (Delta.CriticalMax.getUnitInc() * PriorityOne); // Decrease priority slightly if register pressure would increase over the // current maximum. - ResCount -= (Delta.CurrentMax.getUnitInc()*PriorityTwo); + ResCount -= (Delta.CurrentMax.getUnitInc() * PriorityTwo); // If there are register pressure issues, then we remove the value added for // the instruction being available. The rationale is that we really don't // want to schedule an instruction that causes a spill. @@ -733,16 +763,17 @@ /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during /// DAG building. To adjust for the current scheduling location we need to /// maintain the number of vreg uses remaining to be top-scheduled. -ConvergingVLIWScheduler::CandResult ConvergingVLIWScheduler:: -pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, - SchedCandidate &Candidate) { +ConvergingVLIWScheduler::CandResult +ConvergingVLIWScheduler::pickNodeFromQueue(VLIWSchedBoundary &Zone, + const RegPressureTracker &RPTracker, + SchedCandidate &Candidate) { ReadyQueue &Q = Zone.Available; LLVM_DEBUG(if (SchedDebugVerboseLevel > 1) readyQueueVerboseDump(RPTracker, Candidate, Q); else Q.dump();); // getMaxPressureDelta temporarily modifies the tracker. - RegPressureTracker &TempTracker = const_cast(RPTracker); + RegPressureTracker &TempTracker = const_cast(RPTracker); // BestSU remains NULL if no top candidates beat the best existing candidate. CandResult FoundCandidate = NoCand; @@ -767,8 +798,8 @@ // Choose node order for negative cost candidates. There is no good // candidate in this case. if (CurrentCost < 0 && Candidate.SCost < 0) { - if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) - || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { + if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || + (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { LLVM_DEBUG(traceCandidate("NCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; @@ -828,8 +859,8 @@ // To avoid scheduling indeterminism, we need a tie breaker // for the case when cost is identical for two nodes. if (UseNewerCandidate && CurrentCost == Candidate.SCost) { - if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) - || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { + if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || + (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { LLVM_DEBUG(traceCandidate("TCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; @@ -863,8 +894,8 @@ } SchedCandidate BotCand; // Prefer bottom scheduling when heuristics are silent. - CandResult BotResult = pickNodeFromQueue(Bot, - DAG->getBotRPTracker(), BotCand); + CandResult BotResult = + pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand); assert(BotResult != NoCand && "failed to find the first candidate"); // If either Q has a single candidate that provides the least increase in @@ -881,8 +912,8 @@ } // Check if the top Q has a better candidate. SchedCandidate TopCand; - CandResult TopResult = pickNodeFromQueue(Top, - DAG->getTopRPTracker(), TopCand); + CandResult TopResult = + pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand); assert(TopResult != NoCand && "failed to find the first candidate"); if (TopResult == SingleExcess || TopResult == SingleCritical) { @@ -926,7 +957,7 @@ if (!SU) { SchedCandidate TopCand; CandResult TopResult = - pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand); + pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand); assert(TopResult != NoCand && "failed to find the first candidate"); (void)TopResult; SU = TopCand.SU; @@ -937,7 +968,7 @@ if (!SU) { SchedCandidate BotCand; CandResult BotResult = - pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand); + pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand); assert(BotResult != NoCand && "failed to find the first candidate"); (void)BotResult; SU = BotCand.SU; diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h @@ -30,9 +30,9 @@ class HexagonConvergingVLIWScheduler : public ConvergingVLIWScheduler { protected: - VLIWResourceModel *createVLIWResourceModel( - const TargetSubtargetInfo &STI, - const TargetSchedModel *SchedModel) const override; + VLIWResourceModel * + createVLIWResourceModel(const TargetSubtargetInfo &STI, + const TargetSchedModel *SchedModel) const override; int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) override; }; diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -25,7 +25,7 @@ /// Return true if there is a dependence between SUd and SUu. bool HexagonVLIWResourceModel::hasDependence(const SUnit *SUd, const SUnit *SUu) { - const auto *QII = static_cast(TII); + const auto *QII = static_cast(TII); // Enable .cur formation. if (QII->mayBeCurLoad(*SUd->getInstr())) @@ -42,11 +42,12 @@ return new HexagonVLIWResourceModel(STI, SchedModel); } -int HexagonConvergingVLIWScheduler::SchedulingCost( - ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, - RegPressureDelta &Delta, bool verbose) { - int ResCount = ConvergingVLIWScheduler::SchedulingCost(Q, SU, Candidate, - Delta, verbose); +int HexagonConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, + SchedCandidate &Candidate, + RegPressureDelta &Delta, + bool verbose) { + int ResCount = + ConvergingVLIWScheduler::SchedulingCost(Q, SU, Candidate, Delta, verbose); if (!SU || SU->isScheduled) return ResCount;