Index: clang/include/clang/CodeGen/CGFunctionInfo.h =================================================================== --- clang/include/clang/CodeGen/CGFunctionInfo.h +++ clang/include/clang/CodeGen/CGFunctionInfo.h @@ -116,6 +116,7 @@ bool InReg : 1; // isDirect() || isExtend() || isIndirect() bool CanBeFlattened: 1; // isDirect() bool SignExt : 1; // isExtend() + bool ZeroExt : 1; // isExtend() bool canHavePaddingType() const { return isDirect() || isExtend() || isIndirect() || isIndirectAliased() || @@ -137,7 +138,7 @@ PaddingInReg(false), InAllocaSRet(false), InAllocaIndirect(false), IndirectByVal(false), IndirectRealign(false), SRetAfterThis(false), InReg(false), CanBeFlattened(false), - SignExt(false) {} + SignExt(false), ZeroExt(false) {} static ABIArgInfo getDirect(llvm::Type *T = nullptr, unsigned Offset = 0, llvm::Type *Padding = nullptr, @@ -174,12 +175,12 @@ AI.setPaddingType(nullptr); AI.setDirectOffset(0); AI.setDirectAlign(0); - AI.setSignExt(false); + AI.setZeroExt(true); return AI; } // ABIArgInfo will record the argument as being extended based on the sign - // of its type. + // of its type. Produces a sign or zero extension. static ABIArgInfo getExtend(QualType Ty, llvm::Type *T = nullptr) { assert(Ty->isIntegralOrEnumerationType() && "Unexpected QualType"); if (Ty->hasSignedIntegerRepresentation()) @@ -187,6 +188,13 @@ return getZeroExtend(Ty, T); } + // Struct in register marked explicitly as not needing extension. + static ABIArgInfo getNoExtend(llvm::IntegerType *T) { + auto AI = ABIArgInfo(Extend); + AI.setCoerceToType(T); + return AI; + } + static ABIArgInfo getExtendInReg(QualType Ty, llvm::Type *T = nullptr) { auto AI = getExtend(Ty, T); AI.setInReg(true); @@ -326,7 +334,7 @@ } bool isSignExt() const { - assert(isExtend() && "Invalid kind!"); + assert(isExtend() && (SignExt + ZeroExt <= 1) && "Invalid kind / flags!"); return SignExt; } void setSignExt(bool SExt) { @@ -334,6 +342,15 @@ SignExt = SExt; } + bool isZeroExt() const { + assert(isExtend() && (SignExt + ZeroExt <= 1) && "Invalid kind / flags!"); + return ZeroExt; + } + void setZeroExt(bool ZExt) { + assert(isExtend() && "Invalid kind!"); + ZeroExt = ZExt; + } + llvm::Type *getPaddingType() const { return (canHavePaddingType() ? PaddingType : nullptr); } Index: clang/lib/CodeGen/CGCall.cpp =================================================================== --- clang/lib/CodeGen/CGCall.cpp +++ clang/lib/CodeGen/CGCall.cpp @@ -2306,8 +2306,10 @@ case ABIArgInfo::Extend: if (RetAI.isSignExt()) RetAttrs.addAttribute(llvm::Attribute::SExt); - else + else if (RetAI.isZeroExt()) RetAttrs.addAttribute(llvm::Attribute::ZExt); + else + RetAttrs.addAttribute(llvm::Attribute::NoExt); LLVM_FALLTHROUGH; case ABIArgInfo::Direct: if (RetAI.getInReg()) @@ -2442,8 +2444,10 @@ case ABIArgInfo::Extend: if (AI.isSignExt()) Attrs.addAttribute(llvm::Attribute::SExt); - else + else if (AI.isZeroExt()) Attrs.addAttribute(llvm::Attribute::ZExt); + else + Attrs.addAttribute(llvm::Attribute::NoExt); LLVM_FALLTHROUGH; case ABIArgInfo::Direct: if (ArgNo == 0 && FI.isChainCall()) Index: clang/lib/CodeGen/TargetInfo.cpp =================================================================== --- clang/lib/CodeGen/TargetInfo.cpp +++ clang/lib/CodeGen/TargetInfo.cpp @@ -7736,16 +7736,20 @@ return getNaturalAlignIndirect(Ty, /*ByVal=*/false); // The structure is passed as an unextended integer, a float, or a double. - llvm::Type *PassTy; if (isFPArgumentType(SingleElementTy)) { assert(Size == 32 || Size == 64); + llvm::Type *PassTy; if (Size == 32) PassTy = llvm::Type::getFloatTy(getVMContext()); else PassTy = llvm::Type::getDoubleTy(getVMContext()); - } else - PassTy = llvm::IntegerType::get(getVMContext(), Size); - return ABIArgInfo::getDirect(PassTy); + return ABIArgInfo::getDirect(PassTy); + } else { + llvm::IntegerType *PassTy = llvm::IntegerType::get(getVMContext(), Size); + if (Size <= 32) + return ABIArgInfo::getNoExtend(PassTy); + return ABIArgInfo::getDirect(PassTy); + } } // Non-structure compounds are passed indirectly. Index: clang/test/CodeGen/SystemZ/systemz-abi-vector.c =================================================================== --- clang/test/CodeGen/SystemZ/systemz-abi-vector.c +++ clang/test/CodeGen/SystemZ/systemz-abi-vector.c @@ -146,17 +146,17 @@ struct agg_v1i8 { v1i8 a; }; struct agg_v1i8 pass_agg_v1i8(struct agg_v1i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, i8 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, i8 noext %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, <1 x i8> %{{.*}}) struct agg_v2i8 { v2i8 a; }; struct agg_v2i8 pass_agg_v2i8(struct agg_v2i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, i16 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, i16 noext %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, <2 x i8> %{{.*}}) struct agg_v4i8 { v4i8 a; }; struct agg_v4i8 pass_agg_v4i8(struct agg_v4i8 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, i32 noext %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, <4 x i8> %{{.*}}) struct agg_v8i8 { v8i8 a; }; @@ -189,8 +189,8 @@ struct agg_novector3 { v4i8 a; int : 0; }; struct agg_novector3 pass_agg_novector3(struct agg_novector3 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_novector3(%struct.agg_novector3* noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 %{{.*}}) -// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector3(%struct.agg_novector3* noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_novector3(%struct.agg_novector3* noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 noext %{{.*}}) +// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector3(%struct.agg_novector3* noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 noext %{{.*}}) struct agg_novector4 { v4i8 a __attribute__((aligned (8))); }; struct agg_novector4 pass_agg_novector4(struct agg_novector4 arg) { return arg; } Index: clang/test/CodeGen/SystemZ/systemz-abi.c =================================================================== --- clang/test/CodeGen/SystemZ/systemz-abi.c +++ clang/test/CodeGen/SystemZ/systemz-abi.c @@ -86,11 +86,11 @@ struct agg_1byte { char a[1]; }; struct agg_1byte pass_agg_1byte(struct agg_1byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_1byte(%struct.agg_1byte* noalias sret(%struct.agg_1byte) align 1 %{{.*}}, i8 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_1byte(%struct.agg_1byte* noalias sret(%struct.agg_1byte) align 1 %{{.*}}, i8 noext %{{.*}}) struct agg_2byte { char a[2]; }; struct agg_2byte pass_agg_2byte(struct agg_2byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_2byte(%struct.agg_2byte* noalias sret(%struct.agg_2byte) align 1 %{{.*}}, i16 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_2byte(%struct.agg_2byte* noalias sret(%struct.agg_2byte) align 1 %{{.*}}, i16 noext %{{.*}}) struct agg_3byte { char a[3]; }; struct agg_3byte pass_agg_3byte(struct agg_3byte arg) { return arg; } @@ -98,7 +98,7 @@ struct agg_4byte { char a[4]; }; struct agg_4byte pass_agg_4byte(struct agg_4byte arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_4byte(%struct.agg_4byte* noalias sret(%struct.agg_4byte) align 1 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_4byte(%struct.agg_4byte* noalias sret(%struct.agg_4byte) align 1 %{{.*}}, i32 noext %{{.*}}) struct agg_5byte { char a[5]; }; struct agg_5byte pass_agg_5byte(struct agg_5byte arg) { return arg; } @@ -126,7 +126,7 @@ struct agg_float { float a; }; struct agg_float pass_agg_float(struct agg_float arg) { return arg; } // HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_float(%struct.agg_float* noalias sret(%struct.agg_float) align 4 %{{.*}}, float %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_float(%struct.agg_float* noalias sret(%struct.agg_float) align 4 %{{.*}}, i32 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_float(%struct.agg_float* noalias sret(%struct.agg_float) align 4 %{{.*}}, i32 noext %{{.*}}) struct agg_double { double a; }; struct agg_double pass_agg_double(struct agg_double arg) { return arg; } @@ -159,14 +159,14 @@ struct agg_nofloat3 { float a; int : 0; }; struct agg_nofloat3 pass_agg_nofloat3(struct agg_nofloat3 arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat3(%struct.agg_nofloat3* noalias sret(%struct.agg_nofloat3) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat3(%struct.agg_nofloat3* noalias sret(%struct.agg_nofloat3) align 4 %{{.*}}, i32 noext %{{.*}}) // Union types likewise are *not* float-like aggregate types union union_float { float a; }; union union_float pass_union_float(union union_float arg) { return arg; } -// CHECK-LABEL: define{{.*}} void @pass_union_float(%union.union_float* noalias sret(%union.union_float) align 4 %{{.*}}, i32 %{{.*}}) +// CHECK-LABEL: define{{.*}} void @pass_union_float(%union.union_float* noalias sret(%union.union_float) align 4 %{{.*}}, i32 noext %{{.*}}) union union_double { double a; }; union union_double pass_union_double(union union_double arg) { return arg; } Index: clang/test/CodeGen/SystemZ/systemz-abi.cpp =================================================================== --- clang/test/CodeGen/SystemZ/systemz-abi.cpp +++ clang/test/CodeGen/SystemZ/systemz-abi.cpp @@ -7,7 +7,7 @@ class agg_float_class { float a; }; class agg_float_class pass_agg_float_class(class agg_float_class arg) { return arg; } // CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(%class.agg_float_class* noalias sret(%class.agg_float_class) align 4 %{{.*}}, float %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(%class.agg_float_class* noalias sret(%class.agg_float_class) align 4 %{{.*}}, i32 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(%class.agg_float_class* noalias sret(%class.agg_float_class) align 4 %{{.*}}, i32 noext noundef %{{.*}}) class agg_double_class { double a; }; class agg_double_class pass_agg_double_class(class agg_double_class arg) { return arg; } @@ -19,7 +19,7 @@ struct agg_float_cpp { float a; int : 0; }; struct agg_float_cpp pass_agg_float_cpp(struct agg_float_cpp arg) { return arg; } // CHECK-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(%struct.agg_float_cpp* noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(%struct.agg_float_cpp* noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(%struct.agg_float_cpp* noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 noext noundef %{{.*}}) // A field member of empty class type in C++ makes the record nonhomogeneous, @@ -32,7 +32,7 @@ struct agg_float_empty { float a; [[no_unique_address]] empty dummy; }; struct agg_float_empty pass_agg_float_empty(struct agg_float_empty arg) { return arg; } // CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(%struct.agg_float_empty* noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, float %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(%struct.agg_float_empty* noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, i32 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(%struct.agg_float_empty* noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, i32 noext noundef %{{.*}}) struct agg_nofloat_emptyarray { float a; [[no_unique_address]] empty dummy[3]; }; struct agg_nofloat_emptyarray pass_agg_nofloat_emptyarray(struct agg_nofloat_emptyarray arg) { return arg; } // CHECK-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(%struct.agg_nofloat_emptyarray* noalias sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) @@ -48,7 +48,7 @@ struct agg_float_emptybase : emptybase { float a; }; struct agg_float_emptybase pass_agg_float_emptybase(struct agg_float_emptybase arg) { return arg; } // CHECK-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(%struct.agg_float_emptybase* noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float %{{.*}}) -// SOFT-FLOAT-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(%struct.agg_float_emptybase* noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, i32 %{{.*}}) +// SOFT-FLOAT-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(%struct.agg_float_emptybase* noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, i32 noext noundef %{{.*}}) struct noemptybasearray { [[no_unique_address]] empty dummy[3]; }; struct agg_nofloat_emptybasearray : noemptybasearray { float a; }; struct agg_nofloat_emptybasearray pass_agg_nofloat_emptybasearray(struct agg_nofloat_emptybasearray arg) { return arg; } Index: llvm/docs/LangRef.rst =================================================================== --- llvm/docs/LangRef.rst +++ llvm/docs/LangRef.rst @@ -1073,6 +1073,12 @@ Note that any attributes for the function result (``nounwind``, ``readonly``) come immediately after the argument list. +For an integer argument to an externally visible function, it is mandatory to +specify either zeroext, signext or noext. Although this is not significant +for all targets, some depend on this for correctness entirely. For example, +the SystemZ ABI dictates that any passed integer that is 32 bits or less is +either sign or zero extended to 64 bits by the caller. + Currently, only the following parameter attributes are defined: ``zeroext`` @@ -1084,6 +1090,9 @@ value should be sign-extended to the extent required by the target's ABI (which is usually 32-bits) by the caller (for a parameter) or the callee (for a return value). +``noext`` This indicates to the code generator that the parameter or return + value has the high bits undefined, as for a struct in register, and + therefore does not need to be sign or zero extended. ``inreg`` This indicates that this parameter or return value should be treated in a special target-dependent fashion while emitting code for @@ -8185,8 +8194,8 @@ convention ` the call should use. If none is specified, the call defaults to using C calling conventions. #. The optional :ref:`Parameter Attributes ` list for return - values. Only '``zeroext``', '``signext``', and '``inreg``' attributes - are valid here. + values. Only '``zeroext``', '``signext``', '``noext``', and '``inreg``' + attributes are valid here. #. The optional addrspace attribute can be used to indicate the address space of the called function. If it is not specified, the program address space from the :ref:`datalayout string` will be used. @@ -8273,8 +8282,8 @@ convention ` the call should use. If none is specified, the call defaults to using C calling conventions. #. The optional :ref:`Parameter Attributes ` list for return - values. Only '``zeroext``', '``signext``', and '``inreg``' attributes - are valid here. + values. Only '``zeroext``', '``signext``', '``noext``', and '``inreg``' + attributes are valid here. #. The optional addrspace attribute can be used to indicate the address space of the called function. If it is not specified, the program address space from the :ref:`datalayout string` will be used. @@ -11616,8 +11625,8 @@ calling convention of the call must match the calling convention of the target function, or else the behavior is undefined. #. The optional :ref:`Parameter Attributes ` list for return - values. Only '``zeroext``', '``signext``', and '``inreg``' attributes - are valid here. + values. Only '``zeroext``', '``signext``', '``noext``', and '``inreg``' + attributes are valid here. #. The optional addrspace attribute can be used to indicate the address space of the called function. If it is not specified, the program address space from the :ref:`datalayout string` will be used. Index: llvm/include/llvm/Bitcode/LLVMBitCodes.h =================================================================== --- llvm/include/llvm/Bitcode/LLVMBitCodes.h +++ llvm/include/llvm/Bitcode/LLVMBitCodes.h @@ -684,6 +684,7 @@ ATTR_KIND_NO_SANITIZE_BOUNDS = 79, ATTR_KIND_ALLOC_ALIGN = 80, ATTR_KIND_ALLOCATED_POINTER = 81, + ATTR_KIND_NO_EXT = 82, }; enum ComdatSelectionKindCodes { Index: llvm/include/llvm/CodeGen/TargetCallingConv.h =================================================================== --- llvm/include/llvm/CodeGen/TargetCallingConv.h +++ llvm/include/llvm/CodeGen/TargetCallingConv.h @@ -28,6 +28,7 @@ private: unsigned IsZExt : 1; ///< Zero extended unsigned IsSExt : 1; ///< Sign extended + unsigned IsNoExt : 1; ///< No extension (struct in reg) unsigned IsInReg : 1; ///< Passed in register unsigned IsSRet : 1; ///< Hidden struct-ret ptr unsigned IsByVal : 1; ///< Struct passed by value @@ -60,14 +61,14 @@ public: ArgFlagsTy() - : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsByRef(0), - IsNest(0), IsReturned(0), IsSplit(0), IsInAlloca(0), + : IsZExt(0), IsSExt(0), IsNoExt(0), IsInReg(0), IsSRet(0), IsByVal(0), + IsByRef(0), IsNest(0), IsReturned(0), IsSplit(0), IsInAlloca(0), IsPreallocated(0), IsSplitEnd(0), IsSwiftSelf(0), IsSwiftAsync(0), IsSwiftError(0), IsCFGuardTarget(0), IsHva(0), IsHvaStart(0), IsSecArgPass(0), MemAlign(0), OrigAlign(0), IsInConsecutiveRegsLast(0), IsInConsecutiveRegs(0), IsCopyElisionCandidate(0), IsPointer(0) { - static_assert(sizeof(*this) == 3 * sizeof(unsigned), "flags are too big"); + static_assert(sizeof(*this) == 4 * sizeof(unsigned), "flags are too big"); } bool isZExt() const { return IsZExt; } @@ -76,6 +77,9 @@ bool isSExt() const { return IsSExt; } void setSExt() { IsSExt = 1; } + bool isNoExt() const { return IsNoExt; } + void setNoExt() { IsNoExt = 1; } + bool isInReg() const { return IsInReg; } void setInReg() { IsInReg = 1; } Index: llvm/include/llvm/CodeGen/TargetLowering.h =================================================================== --- llvm/include/llvm/CodeGen/TargetLowering.h +++ llvm/include/llvm/CodeGen/TargetLowering.h @@ -284,6 +284,7 @@ Type *Ty = nullptr; bool IsSExt : 1; bool IsZExt : 1; + bool IsNoExt : 1; bool IsInReg : 1; bool IsSRet : 1; bool IsNest : 1; @@ -300,10 +301,11 @@ Type *IndirectType = nullptr; ArgListEntry() - : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), - IsNest(false), IsByVal(false), IsByRef(false), IsInAlloca(false), - IsPreallocated(false), IsReturned(false), IsSwiftSelf(false), - IsSwiftAsync(false), IsSwiftError(false), IsCFGuardTarget(false) {} + : IsSExt(false), IsZExt(false), IsNoExt(false), IsInReg(false), + IsSRet(false), IsNest(false), IsByVal(false), IsByRef(false), + IsInAlloca(false), IsPreallocated(false), IsReturned(false), + IsSwiftSelf(false), IsSwiftAsync(false), IsSwiftError(false), + IsCFGuardTarget(false) {} void setAttributes(const CallBase *Call, unsigned ArgIdx); }; Index: llvm/include/llvm/IR/Attributes.td =================================================================== --- llvm/include/llvm/IR/Attributes.td +++ llvm/include/llvm/IR/Attributes.td @@ -143,6 +143,9 @@ /// Call cannot be duplicated. def NoDuplicate : EnumAttr<"noduplicate", [FnAttr]>; +/// No extension needed before/after call (high bits are undefined). +def NoExt : EnumAttr<"noext", [ParamAttr, RetAttr]>; + /// Function does not deallocate memory. def NoFree : EnumAttr<"nofree", [FnAttr, ParamAttr]>; Index: llvm/lib/AsmParser/LLLexer.cpp =================================================================== --- llvm/lib/AsmParser/LLLexer.cpp +++ llvm/lib/AsmParser/LLLexer.cpp @@ -630,6 +630,7 @@ KEYWORD(c); KEYWORD(attributes); + KEYWORD(noext); KEYWORD(sync); KEYWORD(async); Index: llvm/lib/Bitcode/Reader/BitcodeReader.cpp =================================================================== --- llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -1630,6 +1630,8 @@ return Attribute::ByRef; case bitc::ATTR_KIND_MUSTPROGRESS: return Attribute::MustProgress; + case bitc::ATTR_KIND_NO_EXT: + return Attribute::NoExt; case bitc::ATTR_KIND_HOT: return Attribute::Hot; } Index: llvm/lib/Bitcode/Writer/BitcodeWriter.cpp =================================================================== --- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -771,6 +771,8 @@ return bitc::ATTR_KIND_BYREF; case Attribute::MustProgress: return bitc::ATTR_KIND_MUSTPROGRESS; + case Attribute::NoExt: + return bitc::ATTR_KIND_NO_EXT; case Attribute::EndAttrKinds: llvm_unreachable("Can not encode end-attribute kinds marker."); case Attribute::None: Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2013,6 +2013,8 @@ Flags.setSExt(); else if (ExtendKind == ISD::ZERO_EXTEND) Flags.setZExt(); + else if (F->getAttributes().hasRetAttr(Attribute::NoExt)) + Flags.setNoExt(); for (unsigned i = 0; i < NumParts; ++i) { Outs.push_back(ISD::OutputArg(Flags, @@ -9839,6 +9841,8 @@ Flags.setZExt(); if (Args[i].IsSExt) Flags.setSExt(); + if (Args[i].IsNoExt) + Flags.setNoExt(); if (Args[i].IsInReg) { // If we are using vectorcall calling convention, a structure that is // passed InReg - is surely an HVA Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -110,6 +110,7 @@ unsigned ArgIdx) { IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt); IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); + IsNoExt = Call->paramHasAttr(ArgIdx, Attribute::NoExt); IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg); IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet); IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest); Index: llvm/lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -30,6 +30,15 @@ #define DEBUG_TYPE "systemz-lower" +static cl::opt VerifyIntArgExtensions( + "verify-int-arg-exts", + cl::desc("Verify that narrow int args are properly extended per the ABI."), + cl::Hidden); + +static cl::opt DisableIntArgExtensions( + "no-arg-exts", cl::desc("Disable the default int args extensions."), + cl::Hidden); + namespace { // Represents information about a comparison. struct Comparison { @@ -1329,6 +1338,45 @@ VerifyVectorType(Outs[i].VT, Outs[i].ArgVT); } +// Verify that narrow integer args are extended to 64 bits as required by the +// ABI. An ingoing integer argument may contain a struct, in which case it +// should be marked with 'noext'. +static void VerifyIntegerArg(MVT VT, ISD::ArgFlagsTy Flags) { + if (VT.isInteger()) { + assert((VT == MVT::i32 || VT.getSizeInBits() >= 64) && + "Unexpected integer argument VT."); + assert((VT != MVT::i32 || + (Flags.isSExt() || Flags.isZExt() || Flags.isNoExt())) && + "Narrow integer argument must have a valid extension type!"); + } +} + +// Optionally either verify that all narrow integer arguments have an +// extension attribute, or add sign extension by default in case of no +// attribute. +static void CheckNarrowIntegerArgs(SmallVectorImpl &Outs) { + // Verify that narrow integer args are extended as required by the ABI. + if (VerifyIntArgExtensions) { + for (unsigned i = 0; i < Outs.size(); ++i) + VerifyIntegerArg(Outs[i].VT, Outs[i].Flags); + return; + } + + if (DisableIntArgExtensions) + return; + + // Add sign extension by default if no extension attribute has been + // given. FIXME: This should not really be handled this way, but is "better + // than nothing". Hopefully the above verification can become the default + // instead. + for (unsigned i = 0; i != Outs.size(); ++i) + if (Outs[i].VT == MVT::i32) { + ISD::ArgFlagsTy &ArgFlags = Outs[i].Flags; + if (!ArgFlags.isSExt() && !ArgFlags.isZExt() && !ArgFlags.isNoExt()) + ArgFlags.setSExt(); + } +} + // Value is a value that has been passed to us in the location described by VA // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining // any loads onto Chain. @@ -1650,6 +1698,14 @@ VerifyVectorTypes(Ins); } + // Integer args <=32 bits should have an extension attribute. + bool HasLocalLinkage = false; + if (auto *G = dyn_cast(Callee)) + if (const Function *Fn = dyn_cast(G->getGlobal())) + HasLocalLinkage = Fn->hasLocalLinkage(); + if (!HasLocalLinkage) + CheckNarrowIntegerArgs(Outs); + // Analyze the operands of the call, assigning locations to each operand. SmallVector ArgLocs; SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx); @@ -1913,6 +1969,10 @@ if (Subtarget.hasVector()) VerifyVectorTypes(Outs); + // Integer args <=32 bits should have an extension attribute. + if (!MF.getFunction().hasLocalLinkage()) + CheckNarrowIntegerArgs(const_cast &>(Outs)); + // Assign locations to each returned value. SmallVector RetLocs; CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext()); Index: llvm/lib/Transforms/Utils/CodeExtractor.cpp =================================================================== --- llvm/lib/Transforms/Utils/CodeExtractor.cpp +++ llvm/lib/Transforms/Utils/CodeExtractor.cpp @@ -974,6 +974,7 @@ case Attribute::Nest: case Attribute::NoAlias: case Attribute::NoCapture: + case Attribute::NoExt: case Attribute::NoUndef: case Attribute::NonNull: case Attribute::Preallocated: Index: llvm/test/CodeGen/SystemZ/and-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/and-02.ll +++ llvm/test/CodeGen/SystemZ/and-02.ll @@ -1,6 +1,6 @@ ; Test 32-bit ANDs in which the second operand is constant. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; ANDs with 1 can use NILF. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/and-07.ll =================================================================== --- llvm/test/CodeGen/SystemZ/and-07.ll +++ llvm/test/CodeGen/SystemZ/and-07.ll @@ -1,6 +1,6 @@ ; Test the three-operand forms of AND. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check NRK. define i32 @f1(i32 %a, i32 %b, i32 %c) { Index: llvm/test/CodeGen/SystemZ/args-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/args-01.ll +++ llvm/test/CodeGen/SystemZ/args-01.ll @@ -1,5 +1,5 @@ -; Test the handling of GPR, FPR and stack arguments when no extension -; type is given. This type of argument is used for passing structures, etc. +; Test the handling of GPR, FPR and stack arguments with the noext attribute. +; This type of argument is used for passing structures, etc. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FLOAT @@ -8,8 +8,9 @@ ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-STACK -declare void @bar(i8, i16, i32, i64, float, double, fp128, i64, - float, double, i8, i16, i32, i64, float, double, fp128) +declare void @bar(i8 noext, i16 noext, i32 noext, i64, float, double, fp128, i64, + float, double, i8 noext, i16 noext, i32 noext, i64, float, + double, fp128) ; There are two indirect fp128 slots, one at offset 224 (the first available ; byte after the outgoing arguments) and one immediately after it at 240. Index: llvm/test/CodeGen/SystemZ/args-04.ll =================================================================== --- llvm/test/CodeGen/SystemZ/args-04.ll +++ llvm/test/CodeGen/SystemZ/args-04.ll @@ -1,7 +1,8 @@ ; Test incoming GPR, FPR and stack arguments when no extension type is given. ; This type of argument is used for passing structures, etc. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs -no-arg-exts \ +; RUN: | FileCheck %s ; Do some arithmetic so that we can see the register being used. define i8 @f1(i8 %r2) { Index: llvm/test/CodeGen/SystemZ/args-11.ll =================================================================== --- llvm/test/CodeGen/SystemZ/args-11.ll +++ llvm/test/CodeGen/SystemZ/args-11.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test outgoing promoted arguments that are split (and passed by reference). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; The i96 arg is promoted to i128 and should get the full stack space. declare void @fn1(i96) Index: llvm/test/CodeGen/SystemZ/args-12.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/args-12.ll @@ -0,0 +1,11 @@ +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \ +; RUN: | FileCheck %s +; REQUIRES: asserts +; +; Test detection of missing extension of an i32 return value. + +define i32 @callee_MissingRetAttr() { + ret i32 -1 +} + +; CHECK: Narrow integer argument must have a valid extension type Index: llvm/test/CodeGen/SystemZ/args-13.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/args-13.ll @@ -0,0 +1,11 @@ +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \ +; RUN: | FileCheck %s +; REQUIRES: asserts +; +; Test detection of missing extension of an i16 return value. + +define i16 @callee_MissingRetAttr() { + ret i16 -1 +} + +; CHECK: Narrow integer argument must have a valid extension type Index: llvm/test/CodeGen/SystemZ/args-14.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/args-14.ll @@ -0,0 +1,11 @@ +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \ +; RUN: | FileCheck %s +; REQUIRES: asserts +; +; Test detection of missing extension of an i8 return value. + +define i8 @callee_MissingRetAttr() { + ret i8 -1 +} + +; CHECK: Narrow integer argument must have a valid extension type Index: llvm/test/CodeGen/SystemZ/args-15.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/args-15.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts + +; Test that it works to pass structs as outgoing call arguments when the +; NoExt attribute is given, either in the call instruction or in the +; prototype of the called function. +define void @caller() { + call void @bar_Struct_32(i32 noext 123) + call void @bar_Struct_16(i16 123) + call void @bar_Struct_8(i8 noext 123) + ret void +} + +declare void @bar_Struct_32(i32 %Arg) +declare void @bar_Struct_16(i16 noext %Arg) +declare void @bar_Struct_8(i8 %Arg) + +; Test that it works to return values with the NoExt attribute. +define noext i8 @callee_NoExtRet_i8() { + ret i8 -1 +} + +define noext i16 @callee_NoExtRet_i16() { + ret i16 -1 +} + +define noext i32 @callee_NoExtRet_i32() { + ret i32 -1 +} + +; An internal function is not checked for an extension attribute. +define internal i32 @callee_NoExtRet_internal(i32 %Arg) { + ret i32 %Arg +} + +; A call to an internal function is ok without argument extension. +define void @caller_internal() { + call i32 @callee_NoExtRet_internal(i32 0) + ret void +} Index: llvm/test/CodeGen/SystemZ/args-16.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/args-16.ll @@ -0,0 +1,14 @@ +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \ +; RUN: | FileCheck %s +; REQUIRES: asserts +; +; Test detection of missing extension of an outgoing i32 call argument. + +define void @caller() { + call void @bar_Struct(i32 123) + ret void +} + +declare void @bar_Struct(i32 %Arg) + +; CHECK: Narrow integer argument must have a valid extension type Index: llvm/test/CodeGen/SystemZ/args-17.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/args-17.ll @@ -0,0 +1,14 @@ +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \ +; RUN: | FileCheck %s +; REQUIRES: asserts +; +; Test detection of missing extension of an outgoing i16 call argument. + +define void @caller() { + call void @bar_Struct(i16 123) + ret void +} + +declare void @bar_Struct(i16 %Arg) + +; CHECK: Narrow integer argument must have a valid extension type Index: llvm/test/CodeGen/SystemZ/args-18.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/args-18.ll @@ -0,0 +1,14 @@ +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \ +; RUN: | FileCheck %s +; REQUIRES: asserts +; +; Test detection of missing extension of an outgoing i8 call argument. + +define void @caller() { + call void @bar_Struct(i8 123) + ret void +} + +declare void @bar_Struct(i8 %Arg) + +; CHECK: Narrow integer argument must have a valid extension type Index: llvm/test/CodeGen/SystemZ/args-19.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/args-19.ll @@ -0,0 +1,49 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu + +; Test that passed outgoing integer arguments are sign-extended by default if +; the extension attribute is missing. +define void @caller() { +; CHECK-LABEL: caller: +; CHECK: lghi %r2, 132 +; CHECK-NEXT: brasl %r14, bar_Struct_32@PLT +; CHECK-NEXT: lghi %r2, 116 +; CHECK-NEXT: brasl %r14, bar_Struct_16@PLT +; CHECK-NEXT: lghi %r2, 108 +; CHECK-NEXT: brasl %r14, bar_Struct_8@PLT + call void @bar_Struct_32(i32 132) + call void @bar_Struct_16(i16 116) + call void @bar_Struct_8(i8 108) + ret void +} + +; Test default sign extension of returned values. +define i32 @callee_1(i32 %Arg) { +; CHECK-LABEL: callee_1: +; CHECK: ahi %r2, 1 +; CHECK-NEXT: lgfr %r2, %r2 +; CHECK-NEXT: br %r14 + %A = add i32 %Arg, 1 + ret i32 %A +} + +define i16 @callee_2(i16 %Arg) { +; CHECK-LABEL: callee_2: +; CHECK: ahi %r2, 1 +; CHECK-NEXT: lghr %r2, %r2 +; CHECK-NEXT: br %r14 + %A = add i16 %Arg, 1 + ret i16 %A +} + +define i8 @callee_3(i8 %Arg) { +; CHECK-LABEL: callee_3: +; CHECK: ahi %r2, 1 +; CHECK-NEXT: lgbr %r2, %r2 +; CHECK-NEXT: br %r14 + %A = add i8 %Arg, 1 + ret i8 %A +} + +declare void @bar_Struct_32(i32 %Arg) +declare void @bar_Struct_16(i16 %Arg) +declare void @bar_Struct_8(i8 %Arg) Index: llvm/test/CodeGen/SystemZ/asm-11.ll =================================================================== --- llvm/test/CodeGen/SystemZ/asm-11.ll +++ llvm/test/CodeGen/SystemZ/asm-11.ll @@ -1,6 +1,7 @@ ; Test the "I" constraint (8-bit unsigned constants). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \ +; RUN: | FileCheck %s ; Test 1 below the first valid value. define i32 @f1() { Index: llvm/test/CodeGen/SystemZ/asm-12.ll =================================================================== --- llvm/test/CodeGen/SystemZ/asm-12.ll +++ llvm/test/CodeGen/SystemZ/asm-12.ll @@ -1,6 +1,7 @@ ; Test the "J" constraint (12-bit unsigned constants). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \ +; RUN: | FileCheck %s ; Test 1 below the first valid value. define i32 @f1() { Index: llvm/test/CodeGen/SystemZ/asm-13.ll =================================================================== --- llvm/test/CodeGen/SystemZ/asm-13.ll +++ llvm/test/CodeGen/SystemZ/asm-13.ll @@ -1,6 +1,7 @@ ; Test the "K" constraint (16-bit signed constants). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \ +; RUN: | FileCheck %s ; Test 1 below the first valid value. define i32 @f1() { Index: llvm/test/CodeGen/SystemZ/asm-14.ll =================================================================== --- llvm/test/CodeGen/SystemZ/asm-14.ll +++ llvm/test/CodeGen/SystemZ/asm-14.ll @@ -1,6 +1,7 @@ ; Test the "L" constraint (20-bit signed constants). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \ +; RUN: | FileCheck %s ; Test 1 below the first valid value. define i32 @f1() { Index: llvm/test/CodeGen/SystemZ/asm-15.ll =================================================================== --- llvm/test/CodeGen/SystemZ/asm-15.ll +++ llvm/test/CodeGen/SystemZ/asm-15.ll @@ -1,6 +1,7 @@ ; Test the "M" constraint (0x7fffffff) ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \ +; RUN: | FileCheck %s ; Test 1 below the valid value. define i32 @f1() { Index: llvm/test/CodeGen/SystemZ/asm-16.ll =================================================================== --- llvm/test/CodeGen/SystemZ/asm-16.ll +++ llvm/test/CodeGen/SystemZ/asm-16.ll @@ -1,6 +1,7 @@ ; Test the "M" constraint (0x7fffffff) ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \ +; RUN: | FileCheck %s ; Test 1 below the valid value. define i32 @f1() { Index: llvm/test/CodeGen/SystemZ/asm-17.ll =================================================================== --- llvm/test/CodeGen/SystemZ/asm-17.ll +++ llvm/test/CodeGen/SystemZ/asm-17.ll @@ -1,7 +1,7 @@ ; Test explicit register names. ; ; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -no-integrated-as \ -; RUN: | FileCheck %s +; RUN: -no-arg-exts | FileCheck %s ; Test i32 GPRs. define i32 @f1() { Index: llvm/test/CodeGen/SystemZ/asm-18.ll =================================================================== --- llvm/test/CodeGen/SystemZ/asm-18.ll +++ llvm/test/CodeGen/SystemZ/asm-18.ll @@ -2,7 +2,7 @@ ; register and "r" constraints to force a low register. ; ; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z196 \ -; RUN: -no-integrated-as | FileCheck %s +; RUN: -no-integrated-as -no-arg-exts | FileCheck %s ; Test loads and stores involving mixtures of high and low registers. define void @f1(i32 *%ptr1, i32 *%ptr2) { Index: llvm/test/CodeGen/SystemZ/atomic-load-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomic-load-01.ll +++ llvm/test/CodeGen/SystemZ/atomic-load-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic loads. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s define i8 @f1(i8 *%src) { ; CHECK-LABEL: f1: Index: llvm/test/CodeGen/SystemZ/atomic-load-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomic-load-02.ll +++ llvm/test/CodeGen/SystemZ/atomic-load-02.ll @@ -1,6 +1,6 @@ ; Test 16-bit atomic loads. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s define i16 @f1(i16 *%src) { ; CHECK-LABEL: f1: Index: llvm/test/CodeGen/SystemZ/atomic-load-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomic-load-03.ll +++ llvm/test/CodeGen/SystemZ/atomic-load-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic loads. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s define i32 @f1(i32 *%src) { ; CHECK-LABEL: f1: Index: llvm/test/CodeGen/SystemZ/atomicrmw-add-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-add-01.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-add-01.ll @@ -1,8 +1,10 @@ ; Test 8-bit atomic additions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check addition of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-add-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-add-02.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-add-02.ll @@ -1,8 +1,10 @@ ; Test 16-bit atomic additions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check addition of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic additions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Check addition of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-add-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-add-05.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-add-05.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic additions, z196 version. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check addition of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-and-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-and-01.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-and-01.ll @@ -1,8 +1,10 @@ ; Test 8-bit atomic ANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check AND of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-and-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-and-02.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-and-02.ll @@ -1,8 +1,10 @@ ; Test 16-bit atomic ANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check AND of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic ANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Check ANDs of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-and-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-and-05.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-and-05.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic ANDs, z196 version. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check AND of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll @@ -1,8 +1,11 @@ ; Test 8-bit atomic min/max operations. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \ +; RUN: | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check signed minimum. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll @@ -1,8 +1,11 @@ ; Test 8-bit atomic min/max operations. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \ +; RUN: | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check signed minimum. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll @@ -1,7 +1,7 @@ ; Test 32-bit atomic minimum and maximum. Here we match the z10 versions, ; which can't use LOCR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Check signed minium. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-nand-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-nand-01.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-nand-01.ll @@ -1,8 +1,10 @@ ; Test 8-bit atomic NANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check NAND of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-nand-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-nand-02.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-nand-02.ll @@ -1,8 +1,10 @@ ; Test 16-bit atomic NANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check NAND of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic NANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Check NANDs of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-or-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-or-01.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-or-01.ll @@ -1,8 +1,10 @@ ; Test 8-bit atomic ORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check OR of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-or-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-or-02.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-or-02.ll @@ -1,8 +1,10 @@ ; Test 16-bit atomic ORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check OR of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic ORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Check ORs of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-or-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-or-05.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-or-05.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic ORs, z196 version. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check OR of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-sub-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-sub-01.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-sub-01.ll @@ -1,8 +1,10 @@ ; Test 8-bit atomic subtractions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check subtraction of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-sub-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-sub-02.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-sub-02.ll @@ -1,8 +1,10 @@ ; Test 16-bit atomic subtractions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check subtraction of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic subtractions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Check subtraction of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-sub-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-sub-05.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-sub-05.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic subtractions, z196 version. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check addition of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll @@ -1,7 +1,8 @@ ; Test 8-bit atomic exchange. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s \ +; RUN: -check-prefix=CHECK-SHIFT ; Check exchange with a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll @@ -1,7 +1,8 @@ ; Test 16-bit atomic exchange. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s \ +; RUN: -check-prefix=CHECK-SHIFT ; Check exchange with a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic exchange. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check register exchange. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-xor-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-xor-01.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-xor-01.ll @@ -1,8 +1,10 @@ ; Test 8-bit atomic XORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check XOR of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-xor-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-xor-02.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-xor-02.ll @@ -1,8 +1,10 @@ ; Test 16-bit atomic XORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2 ; Check XOR of a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic XORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Check XORs of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/atomicrmw-xor-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/atomicrmw-xor-05.ll +++ llvm/test/CodeGen/SystemZ/atomicrmw-xor-05.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic ORs, z196 version. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check OR of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { Index: llvm/test/CodeGen/SystemZ/branch-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/branch-05.ll +++ llvm/test/CodeGen/SystemZ/branch-05.ll @@ -1,6 +1,6 @@ ; Test indirect jumps. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s define i32 @f1(i32 %x, i32 %y, i32 %op) { ; CHECK-LABEL: f1: Index: llvm/test/CodeGen/SystemZ/branch-11.ll =================================================================== --- llvm/test/CodeGen/SystemZ/branch-11.ll +++ llvm/test/CodeGen/SystemZ/branch-11.ll @@ -1,6 +1,6 @@ ; Test indirect jumps on z14. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s define i32 @f1(i32 %x, i32 %y, i32 %op) { ; CHECK-LABEL: f1: Index: llvm/test/CodeGen/SystemZ/bswap-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/bswap-02.ll +++ llvm/test/CodeGen/SystemZ/bswap-02.ll @@ -1,6 +1,6 @@ ; Test 32-bit byteswaps from memory to registers. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare i32 @llvm.bswap.i32(i32 %a) Index: llvm/test/CodeGen/SystemZ/bswap-06.ll =================================================================== --- llvm/test/CodeGen/SystemZ/bswap-06.ll +++ llvm/test/CodeGen/SystemZ/bswap-06.ll @@ -1,6 +1,6 @@ ; Test 16-bit byteswaps from memory to registers. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare i16 @llvm.bswap.i16(i16 %a) Index: llvm/test/CodeGen/SystemZ/call-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/call-03.ll +++ llvm/test/CodeGen/SystemZ/call-03.ll @@ -1,6 +1,6 @@ ; Test sibling calls. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare void @ok(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, float %f4, double %f6) Index: llvm/test/CodeGen/SystemZ/cmpxchg-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/cmpxchg-01.ll +++ llvm/test/CodeGen/SystemZ/cmpxchg-01.ll @@ -1,7 +1,9 @@ ; Test 8-bit compare and swap. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-MAIN +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT ; Check compare and swap with a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/cmpxchg-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/cmpxchg-02.ll +++ llvm/test/CodeGen/SystemZ/cmpxchg-02.ll @@ -1,7 +1,9 @@ ; Test 16-bit compare and swap. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-MAIN +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \ +; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT ; Check compare and swap with a variable. ; - CHECK is for the main loop. Index: llvm/test/CodeGen/SystemZ/cmpxchg-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/cmpxchg-03.ll +++ llvm/test/CodeGen/SystemZ/cmpxchg-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit compare and swap. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check the low end of the CS range. define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) { Index: llvm/test/CodeGen/SystemZ/cmpxchg-04.ll =================================================================== --- llvm/test/CodeGen/SystemZ/cmpxchg-04.ll +++ llvm/test/CodeGen/SystemZ/cmpxchg-04.ll @@ -1,6 +1,6 @@ ; Test 64-bit compare and swap. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check CSG without a displacement. define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) { Index: llvm/test/CodeGen/SystemZ/cmpxchg-06.ll =================================================================== --- llvm/test/CodeGen/SystemZ/cmpxchg-06.ll +++ llvm/test/CodeGen/SystemZ/cmpxchg-06.ll @@ -1,6 +1,6 @@ ; Test 64-bit compare and swap. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check CDSG without a displacement. define i128 @f1(i128 %cmp, i128 %swap, i128 *%src) { Index: llvm/test/CodeGen/SystemZ/codegenprepare-form-OF-ops.ll =================================================================== --- llvm/test/CodeGen/SystemZ/codegenprepare-form-OF-ops.ll +++ llvm/test/CodeGen/SystemZ/codegenprepare-form-OF-ops.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 -no-arg-exts \ +; RUN: | FileCheck %s ; ; Check that CodeGenPrepare transforms these functions to use ; uadd.with.overflow / usub.with.overflow intrinsics so that the compare Index: llvm/test/CodeGen/SystemZ/cond-move-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/cond-move-02.ll +++ llvm/test/CodeGen/SystemZ/cond-move-02.ll @@ -1,10 +1,12 @@ ; Test LOCHI and LOCGHI. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs \ +; RUN: -no-arg-exts | FileCheck %s ; ; Run the test again to make sure it still works the same even ; in the presence of the select instructions. -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs \ +; RUN: -no-arg-exts | FileCheck %s define i32 @f1(i32 %x) { Index: llvm/test/CodeGen/SystemZ/cond-move-06.ll =================================================================== --- llvm/test/CodeGen/SystemZ/cond-move-06.ll +++ llvm/test/CodeGen/SystemZ/cond-move-06.ll @@ -1,6 +1,7 @@ ; Test SELR and SELGR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs \ +; RUN: -no-arg-exts | FileCheck %s ; Test SELR. define i32 @f1(i32 %limit, i32 %a, i32 %b) { Index: llvm/test/CodeGen/SystemZ/ctpop-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/ctpop-01.ll +++ llvm/test/CodeGen/SystemZ/ctpop-01.ll @@ -1,6 +1,6 @@ ; Test population-count instruction ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s declare i32 @llvm.ctpop.i32(i32 %a) declare i64 @llvm.ctpop.i64(i64 %a) Index: llvm/test/CodeGen/SystemZ/fp-conv-09.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-conv-09.ll +++ llvm/test/CodeGen/SystemZ/fp-conv-09.ll @@ -1,6 +1,6 @@ ; Test conversion of floating-point values to signed i32s. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test f32->i32. define i32 @f1(float %f) { Index: llvm/test/CodeGen/SystemZ/fp-conv-10.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-conv-10.ll +++ llvm/test/CodeGen/SystemZ/fp-conv-10.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test conversion of floating-point values to unsigned i32s (z10 only). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; z10 doesn't have native support for unsigned fp-to-i32 conversions; ; they were added in z196 as the Convert to Logical family of instructions. Index: llvm/test/CodeGen/SystemZ/fp-conv-14.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-conv-14.ll +++ llvm/test/CodeGen/SystemZ/fp-conv-14.ll @@ -1,6 +1,6 @@ ; Test conversion of floating-point values to unsigned integers. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Test f32->i32. define i32 @f1(float %f) { Index: llvm/test/CodeGen/SystemZ/fp-conv-16.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-conv-16.ll +++ llvm/test/CodeGen/SystemZ/fp-conv-16.ll @@ -1,6 +1,6 @@ ; Test f128 floating-point conversion to/from integers on z14. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s ; Test signed i32->f128. define void @f1(i32 %i, fp128 *%dst) { Index: llvm/test/CodeGen/SystemZ/fp-move-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-move-02.ll +++ llvm/test/CodeGen/SystemZ/fp-move-02.ll @@ -1,7 +1,7 @@ ; Test moves between FPRs and GPRs. The 32-bit cases test the z10 ; implementation, which has no high-word support. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s declare i64 @foo() declare double @bar() Index: llvm/test/CodeGen/SystemZ/fp-strict-conv-09.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-strict-conv-09.ll +++ llvm/test/CodeGen/SystemZ/fp-strict-conv-09.ll @@ -1,6 +1,6 @@ ; Test strict conversion of floating-point values to signed i32s. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata) declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata) Index: llvm/test/CodeGen/SystemZ/fp-strict-conv-10.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-strict-conv-10.ll +++ llvm/test/CodeGen/SystemZ/fp-strict-conv-10.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test strict conversion of floating-point values to unsigned i32s (z10 only). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; z10 doesn't have native support for unsigned fp-to-i32 conversions; ; they were added in z196 as the Convert to Logical family of instructions. Index: llvm/test/CodeGen/SystemZ/fp-strict-conv-14.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-strict-conv-14.ll +++ llvm/test/CodeGen/SystemZ/fp-strict-conv-14.ll @@ -1,6 +1,6 @@ ; Test strict conversion of floating-point values to unsigned integers. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata) declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata) Index: llvm/test/CodeGen/SystemZ/fp-strict-conv-16.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fp-strict-conv-16.ll +++ llvm/test/CodeGen/SystemZ/fp-strict-conv-16.ll @@ -1,6 +1,6 @@ ; Test f128 floating-point strict conversion to/from integers on z14. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s declare fp128 @llvm.experimental.constrained.sitofp.f128.i32(i32, metadata, metadata) declare fp128 @llvm.experimental.constrained.sitofp.f128.i64(i64, metadata, metadata) Index: llvm/test/CodeGen/SystemZ/fpc-intrinsics.ll =================================================================== --- llvm/test/CodeGen/SystemZ/fpc-intrinsics.ll +++ llvm/test/CodeGen/SystemZ/fpc-intrinsics.ll @@ -1,6 +1,6 @@ ; Test floating-point control register intrinsics. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare void @llvm.s390.sfpc(i32) declare i32 @llvm.s390.efpc() Index: llvm/test/CodeGen/SystemZ/htm-intrinsics.ll =================================================================== --- llvm/test/CodeGen/SystemZ/htm-intrinsics.ll +++ llvm/test/CodeGen/SystemZ/htm-intrinsics.ll @@ -1,6 +1,6 @@ ; Test transactional-execution intrinsics. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -no-arg-exts | FileCheck %s declare i32 @llvm.s390.tbegin(i8 *, i32) declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32) Index: llvm/test/CodeGen/SystemZ/inline-asm-i128.ll =================================================================== --- llvm/test/CodeGen/SystemZ/inline-asm-i128.ll +++ llvm/test/CodeGen/SystemZ/inline-asm-i128.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=s390x-linux-gnu -no-integrated-as < %s | FileCheck %s +; RUN: llc -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts < %s \ +; RUN: | FileCheck %s ; ; Test i128 (tied) operands. Index: llvm/test/CodeGen/SystemZ/insert-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/insert-01.ll +++ llvm/test/CodeGen/SystemZ/insert-01.ll @@ -1,6 +1,6 @@ ; Test insertions of memory into the low byte of an i32. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check a plain insertion with (or (and ... -0xff) (zext (load ....))). ; The whole sequence can be performed by IC. Index: llvm/test/CodeGen/SystemZ/int-abs-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-abs-01.ll +++ llvm/test/CodeGen/SystemZ/int-abs-01.ll @@ -1,6 +1,6 @@ ; Test integer absolute. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test i32->i32 absolute using slt. define i32 @f1(i32 %val) { Index: llvm/test/CodeGen/SystemZ/int-add-13.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-add-13.ll +++ llvm/test/CodeGen/SystemZ/int-add-13.ll @@ -1,6 +1,6 @@ ; Test the three-operand forms of addition. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check ARK. define i32 @f1(i32 %a, i32 %b, i32 %c) { Index: llvm/test/CodeGen/SystemZ/int-add-14.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-add-14.ll +++ llvm/test/CodeGen/SystemZ/int-add-14.ll @@ -1,7 +1,7 @@ ; Test 32-bit addition in which the second operand is constant and in which ; three-operand forms are available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check additions of 1. define i32 @f1(i32 %a, i32 %b) { Index: llvm/test/CodeGen/SystemZ/int-cmp-36.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-cmp-36.ll +++ llvm/test/CodeGen/SystemZ/int-cmp-36.ll @@ -1,7 +1,7 @@ ; Test 32-bit comparisons in which the second operand is sign-extended ; from a PC-relative i16. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s @g = dso_local global i16 1 @h = dso_local global i16 1, align 1, section "foo" Index: llvm/test/CodeGen/SystemZ/int-cmp-38.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-cmp-38.ll +++ llvm/test/CodeGen/SystemZ/int-cmp-38.ll @@ -1,7 +1,7 @@ ; Test 32-bit comparisons in which the second operand is a PC-relative ; variable. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s @g = dso_local global i32 1 @h = dso_local global i32 1, align 2, section "foo" Index: llvm/test/CodeGen/SystemZ/int-cmp-44.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-cmp-44.ll +++ llvm/test/CodeGen/SystemZ/int-cmp-44.ll @@ -2,7 +2,7 @@ ; (z10 version). ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-integrated-as \ -; RUN: -verify-machineinstrs| FileCheck %s +; RUN: -verify-machineinstrs -no-arg-exts | FileCheck %s declare void @foo() Index: llvm/test/CodeGen/SystemZ/int-cmp-45.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-cmp-45.ll +++ llvm/test/CodeGen/SystemZ/int-cmp-45.ll @@ -1,7 +1,8 @@ ; Test that compares are omitted if CC already has the right value ; (z196 version). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-integrated-as | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-integrated-as \ +; RUN: -no-arg-exts | FileCheck %s ; Addition provides enough for comparisons with zero if we know no ; signed overflow happens, which is when the "nsw" flag is set. Index: llvm/test/CodeGen/SystemZ/int-cmp-57.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-cmp-57.ll +++ llvm/test/CodeGen/SystemZ/int-cmp-57.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -disable-cgp | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -disable-cgp -no-arg-exts \ +; RUN: | FileCheck %s ; ; Check that signed comparisons against 0 are eliminated if the defining ; instruction is an add with immediate. Index: llvm/test/CodeGen/SystemZ/int-cmp-61.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-cmp-61.ll +++ llvm/test/CodeGen/SystemZ/int-cmp-61.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s ; ; Test using bitwise logic on icmp operands instead of i1 logic when ; possible. Index: llvm/test/CodeGen/SystemZ/int-const-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-const-01.ll +++ llvm/test/CodeGen/SystemZ/int-const-01.ll @@ -1,6 +1,6 @@ ; Test loading of 32-bit constants. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare void @foo(i32, i32, i32, i32) Index: llvm/test/CodeGen/SystemZ/int-conv-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-conv-01.ll +++ llvm/test/CodeGen/SystemZ/int-conv-01.ll @@ -1,6 +1,6 @@ ; Test sign extensions from a byte to an i32. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test register extension, starting with an i32. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/int-conv-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-conv-02.ll +++ llvm/test/CodeGen/SystemZ/int-conv-02.ll @@ -1,7 +1,7 @@ ; Test zero extensions from a byte to an i32. The tests here ; assume z10 register pressure, without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Test register extension, starting with an i32. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/int-conv-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-conv-05.ll +++ llvm/test/CodeGen/SystemZ/int-conv-05.ll @@ -1,6 +1,6 @@ ; Test sign extensions from a halfword to an i32. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test register extension, starting with an i32. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/int-conv-06.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-conv-06.ll +++ llvm/test/CodeGen/SystemZ/int-conv-06.ll @@ -1,7 +1,7 @@ ; Test zero extensions from a halfword to an i32. The tests here ; assume z10 register pressure, without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Test register extension, starting with an i32. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/int-conv-13.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-conv-13.ll +++ llvm/test/CodeGen/SystemZ/int-conv-13.ll @@ -1,6 +1,6 @@ ; Test load and zero rightmost byte. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s ; Check LZRF with no displacement. define i32 @f1(i32 *%src) { Index: llvm/test/CodeGen/SystemZ/int-div-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-div-01.ll +++ llvm/test/CodeGen/SystemZ/int-div-01.ll @@ -1,6 +1,7 @@ ; Test 32-bit signed division and remainder. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 -no-arg-exts \ +; RUN: | FileCheck %s declare i32 @foo() Index: llvm/test/CodeGen/SystemZ/int-div-06.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-div-06.ll +++ llvm/test/CodeGen/SystemZ/int-div-06.ll @@ -1,6 +1,7 @@ ; Test that divisions by constants are implemented as multiplications. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 -no-arg-exts \ +; RUN: | FileCheck %s ; Check signed 32-bit division. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/int-move-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-move-01.ll +++ llvm/test/CodeGen/SystemZ/int-move-01.ll @@ -1,6 +1,6 @@ ; Test moves between GPRs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test 8-bit moves, which should get promoted to i32. define i8 @f1(i8 %a, i8 %b) { Index: llvm/test/CodeGen/SystemZ/int-move-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-move-02.ll +++ llvm/test/CodeGen/SystemZ/int-move-02.ll @@ -1,6 +1,6 @@ ; Test 32-bit GPR loads. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check the low end of the L range. define i32 @f1(i32 *%src) { Index: llvm/test/CodeGen/SystemZ/int-move-08.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-move-08.ll +++ llvm/test/CodeGen/SystemZ/int-move-08.ll @@ -1,6 +1,6 @@ ; Test 32-bit GPR accesses to a PC-relative location. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s @gsrc16 = dso_local global i16 1 @gsrc32 = dso_local global i32 1 Index: llvm/test/CodeGen/SystemZ/int-move-10.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-move-10.ll +++ llvm/test/CodeGen/SystemZ/int-move-10.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; ; Test PC-relative memory accesses of globals with packed struct types. ; PC-relative memory accesses cannot be used when the address is not Index: llvm/test/CodeGen/SystemZ/int-mul-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-mul-05.ll +++ llvm/test/CodeGen/SystemZ/int-mul-05.ll @@ -1,6 +1,6 @@ ; Test 32-bit multiplication in which the second operand is constant. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check multiplication by 2, which should use shifts. define i32 @f1(i32 %a, i32 *%dest) { Index: llvm/test/CodeGen/SystemZ/int-mul-11.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-mul-11.ll +++ llvm/test/CodeGen/SystemZ/int-mul-11.ll @@ -1,6 +1,6 @@ ; Test three-operand multiplication instructions on z14. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s ; Check MSRKC. define i32 @f1(i32 %dummy, i32 %a, i32 %b) { Index: llvm/test/CodeGen/SystemZ/int-neg-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-neg-01.ll +++ llvm/test/CodeGen/SystemZ/int-neg-01.ll @@ -1,6 +1,6 @@ ; Test integer negation. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test i32->i32 negation. define i32 @f1(i32 %val) { Index: llvm/test/CodeGen/SystemZ/int-neg-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-neg-02.ll +++ llvm/test/CodeGen/SystemZ/int-neg-02.ll @@ -1,6 +1,6 @@ ; Test negative integer absolute. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test i32->i32 negative absolute using slt. define i32 @f1(i32 %val) { Index: llvm/test/CodeGen/SystemZ/int-sub-08.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-sub-08.ll +++ llvm/test/CodeGen/SystemZ/int-sub-08.ll @@ -1,6 +1,6 @@ ; Test the three-operand forms of subtraction. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check SRK. define i32 @f1(i32 %a, i32 %b, i32 %c) { Index: llvm/test/CodeGen/SystemZ/int-uadd-06.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-uadd-06.ll +++ llvm/test/CodeGen/SystemZ/int-uadd-06.ll @@ -1,6 +1,6 @@ ; Test the three-operand form of 32-bit addition. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s declare i32 @foo(i32, i32, i32) Index: llvm/test/CodeGen/SystemZ/int-usub-06.ll =================================================================== --- llvm/test/CodeGen/SystemZ/int-usub-06.ll +++ llvm/test/CodeGen/SystemZ/int-usub-06.ll @@ -1,6 +1,6 @@ ; Test the three-operand form of 32-bit subtraction. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s declare i32 @foo(i32, i32, i32) Index: llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll =================================================================== --- llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll +++ llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll @@ -1,7 +1,7 @@ ; Test that DAGCombiner gets helped by computeKnownBitsForTargetNode() with ; vector intrinsics. ; -; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s +; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts < %s | FileCheck %s declare {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16>, <8 x i16>) declare {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32>, <4 x i32>) Index: llvm/test/CodeGen/SystemZ/knownbits.ll =================================================================== --- llvm/test/CodeGen/SystemZ/knownbits.ll +++ llvm/test/CodeGen/SystemZ/knownbits.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s +; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts < %s | FileCheck %s ; Test that DAGCombiner gets helped by computeKnownBitsForTargetNode(). Index: llvm/test/CodeGen/SystemZ/memcmp-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/memcmp-01.ll +++ llvm/test/CodeGen/SystemZ/memcmp-01.ll @@ -1,6 +1,6 @@ ; Test memcmp using CLC, with i32 results. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare signext i32 @memcmp(i8 *%src1, i8 *%src2, i64 %size) Index: llvm/test/CodeGen/SystemZ/not-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/not-01.ll +++ llvm/test/CodeGen/SystemZ/not-01.ll @@ -1,6 +1,6 @@ ; Combined logical operations involving complement on z15 ; -; RUN: llc -mcpu=z15 < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc -mcpu=z15 < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; And-with-complement 32-bit. define i32 @f1(i32 %dummy, i32 %a, i32 %b) { Index: llvm/test/CodeGen/SystemZ/or-07.ll =================================================================== --- llvm/test/CodeGen/SystemZ/or-07.ll +++ llvm/test/CodeGen/SystemZ/or-07.ll @@ -1,6 +1,6 @@ ; Test the three-operand forms of OR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check XRK. define i32 @f1(i32 %a, i32 %b, i32 %c) { Index: llvm/test/CodeGen/SystemZ/pr42512.ll =================================================================== --- llvm/test/CodeGen/SystemZ/pr42512.ll +++ llvm/test/CodeGen/SystemZ/pr42512.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s define i8 @test(i8 %x) { ; CHECK-LABEL: test: Index: llvm/test/CodeGen/SystemZ/risbg-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/risbg-01.ll +++ llvm/test/CodeGen/SystemZ/risbg-01.ll @@ -2,7 +2,7 @@ ; Test sequences that can use RISBG with a zeroed first operand. ; The tests here assume that RISBLG isn't available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Test an extraction of bit 0 from a right-shifted value. define i32 @f1(i32 %foo) { Index: llvm/test/CodeGen/SystemZ/risbg-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/risbg-02.ll +++ llvm/test/CodeGen/SystemZ/risbg-02.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test sequences that can use RISBG with a normal first operand. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test a case with two ANDs. define i32 @f1(i32 %a, i32 %b) { Index: llvm/test/CodeGen/SystemZ/risbg-04.ll =================================================================== --- llvm/test/CodeGen/SystemZ/risbg-04.ll +++ llvm/test/CodeGen/SystemZ/risbg-04.ll @@ -2,7 +2,7 @@ ; Test sequences that can use RISBG with a zeroed first operand. ; The tests here assume that RISBLG is available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Test an extraction of bit 0 from a right-shifted value. define i32 @f1(i32 %foo) { Index: llvm/test/CodeGen/SystemZ/rot-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/rot-01.ll +++ llvm/test/CodeGen/SystemZ/rot-01.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test shortening of NILL to NILF when the result is used as a rotate amount. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test 32-bit rotate. define i32 @f1(i32 %val, i32 %amt) { Index: llvm/test/CodeGen/SystemZ/rot-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/rot-02.ll +++ llvm/test/CodeGen/SystemZ/rot-02.ll @@ -2,7 +2,7 @@ ; Test removal of AND operations that don't affect last 6 bits of rotate amount ; operand. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test that AND is not removed when some lower 5 bits are not set. define i32 @f1(i32 %val, i32 %amt) { Index: llvm/test/CodeGen/SystemZ/scalar-ctlz.ll =================================================================== --- llvm/test/CodeGen/SystemZ/scalar-ctlz.ll +++ llvm/test/CodeGen/SystemZ/scalar-ctlz.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s ; ; FIXME: two consecutive immediate adds not fused in i16/i8 functions. Index: llvm/test/CodeGen/SystemZ/selectcc-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/selectcc-01.ll +++ llvm/test/CodeGen/SystemZ/selectcc-01.ll @@ -1,6 +1,6 @@ ; Test an i32 0/-1 SELECTCCC for every floating-point condition. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test CC in { 0 } define i32 @f1(float %a, float %b) { Index: llvm/test/CodeGen/SystemZ/selectcc-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/selectcc-02.ll +++ llvm/test/CodeGen/SystemZ/selectcc-02.ll @@ -1,6 +1,6 @@ ; Test an i32 0/-1 SELECTCCC for every floating-point condition. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test CC in { 1, 2, 3 } define i32 @f1(float %a, float %b) { Index: llvm/test/CodeGen/SystemZ/setcc-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/setcc-01.ll +++ llvm/test/CodeGen/SystemZ/setcc-01.ll @@ -1,7 +1,7 @@ ; Test SETCC for every integer condition. The tests here assume that ; RISBLG isn't available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Test CC in { 0 }, with 3 don't care. define i32 @f1(i32 %a, i32 %b) { Index: llvm/test/CodeGen/SystemZ/setcc-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/setcc-02.ll +++ llvm/test/CodeGen/SystemZ/setcc-02.ll @@ -1,7 +1,7 @@ ; Test SETCC for every floating-point condition. The tests here assume that ; RISBLG isn't available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s ; Test CC in { 0 } define i32 @f1(float %a, float %b) { Index: llvm/test/CodeGen/SystemZ/sext-zext.ll =================================================================== --- llvm/test/CodeGen/SystemZ/sext-zext.ll +++ llvm/test/CodeGen/SystemZ/sext-zext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ;; fold (sext (not x)) -> (add (zext x) -1) define i32 @sext_of_not(i1 %x) { Index: llvm/test/CodeGen/SystemZ/shift-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/shift-01.ll +++ llvm/test/CodeGen/SystemZ/shift-01.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test 32-bit shifts left. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check the low end of the SLL range. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/shift-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/shift-02.ll +++ llvm/test/CodeGen/SystemZ/shift-02.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test 32-bit logical shifts right. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check the low end of the SRL range. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/shift-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/shift-03.ll +++ llvm/test/CodeGen/SystemZ/shift-03.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test 32-bit arithmetic shifts right. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check the low end of the SRA range. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/shift-04.ll =================================================================== --- llvm/test/CodeGen/SystemZ/shift-04.ll +++ llvm/test/CodeGen/SystemZ/shift-04.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test 32-bit rotates left. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check the low end of the RLL range. define i32 @f1(i32 %a) { Index: llvm/test/CodeGen/SystemZ/shift-09.ll =================================================================== --- llvm/test/CodeGen/SystemZ/shift-09.ll +++ llvm/test/CodeGen/SystemZ/shift-09.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test three-operand shifts. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check that we use SLLK over SLL where useful. define i32 @f1(i32 %a, i32 %b, i32 %amt) { Index: llvm/test/CodeGen/SystemZ/shift-11.ll =================================================================== --- llvm/test/CodeGen/SystemZ/shift-11.ll +++ llvm/test/CodeGen/SystemZ/shift-11.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Test shortening of NILL to NILF when the result is used as a shift amount. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Test logical shift right. define i32 @f1(i32 %a, i32 %sh) { Index: llvm/test/CodeGen/SystemZ/shift-12.ll =================================================================== --- llvm/test/CodeGen/SystemZ/shift-12.ll +++ llvm/test/CodeGen/SystemZ/shift-12.ll @@ -2,7 +2,7 @@ ; Test removal of AND operations that don't affect last 6 bits of shift amount ; operand. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s ; Test that AND is not removed when some lower 6 bits are not set. define i32 @f1(i32 %a, i32 %sh) { Index: llvm/test/CodeGen/SystemZ/soft-float-args.ll =================================================================== --- llvm/test/CodeGen/SystemZ/soft-float-args.ll +++ llvm/test/CodeGen/SystemZ/soft-float-args.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -mattr=soft-float -O3 < %s | FileCheck %s +; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -mattr=soft-float -O3 \ +; RUN: -no-arg-exts < %s | FileCheck %s ; ; Test that arguments and return values of fp/vector types are always handled ; with gprs with soft-float. Index: llvm/test/CodeGen/SystemZ/stack-clash-dynamic-alloca.ll =================================================================== --- llvm/test/CodeGen/SystemZ/stack-clash-dynamic-alloca.ll +++ llvm/test/CodeGen/SystemZ/stack-clash-dynamic-alloca.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -verify-machineinstrs \ +; RUN: -no-arg-exts | FileCheck %s define i32 @fun0(i32 %n) #0 { ; CHECK-LABEL: fun0: Index: llvm/test/CodeGen/SystemZ/stack-clash-protection.ll =================================================================== --- llvm/test/CodeGen/SystemZ/stack-clash-protection.ll +++ llvm/test/CodeGen/SystemZ/stack-clash-protection.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 -verify-machineinstrs \ +; RUN: -no-arg-exts | FileCheck %s ; ; Test stack clash protection probing for static allocas. Index: llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll =================================================================== --- llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll +++ llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s +; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts < %s | FileCheck %s ; Store a <4 x i31> vector. define void @fun0(<4 x i31> %src, <4 x i31>* %p) Index: llvm/test/CodeGen/SystemZ/strcmp-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/strcmp-01.ll +++ llvm/test/CodeGen/SystemZ/strcmp-01.ll @@ -1,6 +1,6 @@ ; Test strcmp using CLST, i32 version. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare signext i32 @strcmp(i8 *%src1, i8 *%src2) Index: llvm/test/CodeGen/SystemZ/strcpy-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/strcpy-01.ll +++ llvm/test/CodeGen/SystemZ/strcpy-01.ll @@ -1,6 +1,6 @@ ; Test strcpy using MVST. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare i8 *@strcpy(i8 *%dest, i8 *%src) declare i8 *@stpcpy(i8 *%dest, i8 *%src) Index: llvm/test/CodeGen/SystemZ/strcpy-nobuiltin.ll =================================================================== --- llvm/test/CodeGen/SystemZ/strcpy-nobuiltin.ll +++ llvm/test/CodeGen/SystemZ/strcpy-nobuiltin.ll @@ -1,7 +1,7 @@ ; Test that strcmp won't be converted to MVST if calls are ; marked with nobuiltin, eg. for sanitizers. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare i8 *@strcpy(i8 *%dest, i8 *%src) declare i8 *@stpcpy(i8 *%dest, i8 *%src) Index: llvm/test/CodeGen/SystemZ/swift-return.ll =================================================================== --- llvm/test/CodeGen/SystemZ/swift-return.ll +++ llvm/test/CodeGen/SystemZ/swift-return.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs | FileCheck --check-prefix=CHECK-O0 %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs -no-arg-exts \ +; RUN: | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs -no-arg-exts \ +; RUN: | FileCheck --check-prefix=CHECK-O0 %s @var = global i32 0 Index: llvm/test/CodeGen/SystemZ/swifterror.ll =================================================================== --- llvm/test/CodeGen/SystemZ/swifterror.ll +++ llvm/test/CodeGen/SystemZ/swifterror.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -; RUN: llc < %s -O0 -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck --check-prefix=CHECK-O0 %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \ +; RUN: | FileCheck %s +; RUN: llc < %s -O0 -mtriple=s390x-linux-gnu -disable-block-placement \ +; RUN: -no-arg-exts | FileCheck --check-prefix=CHECK-O0 %s declare i8* @malloc(i64) declare void @free(i8*) Index: llvm/test/CodeGen/SystemZ/tdc-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/tdc-01.ll +++ llvm/test/CodeGen/SystemZ/tdc-01.ll @@ -1,6 +1,6 @@ ; Test the Test Data Class instruction, selected manually via the intrinsic. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare i32 @llvm.s390.tdc.f32(float, i64) declare i32 @llvm.s390.tdc.f64(double, i64) Index: llvm/test/CodeGen/SystemZ/tdc-06.ll =================================================================== --- llvm/test/CodeGen/SystemZ/tdc-06.ll +++ llvm/test/CodeGen/SystemZ/tdc-06.ll @@ -1,6 +1,6 @@ ; Test the Test Data Class instruction, as used by fpclassify. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; declare float @llvm.fabs.f32(float) Index: llvm/test/CodeGen/SystemZ/tdc-07.ll =================================================================== --- llvm/test/CodeGen/SystemZ/tdc-07.ll +++ llvm/test/CodeGen/SystemZ/tdc-07.ll @@ -1,6 +1,6 @@ ; Test the Test Data Class instruction on z14 ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s declare i32 @llvm.s390.tdc.f128(fp128, i64) Index: llvm/test/CodeGen/SystemZ/trap-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/trap-01.ll +++ llvm/test/CodeGen/SystemZ/trap-01.ll @@ -1,6 +1,6 @@ ; Test traps and conditional traps ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s declare void @llvm.trap() Index: llvm/test/CodeGen/SystemZ/trap-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/trap-02.ll +++ llvm/test/CodeGen/SystemZ/trap-02.ll @@ -1,6 +1,6 @@ ; Test zE12 conditional traps ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -no-arg-exts | FileCheck %s declare void @llvm.trap() Index: llvm/test/CodeGen/SystemZ/trap-03.ll =================================================================== --- llvm/test/CodeGen/SystemZ/trap-03.ll +++ llvm/test/CodeGen/SystemZ/trap-03.ll @@ -1,6 +1,6 @@ ; Test load-and-trap instructions (LAT/LGAT) ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -no-arg-exts | FileCheck %s declare void @llvm.trap() Index: llvm/test/CodeGen/SystemZ/unaligned-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/unaligned-01.ll +++ llvm/test/CodeGen/SystemZ/unaligned-01.ll @@ -1,7 +1,7 @@ ; Check that unaligned accesses are allowed in general. We check the ; few exceptions (like CRL) in their respective test files. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s ; Check that these four byte stores become a single word store. define void @f1(i8 *%ptr) { Index: llvm/test/CodeGen/SystemZ/vec-combine-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/vec-combine-02.ll +++ llvm/test/CodeGen/SystemZ/vec-combine-02.ll @@ -1,6 +1,6 @@ ; Test various representations of pack-like operations. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s ; One way of writing a <4 x i32> -> <8 x i16> pack. define <8 x i16> @f1(<4 x i32> %val0, <4 x i32> %val1) { Index: llvm/test/CodeGen/SystemZ/vec-extract-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/vec-extract-02.ll +++ llvm/test/CodeGen/SystemZ/vec-extract-02.ll @@ -1,6 +1,6 @@ ; Verify ReplaceExtractVectorEltOfLoadWithNarrowedLoad fixes ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s ; Test a case where a vector extraction can be simplified to a scalar load. ; The index must be extended from i32 to i64. Index: llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll +++ llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll @@ -1,6 +1,6 @@ ; Test vector intrinsics. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s declare i32 @llvm.s390.lcbb(i8 *, i32) declare <16 x i8> @llvm.s390.vlbb(i8 *, i32) Index: llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll =================================================================== --- llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll +++ llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll @@ -1,6 +1,6 @@ ; Test vector intrinsics added with z14. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s declare <2 x i64> @llvm.s390.vbperm(<16 x i8>, <16 x i8>) declare <16 x i8> @llvm.s390.vmslg(<2 x i64>, <2 x i64>, <16 x i8>, i32) Index: llvm/test/CodeGen/SystemZ/vec-move-05.ll =================================================================== --- llvm/test/CodeGen/SystemZ/vec-move-05.ll +++ llvm/test/CodeGen/SystemZ/vec-move-05.ll @@ -1,6 +1,6 @@ ; Test vector extraction. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s ; Test v16i8 extraction of the first element. define i8 @f1(<16 x i8> %val) { Index: llvm/test/CodeGen/SystemZ/xor-07.ll =================================================================== --- llvm/test/CodeGen/SystemZ/xor-07.ll +++ llvm/test/CodeGen/SystemZ/xor-07.ll @@ -1,6 +1,6 @@ ; Test the three-operand forms of XOR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s ; Check XRK. define i32 @f1(i32 %a, i32 %b, i32 %c) { Index: llvm/test/DebugInfo/Generic/missing-abstract-variable.ll =================================================================== --- llvm/test/DebugInfo/Generic/missing-abstract-variable.ll +++ llvm/test/DebugInfo/Generic/missing-abstract-variable.ll @@ -4,7 +4,9 @@ ; powerpc64 (and on x86_64 at at least -O2). Presumably this is a SelectionDAG ; issue. ; FIXME: arm64 is an alias for aarch64 on macs, apparently? -; XFAIL: powerpc64, aarch64, arm64, hexagon, riscv, sparc +; FIXME: Fails on s390x (with default arg extension) due to DAGCombiner bug, +; see https://bugs.llvm.org/show_bug.cgi?id=52373. +; XFAIL: powerpc64, aarch64, arm64, hexagon, riscv, sparc, s390x ; Build from the following source with clang -O2. Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_function_name.ll =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_function_name.ll +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_function_name.ll @@ -1,6 +1,6 @@ ; Check that we accept functions with '$' in the name. ; -; RUN: llc -mtriple=s390x-unknown-linux < %s | FileCheck %s +; RUN: llc -mtriple=s390x-unknown-linux -no-arg-exts < %s | FileCheck %s ; define hidden i32 @"_Z54bar$ompvariant$bar"() { entry: Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_function_name.ll.expected =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_function_name.ll.expected +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_function_name.ll.expected @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Check that we accept functions with '$' in the name. ; -; RUN: llc -mtriple=s390x-unknown-linux < %s | FileCheck %s +; RUN: llc -mtriple=s390x-unknown-linux -no-arg-exts < %s | FileCheck %s ; define hidden i32 @"_Z54bar$ompvariant$bar"() { ; CHECK-LABEL: _Z54bar$ompvariant$bar: Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll @@ -1,4 +1,5 @@ -; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s +; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux -no-arg-exts < %s \ +; RUN: | FileCheck %s ; ; NOTE: Machine outliner doesn't run. @x = dso_local global i32 0, align 4 Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs -; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s +; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux -no-arg-exts < %s \ +; RUN: | FileCheck %s ; NOTE: Machine outliner doesn't run. @x = dso_local global i32 0, align 4 Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s +; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux -no-arg-exts < %s \ +; RUN: | FileCheck %s ; ; NOTE: Machine outliner doesn't run. @x = dso_local global i32 0, align 4