diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4537,7 +4537,7 @@
     // address into a register.
     Callee = LowerGlobalOrExternal(Callee, DAG, /*ForCall=*/true);
   } else if (Subtarget.isTarget64BitILP32() &&
-             Callee->getValueType(0) == MVT::i32) {
+             Callee.getValueType() == MVT::i32) {
     // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
     Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
   }
diff --git a/llvm/test/CodeGen/X86/call-structfp.ll b/llvm/test/CodeGen/X86/call-structfp.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-structfp.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnux32 | FileCheck %s
+declare { i64, void ()* } @f()
+define void @pr52357() {
+; CHECK-LABEL: pr52357:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    callq f@PLT
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    jmpq *%rax # TAILCALL
+entry:
+  %0 = tail call { i64, void ()* } @f()
+  %1 = extractvalue { i64, void ()* } %0, 1
+  tail call void %1()
+  ret void
+}