diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -19,11 +19,15 @@
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
 
-// Zbc extension
-TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc")
-TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc")
+// Zbc or Zbkc extension
+TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")
+TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc")
 TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc")
 
+// Zbkx
+TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "zbkx")
+TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "zbkx")
+
 // Zbe extension
 TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe")
 TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc",
@@ -67,5 +71,52 @@
 TARGET_BUILTIN(__builtin_riscv_fsl_64, "WiWiWiWi", "nc", "experimental-zbt,64bit")
 TARGET_BUILTIN(__builtin_riscv_fsr_64, "WiWiWiWi", "nc", "experimental-zbt,64bit")
 
+// Zbkb extension
+TARGET_BUILTIN(__builtin_riscv_brev8, "ZiZi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_zip, "ZiZi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_unzip, "ZiZi", "nc", "zbkb")
+
+// Zknd extension
+TARGET_BUILTIN(__builtin_riscv_aes32dsi, "ZiZiZiIUc", "nc", "zknd")
+TARGET_BUILTIN(__builtin_riscv_aes32dsmi, "ZiZiZiIUc", "nc", "zknd")
+TARGET_BUILTIN(__builtin_riscv_aes64ds, "WiWiWi", "nc", "zknd,64bit")
+TARGET_BUILTIN(__builtin_riscv_aes64dsm, "WiWiWi", "nc", "zknd,64bit")
+TARGET_BUILTIN(__builtin_riscv_aes64im, "WiWi", "nc", "zknd,64bit")
+
+// Zknd & zkne
+TARGET_BUILTIN(__builtin_riscv_aes64ks1i, "WiWiIUi", "nc", "zknd|zkne,64bit")
+TARGET_BUILTIN(__builtin_riscv_aes64ks2, "WiWiWi", "nc", "zknd|zkne,64bit")
+
+// Zkne extension
+TARGET_BUILTIN(__builtin_riscv_aes32esi, "ZiZiZiIUc", "nc", "zkne")
+TARGET_BUILTIN(__builtin_riscv_aes32esmi, "ZiZiZiIUc", "nc", "zkne")
+TARGET_BUILTIN(__builtin_riscv_aes64es, "WiWiWi", "nc", "zkne,64bit")
+TARGET_BUILTIN(__builtin_riscv_aes64esm, "WiWiWi", "nc", "zkne,64bit")
+
+// Zknh extension
+TARGET_BUILTIN(__builtin_riscv_sha256sig0, "LiLi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sig1, "LiLi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sum0, "LiLi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sum1, "LiLi", "nc", "zknh")
+
+TARGET_BUILTIN(__builtin_riscv_sha512sig0h, "ZiZiZi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig0l, "ZiZiZi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig1h, "ZiZiZi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig1l, "ZiZiZi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sum0r, "ZiZiZi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sum1r, "ZiZiZi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha512sig0, "WiWi", "nc", "zknh,64bit")
+TARGET_BUILTIN(__builtin_riscv_sha512sig1, "WiWi", "nc", "zknh,64bit")
+TARGET_BUILTIN(__builtin_riscv_sha512sum0, "WiWi", "nc", "zknh,64bit")
+TARGET_BUILTIN(__builtin_riscv_sha512sum1, "WiWi", "nc", "zknh,64bit")
+
+// Zksed extension
+TARGET_BUILTIN(__builtin_riscv_sm4ed, "LiLiLiIUc", "nc", "zksed")
+TARGET_BUILTIN(__builtin_riscv_sm4ks, "LiLiLiIUc", "nc", "zksed")
+
+// Zksh extension
+TARGET_BUILTIN(__builtin_riscv_sm3p0, "LiLi", "nc", "zksh")
+TARGET_BUILTIN(__builtin_riscv_sm3p1, "LiLi", "nc", "zksh")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18767,6 +18767,8 @@
   case RISCV::BI__builtin_riscv_shfl_64:
   case RISCV::BI__builtin_riscv_unshfl_32:
   case RISCV::BI__builtin_riscv_unshfl_64:
+  case RISCV::BI__builtin_riscv_xperm4:
+  case RISCV::BI__builtin_riscv_xperm8:
   case RISCV::BI__builtin_riscv_xperm_n:
   case RISCV::BI__builtin_riscv_xperm_b:
   case RISCV::BI__builtin_riscv_xperm_h:
@@ -18782,7 +18784,10 @@
   case RISCV::BI__builtin_riscv_fsl_32:
   case RISCV::BI__builtin_riscv_fsr_32:
   case RISCV::BI__builtin_riscv_fsl_64:
-  case RISCV::BI__builtin_riscv_fsr_64: {
+  case RISCV::BI__builtin_riscv_fsr_64:
+  case RISCV::BI__builtin_riscv_brev8:
+  case RISCV::BI__builtin_riscv_zip:
+  case RISCV::BI__builtin_riscv_unzip: {
     switch (BuiltinID) {
     default: llvm_unreachable("unexpected builtin ID");
     // Zbb
@@ -18883,11 +18888,140 @@
     case RISCV::BI__builtin_riscv_fsr_64:
       ID = Intrinsic::riscv_fsr;
       break;
+
+    // Zbkx
+    case RISCV::BI__builtin_riscv_xperm8:
+      ID = Intrinsic::riscv_xperm8;
+      break;
+    case RISCV::BI__builtin_riscv_xperm4:
+      ID = Intrinsic::riscv_xperm4;
+      break;
+
+    // Zbkb
+    case RISCV::BI__builtin_riscv_brev8:
+      ID = Intrinsic::riscv_brev8;
+      break;
+    case RISCV::BI__builtin_riscv_zip:
+      ID = Intrinsic::riscv_zip;
+      break;
+    case RISCV::BI__builtin_riscv_unzip:
+      ID = Intrinsic::riscv_unzip;
+      break;
     }
 
     IntrinsicTypes = {ResultType};
     break;
   }
+
+  // Zk builtins
+
+  // Zknd
+  case RISCV::BI__builtin_riscv_aes32dsi:
+    ID = Intrinsic::riscv_aes32dsi;
+    break;
+  case RISCV::BI__builtin_riscv_aes32dsmi:
+    ID = Intrinsic::riscv_aes32dsmi;
+    break;
+  case RISCV::BI__builtin_riscv_aes64ds:
+    ID = Intrinsic::riscv_aes64ds;
+    break;
+  case RISCV::BI__builtin_riscv_aes64dsm:
+    ID = Intrinsic::riscv_aes64dsm;
+    break;
+  case RISCV::BI__builtin_riscv_aes64im:
+    ID = Intrinsic::riscv_aes64im;
+    break;
+
+  // Zkne
+  case RISCV::BI__builtin_riscv_aes32esi:
+    ID = Intrinsic::riscv_aes32esi;
+    break;
+  case RISCV::BI__builtin_riscv_aes32esmi:
+    ID = Intrinsic::riscv_aes32esmi;
+    break;
+  case RISCV::BI__builtin_riscv_aes64es:
+    ID = Intrinsic::riscv_aes64es;
+    break;
+  case RISCV::BI__builtin_riscv_aes64esm:
+    ID = Intrinsic::riscv_aes64esm;
+    break;
+
+  // Zknd & Zkne
+  case RISCV::BI__builtin_riscv_aes64ks1i:
+    ID = Intrinsic::riscv_aes64ks1i;
+    break;
+  case RISCV::BI__builtin_riscv_aes64ks2:
+    ID = Intrinsic::riscv_aes64ks2;
+    break;
+
+  // Zknh
+  case RISCV::BI__builtin_riscv_sha256sig0:
+    ID = Intrinsic::riscv_sha256sig0;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_sha256sig1:
+    ID = Intrinsic::riscv_sha256sig1;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_sha256sum0:
+    ID = Intrinsic::riscv_sha256sum0;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_sha256sum1:
+    ID = Intrinsic::riscv_sha256sum1;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_sha512sig0:
+    ID = Intrinsic::riscv_sha512sig0;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sig0h:
+    ID = Intrinsic::riscv_sha512sig0h;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sig0l:
+    ID = Intrinsic::riscv_sha512sig0l;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sig1:
+    ID = Intrinsic::riscv_sha512sig1;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sig1h:
+    ID = Intrinsic::riscv_sha512sig1h;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sig1l:
+    ID = Intrinsic::riscv_sha512sig1l;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sum0:
+    ID = Intrinsic::riscv_sha512sum0;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sum0r:
+    ID = Intrinsic::riscv_sha512sum0r;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sum1:
+    ID = Intrinsic::riscv_sha512sum1;
+    break;
+  case RISCV::BI__builtin_riscv_sha512sum1r:
+    ID = Intrinsic::riscv_sha512sum1r;
+    break;
+
+  // Zksed
+  case RISCV::BI__builtin_riscv_sm4ks:
+    ID = Intrinsic::riscv_sm4ks;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_sm4ed:
+    ID = Intrinsic::riscv_sm4ed;
+    IntrinsicTypes = {ResultType};
+    break;
+
+  // Zksh
+  case RISCV::BI__builtin_riscv_sm3p0:
+    ID = Intrinsic::riscv_sm3p0;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_sm3p1:
+    ID = Intrinsic::riscv_sm3p1;
+    IntrinsicTypes = {ResultType};
+    break;
+
   // Vector builtins are handled from here.
 #include "clang/Basic/riscv_vector_builtin_cg.inc"
   }
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3998,6 +3998,27 @@
          << Arg->getSourceRange();
 }
 
+static bool isRISCV32Builtin(unsigned BuiltinID) {
+  // These builtins only work on riscv32 targets.
+  switch (BuiltinID) {
+  case RISCV::BI__builtin_riscv_zip:
+  case RISCV::BI__builtin_riscv_unzip:
+  case RISCV::BI__builtin_riscv_aes32dsi:
+  case RISCV::BI__builtin_riscv_aes32dsmi:
+  case RISCV::BI__builtin_riscv_aes32esi:
+  case RISCV::BI__builtin_riscv_aes32esmi:
+  case RISCV::BI__builtin_riscv_sha512sig0h:
+  case RISCV::BI__builtin_riscv_sha512sig0l:
+  case RISCV::BI__builtin_riscv_sha512sig1h:
+  case RISCV::BI__builtin_riscv_sha512sig1l:
+  case RISCV::BI__builtin_riscv_sha512sum0r:
+  case RISCV::BI__builtin_riscv_sha512sum1r:
+    return true;
+  }
+
+  return false;
+}
+
 bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
                                          unsigned BuiltinID,
                                          CallExpr *TheCall) {
@@ -4008,6 +4029,12 @@
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
   Features.split(ReqFeatures, ',');
 
+  // Check for 32-bit only builtins on a 64-bit target.
+  const llvm::Triple &TT = TI.getTriple();
+  if (TT.getArch() != llvm::Triple::riscv32 && isRISCV32Builtin(BuiltinID))
+    return Diag(TheCall->getCallee()->getBeginLoc(),
+                diag::err_32_bit_builtin_64_bit_tgt);
+
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {
     SmallVector<StringRef> ReqOpFeatures;
@@ -4055,6 +4082,14 @@
   case RISCVVector::BI__builtin_rvv_vsetvlimax:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
            CheckRISCVLMUL(TheCall, 1);
+  // Check if byteselect is in [0, 3]
+  case RISCV::BI__builtin_riscv_aes32dsi:
+  case RISCV::BI__builtin_riscv_aes32dsmi:
+  case RISCV::BI__builtin_riscv_aes32esi:
+  case RISCV::BI__builtin_riscv_aes32esmi:
+  case RISCV::BI__builtin_riscv_sm4ks:
+  case RISCV::BI__builtin_riscv_sm4ed:
+    return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3);
   }
 
   return false;
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkb -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBKB
+
+// RV32ZBKB-LABEL: @brev8(
+// RV32ZBKB-NEXT:  entry:
+// RV32ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKB-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
+// RV32ZBKB-NEXT:    ret i32 [[TMP1]]
+//
+int brev8(int rs1)
+{
+  return __builtin_riscv_brev8(rs1);
+}
+
+// RV32ZBKB-LABEL: @zip(
+// RV32ZBKB-NEXT:  entry:
+// RV32ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKB-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.zip.i32(i32 [[TMP0]])
+// RV32ZBKB-NEXT:    ret i32 [[TMP1]]
+//
+int zip(int rs1)
+{
+  return __builtin_riscv_zip(rs1);
+}
+
+// RV32ZBKB-LABEL: @unzip(
+// RV32ZBKB-NEXT:  entry:
+// RV32ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKB-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.unzip.i32(i32 [[TMP0]])
+// RV32ZBKB-NEXT:    ret i32 [[TMP1]]
+//
+int unzip(int rs1)
+{
+  return __builtin_riscv_unzip(rs1);
+}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBKC
+
+// RV32ZBKC-LABEL: @clmul(
+// RV32ZBKC-NEXT:  entry:
+// RV32ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKC-NEXT:    ret i32 [[TMP2]]
+//
+long clmul(long a, long b) {
+  return __builtin_riscv_clmul(a, b);
+}
+
+// RV32ZBKC-LABEL: @clmulh(
+// RV32ZBKC-NEXT:  entry:
+// RV32ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKC-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBKC-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// RV32ZBKC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKC-NEXT:    ret i32 [[TMP2]]
+//
+long clmulh(long a, long b) {
+  return __builtin_riscv_clmulh(a, b);
+}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBKX
+
+// RV32ZBKX-LABEL: @xperm8(
+// RV32ZBKX-NEXT:  entry:
+// RV32ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKX-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKX-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBKX-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKX-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBKX-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKX-NEXT:    ret i32 [[TMP2]]
+//
+long xperm8(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm8(rs1, rs2);
+}
+
+// RV32ZBKX-LABEL: @xperm4(
+// RV32ZBKX-NEXT:  entry:
+// RV32ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBKX-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBKX-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBKX-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBKX-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBKX-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBKX-NEXT:    ret i32 [[TMP2]]
+//
+long xperm4(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm4(rs1, rs2);
+}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
@@ -0,0 +1,17 @@
+
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBKB
+
+// RV64ZBKB-LABEL: @brev8(
+// RV64ZBKB-NEXT:  entry:
+// RV64ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKB-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
+// RV64ZBKB-NEXT:    ret i32 [[TMP1]]
+//
+int brev8(int rs1)
+{
+  return __builtin_riscv_brev8(rs1);
+}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBKC
+
+// RV64ZBKC-LABEL: @clmul(
+// RV64ZBKC-NEXT:  entry:
+// RV64ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKC-NEXT:    ret i64 [[TMP2]]
+//
+long clmul(long a, long b) {
+  return __builtin_riscv_clmul(a, b);
+}
+
+// RV64ZBKC-LABEL: @clmulh(
+// RV64ZBKC-NEXT:  entry:
+// RV64ZBKC-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKC-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBKC-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBKC-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKC-NEXT:    ret i64 [[TMP2]]
+//
+long clmulh(long a, long b) {
+  return __builtin_riscv_clmulh(a, b);
+}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBKX
+
+// RV64ZBKX-LABEL: @xperm8(
+// RV64ZBKX-NEXT:  entry:
+// RV64ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKX-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBKX-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBKX-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBKX-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBKX-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKX-NEXT:    ret i64 [[TMP2]]
+//
+long xperm8(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm8(rs1, rs2);
+}
+
+// RV64ZBKX-LABEL: @xperm4(
+// RV64ZBKX-NEXT:  entry:
+// RV64ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBKX-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBKX-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBKX-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBKX-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBKX-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBKX-NEXT:    ret i64 [[TMP2]]
+//
+long xperm4(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm4(rs1, rs2);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zknd -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZKND
+
+// RV32ZKND-LABEL: @aes32dsi(
+// RV32ZKND-NEXT:  entry:
+// RV32ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKND-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKND-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKND-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKND-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKND-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKND-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
+// RV32ZKND-NEXT:    ret i32 [[TMP2]]
+//
+int aes32dsi(int rs1, int rs2) {
+  return __builtin_riscv_aes32dsi(rs1, rs2, 3);
+}
+
+// RV32ZKND-LABEL: @aes32dsmi(
+// RV32ZKND-NEXT:  entry:
+// RV32ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKND-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKND-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKND-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKND-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKND-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKND-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsmi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
+// RV32ZKND-NEXT:    ret i32 [[TMP2]]
+//
+int aes32dsmi(int rs1, int rs2) {
+  return __builtin_riscv_aes32dsmi(rs1, rs2, 3);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zkne -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZKNE
+
+// RV32ZKNE-LABEL: @aes32esi(
+// RV32ZKNE-NEXT:  entry:
+// RV32ZKNE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNE-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
+// RV32ZKNE-NEXT:    ret i32 [[TMP2]]
+//
+int aes32esi(int rs1, int rs2) {
+  return __builtin_riscv_aes32esi(rs1, rs2, 3);
+}
+
+// RV32ZKNE-LABEL: @aes32esmi(
+// RV32ZKNE-NEXT:  entry:
+// RV32ZKNE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNE-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esmi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
+// RV32ZKNE-NEXT:    ret i32 [[TMP2]]
+//
+int aes32esmi(int rs1, int rs2) {
+  return __builtin_riscv_aes32esmi(rs1, rs2, 3);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
@@ -0,0 +1,141 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zknh -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZKNH
+
+// RV32ZKNH-LABEL: @sha256sig0(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig0.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP1]]
+//
+long sha256sig0(long rs1) {
+  return __builtin_riscv_sha256sig0(rs1);
+}
+
+// RV32ZKNH-LABEL: @sha256sig1(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig1.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP1]]
+//
+long sha256sig1(long rs1) {
+  return __builtin_riscv_sha256sig1(rs1);
+}
+
+// RV32ZKNH-LABEL: @sha256sum0(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum0.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP1]]
+//
+long sha256sum0(long rs1) {
+  return __builtin_riscv_sha256sum0(rs1);
+}
+
+// RV32ZKNH-LABEL: @sha256sum1(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum1.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP1]]
+//
+long sha256sum1(long rs1) {
+  return __builtin_riscv_sha256sum1(rs1);
+}
+
+// RV32ZKNH-LABEL: @sha512sig0h(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sig0h(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP2]]
+//
+int sha512sig0h(int rs1, int rs2) {
+  return __builtin_riscv_sha512sig0h(rs1, rs2);
+}
+
+// RV32ZKNH-LABEL: @sha512sig0l(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sig0l(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP2]]
+//
+int sha512sig0l(int rs1, int rs2) {
+  return __builtin_riscv_sha512sig0l(rs1, rs2);
+}
+
+// RV32ZKNH-LABEL: @sha512sig1h(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sig1h(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP2]]
+//
+int sha512sig1h(int rs1, int rs2) {
+  return __builtin_riscv_sha512sig1h(rs1, rs2);
+}
+
+// RV32ZKNH-LABEL: @sha512sig1l(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sig1l(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP2]]
+//
+int sha512sig1l(int rs1, int rs2) {
+  return __builtin_riscv_sha512sig1l(rs1, rs2);
+}
+
+// RV32ZKNH-LABEL: @sha512sum0r(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sum0r(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP2]]
+//
+int sha512sum0r(int rs1, int rs2) {
+  return __builtin_riscv_sha512sum0r(rs1, rs2);
+}
+
+// RV32ZKNH-LABEL: @sha512sum1r(
+// RV32ZKNH-NEXT:  entry:
+// RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKNH-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sha512sum1r(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZKNH-NEXT:    ret i32 [[TMP2]]
+//
+int sha512sum1r(int rs1, int rs2) {
+  return __builtin_riscv_sha512sum1r(rs1, rs2);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zksed -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZKSED
+
+// RV32ZKSED-LABEL: @sm4ks(
+// RV32ZKSED-NEXT:  entry:
+// RV32ZKSED-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ks.i32(i32 [[TMP0]], i32 [[TMP1]], i8 0)
+// RV32ZKSED-NEXT:    ret i32 [[TMP2]]
+//
+long sm4ks(long rs1, long rs2) {
+  return __builtin_riscv_sm4ks(rs1, rs2, 0);
+}
+
+
+// RV32ZKSED-LABEL: @sm4ed(
+// RV32ZKSED-NEXT:  entry:
+// RV32ZKSED-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ed.i32(i32 [[TMP0]], i32 [[TMP1]], i8 0)
+// RV32ZKSED-NEXT:    ret i32 [[TMP2]]
+//
+long sm4ed(long rs1, long rs2) {
+  return __builtin_riscv_sm4ed(rs1, rs2, 0);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zksh -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZKSH
+
+// RV32ZKSH-LABEL: @sm3p0(
+// RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKSH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKSH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0.i32(i32 [[TMP0]])
+// RV32ZKSH-NEXT:    ret i32 [[TMP1]]
+//
+long sm3p0(long rs1)
+{
+  return __builtin_riscv_sm3p0(rs1);
+}
+
+// RV32ZKSH-LABEL: @sm3p1(
+// RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZKSH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZKSH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1.i32(i32 [[TMP0]])
+// RV32ZKSH-NEXT:    ret i32 [[TMP1]]
+//
+long sm3p1(long rs1) {
+  return __builtin_riscv_sm3p1(rs1);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
@@ -0,0 +1,38 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZKND-ZKNE
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZKND-ZKNE
+
+// RV64ZKND-ZKNE-LABEL: @aes64ks1i(
+// RV64ZKND-ZKNE-NEXT:  entry:
+// RV64ZKND-ZKNE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-ZKNE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-ZKNE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-ZKNE-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-ZKNE-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.aes64ks1i(i64 [[CONV]], i32 0)
+// RV64ZKND-ZKNE-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKND-ZKNE-NEXT:    ret i32 [[CONV1]]
+//
+int aes64ks1i(int rs1) {
+  return __builtin_riscv_aes64ks1i(rs1, 0);
+}
+
+// RV64ZKND-ZKNE-LABEL: @aes64ks2(
+// RV64ZKND-ZKNE-NEXT:  entry:
+// RV64ZKND-ZKNE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-ZKNE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-ZKNE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-ZKNE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKND-ZKNE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-ZKNE-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-ZKNE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKND-ZKNE-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKND-ZKNE-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.aes64ks2(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKND-ZKNE-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKND-ZKNE-NEXT:    ret i32 [[CONV2]]
+//
+int aes64ks2(int rs1, int rs2) {
+  return __builtin_riscv_aes64ks2(rs1, rs2);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
@@ -0,0 +1,56 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZKND
+
+
+// RV64ZKND-LABEL: @es64dsm(
+// RV64ZKND-NEXT:  entry:
+// RV64ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKND-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.aes64dsm(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKND-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKND-NEXT:    ret i32 [[CONV2]]
+//
+int es64dsm(int rs1, int rs2) {
+  return __builtin_riscv_aes64dsm(rs1, rs2);
+}
+
+
+// RV64ZKND-LABEL: @es64ds(
+// RV64ZKND-NEXT:  entry:
+// RV64ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKND-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKND-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.aes64ds(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKND-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKND-NEXT:    ret i32 [[CONV2]]
+//
+int es64ds(int rs1, int rs2) {
+  return __builtin_riscv_aes64ds(rs1, rs2);
+}
+
+
+// RV64ZKND-LABEL: @es64im(
+// RV64ZKND-NEXT:  entry:
+// RV64ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKND-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKND-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKND-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.aes64im(i64 [[CONV]])
+// RV64ZKND-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKND-NEXT:    ret i32 [[CONV1]]
+//
+int es64im(int rs1) {
+  return __builtin_riscv_aes64im(rs1);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZKNE
+
+
+// RV64ZKNE-LABEL: @aes64es(
+// RV64ZKNE-NEXT:  entry:
+// RV64ZKNE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKNE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNE-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKNE-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKNE-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.aes64es(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKNE-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKNE-NEXT:    ret i32 [[CONV2]]
+//
+int aes64es(int rs1, int rs2) {
+  return __builtin_riscv_aes64es(rs1, rs2);
+}
+
+
+// RV64ZKNE-LABEL: @aes64esm(
+// RV64ZKNE-NEXT:  entry:
+// RV64ZKNE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZKNE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNE-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZKNE-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// RV64ZKNE-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.aes64esm(i64 [[CONV]], i64 [[CONV1]])
+// RV64ZKNE-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
+// RV64ZKNE-NEXT:    ret i32 [[CONV2]]
+//
+int aes64esm(int rs1, int rs2) {
+  return __builtin_riscv_aes64esm(rs1, rs2);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
@@ -0,0 +1,113 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zknh -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZKNH
+
+
+// RV64ZKNH-LABEL: @sha512sig0(
+// RV64ZKNH-NEXT:  entry:
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig0(i64 [[CONV]])
+// RV64ZKNH-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKNH-NEXT:    ret i32 [[CONV1]]
+//
+int sha512sig0(int rs1) {
+  return __builtin_riscv_sha512sig0(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha512sig1(
+// RV64ZKNH-NEXT:  entry:
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig1(i64 [[CONV]])
+// RV64ZKNH-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKNH-NEXT:    ret i32 [[CONV1]]
+//
+int sha512sig1(int rs1) {
+  return __builtin_riscv_sha512sig1(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha512sum0(
+// RV64ZKNH-NEXT:  entry:
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum0(i64 [[CONV]])
+// RV64ZKNH-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKNH-NEXT:    ret i32 [[CONV1]]
+//
+int sha512sum0(int rs1) {
+  return __builtin_riscv_sha512sum0(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha512sum1(
+// RV64ZKNH-NEXT:  entry:
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum1(i64 [[CONV]])
+// RV64ZKNH-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZKNH-NEXT:    ret i32 [[CONV1]]
+//
+int sha512sum1(int rs1) {
+  return __builtin_riscv_sha512sum1(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha256sig0(
+// RV64ZKNH-NEXT:  entry:
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sig0.i64(i64 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
+//
+long sha256sig0(long rs1) {
+  return __builtin_riscv_sha256sig0(rs1);
+}
+
+// RV64ZKNH-LABEL: @sha256sig1(
+// RV64ZKNH-NEXT:  entry:
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sig1.i64(i64 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
+//
+long sha256sig1(long rs1) {
+  return __builtin_riscv_sha256sig1(rs1);
+}
+
+
+// RV64ZKNH-LABEL: @sha256sum0(
+// RV64ZKNH-NEXT:  entry:
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sum0.i64(i64 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
+//
+long sha256sum0(long rs1) {
+  return __builtin_riscv_sha256sum0(rs1);
+}
+
+// RV64ZKNH-LABEL: @sha256sum1(
+// RV64ZKNH-NEXT:  entry:
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sum1.i64(i64 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
+//
+long sha256sum1(long rs1) {
+  return __builtin_riscv_sha256sum1(rs1);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
@@ -0,0 +1,33 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZKSED
+
+// RV64ZKSED-LABEL: @sm4ks(
+// RV64ZKSED-NEXT:  entry:
+// RV64ZKSED-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSED-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSED-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKSED-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZKSED-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKSED-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZKSED-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ks.i64(i64 [[TMP0]], i64 [[TMP1]], i8 0)
+// RV64ZKSED-NEXT:    ret i64 [[TMP2]]
+//
+long sm4ks(long rs1, long rs2) {
+  return __builtin_riscv_sm4ks(rs1, rs2, 0);
+}
+
+// RV64ZKSED-LABEL: @sm4ed(
+// RV64ZKSED-NEXT:  entry:
+// RV64ZKSED-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSED-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSED-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKSED-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZKSED-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKSED-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZKSED-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ed.i64(i64 [[TMP0]], i64 [[TMP1]], i8 0)
+// RV64ZKSED-NEXT:    ret i64 [[TMP2]]
+//
+long sm4ed(long rs1, long rs2) {
+  return __builtin_riscv_sm4ed(rs1, rs2, 0);
+}
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zksh -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZKSH
+
+// RV64ZKSH-LABEL: @sm3p0(
+// RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSH-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKSH-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKSH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sm3p0.i64(i64 [[TMP0]])
+// RV64ZKSH-NEXT:    ret i64 [[TMP1]]
+//
+long sm3p0(long rs1) {
+  return __builtin_riscv_sm3p0(rs1);
+}
+
+
+// RV64ZKSH-LABEL: @sm3p1(
+// RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKSH-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZKSH-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZKSH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sm3p1.i64(i64 [[TMP0]])
+// RV64ZKSH-NEXT:    ret i64 [[TMP1]]
+//
+long sm3p1(long rs1) {
+  return __builtin_riscv_sm3p1(rs1);
+}
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: "-target-feature" "+zbkc"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkx1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKX %s
+// RV32-ZBKX: "-target-feature" "+zbkx"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkb1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKB %s
+// RV32-ZBKB: "-target-feature" "+zbkb"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izknd1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZKND %s
+// RV32-ZKND: "-target-feature" "+zknd"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izkne1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZKNE %s
+// RV32-ZKNE: "-target-feature" "+zkne"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izknh1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZKNH %s
+// RV32-ZKNH: "-target-feature" "+zknh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izksed1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZKSED %s
+// RV32-ZKSED: "-target-feature" "+zksed"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izksh1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZKSH %s
+// RV32-ZKSH: "-target-feature" "+zksh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izkr1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZKR %s
+// RV32-ZKR: "-target-feature" "+zkr"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izkt1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZKT %s
+// RV32-ZKT: "-target-feature" "+zkt"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izk1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZK %s
+// RV32-ZK: "-target-feature" "+zk"
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 1000000{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk