Index: llvm/lib/Transforms/Utils/SimplifyCFG.cpp
===================================================================
--- llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -6441,6 +6441,14 @@
   if (!Options.SimplifyCondBranch)
     return false;
 
+  if (auto *CI = dyn_cast<Instruction>(BI->getCondition()))
+    if (auto *NewCond = SimplifyInstruction(CI, DL)) {
+      BI->setCondition(NewCond);
+      if (CI->use_empty() && !CI->mayHaveSideEffects())
+        CI->eraseFromParent();
+      return requestResimplify();
+    }
+
   // Conditional branch
   if (isValueEqualityComparison(BI)) {
     // If we only have one predecessor, and if it is a branch on this value,
Index: llvm/test/CodeGen/AArch64/cmp-frameindex.ll
===================================================================
--- llvm/test/CodeGen/AArch64/cmp-frameindex.ll
+++ llvm/test/CodeGen/AArch64/cmp-frameindex.ll
@@ -3,15 +3,11 @@
 
 define void @test_frameindex_cmp() {
 ; CHECK-LABEL: test_frameindex_cmp:
-; CHECK:       // %bb.0:
+; CHECK:       // %bb.0: // %bb1
 ; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w30, -16
-; CHECK-NEXT:    cmn sp, #12
-; CHECK-NEXT:    b.eq .LBB0_2
-; CHECK-NEXT:  // %bb.1: // %bb1
 ; CHECK-NEXT:    bl bar
-; CHECK-NEXT:  .LBB0_2: // %common.ret
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %stack = alloca i8
Index: llvm/test/CodeGen/AArch64/large-stack-cmp.ll
===================================================================
--- llvm/test/CodeGen/AArch64/large-stack-cmp.ll
+++ llvm/test/CodeGen/AArch64/large-stack-cmp.ll
@@ -3,7 +3,7 @@
 
 define void @foo() {
 ; CHECK-LABEL: foo:
-; CHECK:       ; %bb.0:
+; CHECK:       ; %bb.0: ; %false
 ; CHECK-NEXT:    stp x28, x27, [sp, #-32]! ; 16-byte Folded Spill
 ; CHECK-NEXT:    stp x29, x30, [sp, #16] ; 16-byte Folded Spill
 ; CHECK-NEXT:    sub sp, sp, #1, lsl #12 ; =4096
@@ -13,15 +13,7 @@
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    .cfi_offset w27, -24
 ; CHECK-NEXT:    .cfi_offset w28, -32
-; CHECK-NEXT:    adds x8, sp, #1, lsl #12 ; =4096
-; CHECK-NEXT:    cmn x8, #32
-; CHECK-NEXT:    b.eq LBB0_2
-; CHECK-NEXT:  ; %bb.1: ; %false
 ; CHECK-NEXT:    bl _baz
-; CHECK-NEXT:    b LBB0_3
-; CHECK-NEXT:  LBB0_2: ; %true
-; CHECK-NEXT:    bl _bar
-; CHECK-NEXT:  LBB0_3: ; %common.ret
 ; CHECK-NEXT:    add sp, sp, #1, lsl #12 ; =4096
 ; CHECK-NEXT:    add sp, sp, #80
 ; CHECK-NEXT:    ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
Index: llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
===================================================================
--- llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
+++ llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll
@@ -12,19 +12,11 @@
 define i32 @test(i32* %ptr) {
 ; CHECK-LABEL: test:
 ; CHECK:       ; %bb.0: ; %bb
-; CHECK-NEXT:    mov x8, x0
-; CHECK-NEXT:    mov w9, wzr
+; CHECK-NEXT:    mov w8, wzr
 ; CHECK-NEXT:  LBB0_1: ; %.thread
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    lsr w11, w9, #1
-; CHECK-NEXT:    sub w10, w9, #1
-; CHECK-NEXT:    mov w9, w11
-; CHECK-NEXT:    tbnz w10, #0, LBB0_1
-; CHECK-NEXT:  ; %bb.2: ; %bb343
-; CHECK-NEXT:    and w9, w10, #0x1
-; CHECK-NEXT:    mov w0, #-1
-; CHECK-NEXT:    str w9, [x8]
-; CHECK-NEXT:    ret
+; CHECK-NEXT:    lsr w8, w8, #1
+; CHECK-NEXT:    b LBB0_1
 bb:
   br label %.thread
 
Index: llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
===================================================================
--- llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
+++ llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
@@ -12,27 +12,8 @@
 
 define void @func() {
 ; CHECK-LABEL: func:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1
-; CHECK-NEXT:    cbnz w8, .LBB0_3
-; CHECK-NEXT:  // %bb.1: // %b1
-; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    .cfi_offset w30, -16
-; CHECK-NEXT:    cbz wzr, .LBB0_4
-; CHECK-NEXT:  // %bb.2: // %b3
-; CHECK-NEXT:    ldr w8, [x8]
-; CHECK-NEXT:    and w0, w8, #0x100
-; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-NEXT:    cbz w0, .LBB0_5
-; CHECK-NEXT:  .LBB0_3: // %common.ret.sink.split
+; CHECK:       // %bb.0: // %b6
 ; CHECK-NEXT:    b extfunc
-; CHECK-NEXT:  .LBB0_4: // %b2
-; CHECK-NEXT:    bl extfunc
-; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-NEXT:    cbnz w0, .LBB0_3
-; CHECK-NEXT:  .LBB0_5: // %common.ret
-; CHECK-NEXT:    ret
   %c0 = icmp sgt i64 0, 0
   br i1 %c0, label %b1, label %b6
 
Index: llvm/test/CodeGen/ARM/no_redundant_trunc_for_cmp.ll
===================================================================
--- llvm/test/CodeGen/ARM/no_redundant_trunc_for_cmp.ll
+++ llvm/test/CodeGen/ARM/no_redundant_trunc_for_cmp.ll
@@ -51,10 +51,6 @@
 define void @test_i8_i16(i8 signext %x) optsize {
 ; CHECK-LABEL: test_i8_i16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    cmp.w r0, #300
-; CHECK-NEXT:    it eq
-; CHECK-NEXT:    beq foo2
-; CHECK-NEXT:  .LBB2_1: @ %if.then
 ; CHECK-NEXT:    b foo1
 entry:
   %x16 = sext i8 %x to i16
Index: llvm/test/CodeGen/Hexagon/loop_correctness.ll
===================================================================
--- llvm/test/CodeGen/Hexagon/loop_correctness.ll
+++ llvm/test/CodeGen/Hexagon/loop_correctness.ll
@@ -73,18 +73,6 @@
 ; CHECK-LABEL: f2:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     loop0(.LBB2_1,#1)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp2: // Block address taken
-; CHECK-NEXT:  .LBB2_1: // %b2
-; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    {
-; CHECK-NEXT:     nop
-; CHECK-NEXT:     nop
-; CHECK-NEXT:    } :endloop0
-; CHECK-NEXT:  // %bb.2: // %b3
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31
 ; CHECK-NEXT:    }
 b0:
@@ -110,7 +98,7 @@
 ; CHECK-NEXT:     loop0(.LBB3_1,#4)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp3: // Block address taken
+; CHECK-NEXT:  .Ltmp2: // Block address taken
 ; CHECK-NEXT:  .LBB3_1: // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
@@ -144,7 +132,7 @@
 ; CHECK-NEXT:     loop0(.LBB4_1,#2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp4: // Block address taken
+; CHECK-NEXT:  .Ltmp3: // Block address taken
 ; CHECK-NEXT:  .LBB4_1: // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
@@ -178,7 +166,7 @@
 ; CHECK-NEXT:     loop0(.LBB5_1,#2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp5: // Block address taken
+; CHECK-NEXT:  .Ltmp4: // Block address taken
 ; CHECK-NEXT:  .LBB5_1: // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
Index: llvm/test/CodeGen/Thumb2/mve-phireg.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-phireg.ll
+++ llvm/test/CodeGen/Thumb2/mve-phireg.ll
@@ -6,90 +6,37 @@
 define arm_aapcs_vfpcc void @k() {
 ; CHECK-LABEL: k:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT:    .pad #4
-; CHECK-NEXT:    sub sp, #4
-; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14}
-; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14}
+; CHECK-NEXT:    .vsave {d14}
+; CHECK-NEXT:    vpush {d14}
+; CHECK-NEXT:    .vsave {d12}
+; CHECK-NEXT:    vpush {d12}
+; CHECK-NEXT:    .vsave {d10}
+; CHECK-NEXT:    vpush {d10}
+; CHECK-NEXT:    .vsave {d8}
+; CHECK-NEXT:    vpush {d8}
 ; CHECK-NEXT:    .pad #16
 ; CHECK-NEXT:    sub sp, #16
-; CHECK-NEXT:    adr.w r8, .LCPI0_0
-; CHECK-NEXT:    adr.w r9, .LCPI0_1
-; CHECK-NEXT:    vldrw.u32 q6, [r8]
-; CHECK-NEXT:    vldrw.u32 q5, [r9]
-; CHECK-NEXT:    vmov.i32 q0, #0x1
-; CHECK-NEXT:    vmov.i8 q1, #0x0
-; CHECK-NEXT:    vmov.i8 q2, #0xff
-; CHECK-NEXT:    vmov.i16 q3, #0x6
-; CHECK-NEXT:    vmov.i16 q4, #0x3
-; CHECK-NEXT:    mov.w r12, #0
-; CHECK-NEXT:  .LBB0_1: @ %vector.body
-; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vand q6, q6, q0
-; CHECK-NEXT:    vand q5, q5, q0
-; CHECK-NEXT:    vcmp.i32 eq, q6, zr
-; CHECK-NEXT:    cmp.w r12, #0
-; CHECK-NEXT:    vpsel q6, q2, q1
-; CHECK-NEXT:    vcmp.i32 eq, q5, zr
-; CHECK-NEXT:    vpsel q5, q2, q1
-; CHECK-NEXT:    vmov r4, r0, d12
-; CHECK-NEXT:    vmov r3, r6, d10
-; CHECK-NEXT:    vmov r1, r2, d11
-; CHECK-NEXT:    vmov.16 q5[0], r3
-; CHECK-NEXT:    vmov.16 q5[1], r6
-; CHECK-NEXT:    vmov r5, r7, d13
-; CHECK-NEXT:    vmov.16 q5[2], r1
-; CHECK-NEXT:    vmov.16 q5[3], r2
-; CHECK-NEXT:    vmov.16 q5[4], r4
-; CHECK-NEXT:    vmov.16 q5[5], r0
-; CHECK-NEXT:    vmov.16 q5[6], r5
-; CHECK-NEXT:    vmov.16 q5[7], r7
-; CHECK-NEXT:    vcmp.i16 ne, q5, zr
-; CHECK-NEXT:    vmov.i32 q5, #0x0
-; CHECK-NEXT:    vpsel q6, q4, q3
-; CHECK-NEXT:    vstrh.16 q6, [r0]
-; CHECK-NEXT:    vmov q6, q5
-; CHECK-NEXT:    bne .LBB0_1
-; CHECK-NEXT:  @ %bb.2: @ %for.cond4.preheader
-; CHECK-NEXT:    movs r6, #0
-; CHECK-NEXT:    cbnz r6, .LBB0_5
-; CHECK-NEXT:  .LBB0_3: @ %for.body10
-; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    cbnz r6, .LBB0_4
-; CHECK-NEXT:    le .LBB0_3
-; CHECK-NEXT:  .LBB0_4: @ %for.cond4.loopexit
-; CHECK-NEXT:    bl l
-; CHECK-NEXT:  .LBB0_5: @ %vector.body105.preheader
-; CHECK-NEXT:    vldrw.u32 q0, [r8]
-; CHECK-NEXT:    vldrw.u32 q1, [r9]
-; CHECK-NEXT:    vmov.i32 q2, #0x8
-; CHECK-NEXT:  .LBB0_6: @ %vector.body105
-; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vadd.i32 q1, q1, q2
-; CHECK-NEXT:    vadd.i32 q0, q0, q2
-; CHECK-NEXT:    cbz r6, .LBB0_7
-; CHECK-NEXT:    le .LBB0_6
-; CHECK-NEXT:  .LBB0_7: @ %vector.body115.ph
-; CHECK-NEXT:    vldrw.u32 q0, [r9]
-; CHECK-NEXT:    vstrw.32 q0, [sp] @ 16-byte Spill
+; CHECK-NEXT:    movw r0, #13107
+; CHECK-NEXT:    vmov.i16 q0, #0x6
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vmov.i16 q1, #0x3
+; CHECK-NEXT:    adr r0, .LCPI0_0
+; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    vstrh.16 q0, [r0]
+; CHECK-NEXT:    vstrw.32 q1, [sp] @ 16-byte Spill
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    vldrw.u32 q1, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.i32 q0, #0x4
-; CHECK-NEXT:  .LBB0_8: @ %vector.body115
+; CHECK-NEXT:  .LBB0_1: @ %vector.body115
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vadd.i32 q1, q1, q0
-; CHECK-NEXT:    b .LBB0_8
+; CHECK-NEXT:    b .LBB0_1
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  @ %bb.9:
+; CHECK-NEXT:  @ %bb.2:
 ; CHECK-NEXT:  .LCPI0_0:
-; CHECK-NEXT:    .long 4 @ 0x4
-; CHECK-NEXT:    .long 5 @ 0x5
-; CHECK-NEXT:    .long 6 @ 0x6
-; CHECK-NEXT:    .long 7 @ 0x7
-; CHECK-NEXT:  .LCPI0_1:
 ; CHECK-NEXT:    .long 0 @ 0x0
 ; CHECK-NEXT:    .long 1 @ 0x1
 ; CHECK-NEXT:    .long 2 @ 0x2
Index: llvm/test/Transforms/CallSiteSplitting/split-loop.ll
===================================================================
--- llvm/test/Transforms/CallSiteSplitting/split-loop.ll
+++ llvm/test/Transforms/CallSiteSplitting/split-loop.ll
@@ -4,14 +4,7 @@
 define i16 @test1() {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 undef, i16 1, i16 0
-; CHECK-NEXT:    [[TOBOOL18:%.*]] = icmp ne i16 [[SPEC_SELECT]], 0
-; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[TOBOOL18]], true
-; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
-; CHECK-NEXT:    br label [[FOR_COND12:%.*]]
-; CHECK:       for.cond12:
-; CHECK-NEXT:    call void @callee(i16 [[SPEC_SELECT]])
-; CHECK-NEXT:    br label [[FOR_COND12]]
+; CHECK-NEXT:    unreachable
 ;
 entry:
   %spec.select = select i1 undef, i16 1, i16 0
@@ -29,16 +22,7 @@
 define i16 @test2() {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[S:%.*]] = select i1 undef, i16 1, i16 0
-; CHECK-NEXT:    [[TOBOOL18:%.*]] = icmp ne i16 [[S]], 0
-; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[TOBOOL18]], true
-; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
-; CHECK-NEXT:    br label [[FOR_COND12:%.*]]
-; CHECK:       for.cond12:
-; CHECK-NEXT:    call void @callee(i16 [[S]])
-; CHECK-NEXT:    [[ADD:%.*]] = add i16 [[S]], 10
-; CHECK-NEXT:    [[ADD2:%.*]] = add i16 [[S]], 10
-; CHECK-NEXT:    br label [[FOR_COND12]]
+; CHECK-NEXT:    unreachable
 ;
 entry:
   %s= select i1 undef, i16 1, i16 0
@@ -58,18 +42,7 @@
 define i16 @test3() {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[S:%.*]] = select i1 undef, i16 1, i16 0
-; CHECK-NEXT:    [[TOBOOL18:%.*]] = icmp ne i16 [[S]], 0
-; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[TOBOOL18]], true
-; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
-; CHECK-NEXT:    br label [[FOR_COND12:%.*]]
-; CHECK:       for.cond12:
-; CHECK-NEXT:    call void @callee(i16 [[S]])
-; CHECK-NEXT:    [[ADD:%.*]] = add i16 [[S]], 10
-; CHECK-NEXT:    [[ADD2:%.*]] = add i16 [[ADD]], 10
-; CHECK-NEXT:    br i1 undef, label [[FOR_COND12]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    ret i16 [[ADD2]]
+; CHECK-NEXT:    unreachable
 ;
 entry:
   %s= select i1 undef, i16 1, i16 0
Index: llvm/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll
===================================================================
--- llvm/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll
+++ llvm/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll
@@ -68,16 +68,6 @@
 define void @foo_swapped(i32 %a, i32 %b) {
 ; CHECK-LABEL: @foo_swapped(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 1, 2
-; CHECK-NEXT:    br i1 [[CMP1]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP_SPLIT:%.*]], !prof [[PROF1:![0-9]+]]
-; CHECK:       for.body:
-; CHECK-NEXT:    [[INC_I:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT:    [[ADD_I:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ 100, [[ENTRY]] ]
-; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[INC_I]], 1
-; CHECK-NEXT:    [[ADD]] = add nsw i32 [[A:%.*]], [[ADD_I]]
-; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[B:%.*]]
-; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_SPLIT]], label [[FOR_BODY]]
-; CHECK:       for.cond.cleanup.split:
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -99,6 +89,3 @@
   ret void
 }
 !0 = !{!"branch_weights", i32 64, i32 4}
-
-;CHECK: !0 = !{!"branch_weights", i32 64, i32 4}
-;CHECK: !1 = !{!"branch_weights", i32 4, i32 64}
Index: llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
+++ llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
@@ -34,24 +34,7 @@
 ; UNROLL:       pred.store.continue3:
 ; UNROLL-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
 ; UNROLL-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
-; UNROLL-NEXT:    br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; UNROLL:       middle.block:
-; UNROLL-NEXT:    [[CMP_N:%.*]] = icmp eq i64 128, 128
-; UNROLL-NEXT:    br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]]
-; UNROLL:       for.body:
-; UNROLL-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 128, [[MIDDLE_BLOCK]] ]
-; UNROLL-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[INDVARS_IV]]
-; UNROLL-NEXT:    [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
-; UNROLL-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[TMP9]], 100
-; UNROLL-NEXT:    br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]]
-; UNROLL:       if.then:
-; UNROLL-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 20
-; UNROLL-NEXT:    store i32 [[ADD]], i32* [[ARRAYIDX]], align 4
-; UNROLL-NEXT:    br label [[FOR_INC]]
-; UNROLL:       for.inc:
-; UNROLL-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
-; UNROLL-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128
-; UNROLL-NEXT:    br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
+; UNROLL-NEXT:    br i1 [[TMP8]], label [[FOR_END:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
 ; UNROLL:       for.end:
 ; UNROLL-NEXT:    ret i32 0
 ;
@@ -140,24 +123,7 @@
 ; VEC:       pred.store.continue2:
 ; VEC-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
 ; VEC-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
-; VEC-NEXT:    br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; VEC:       middle.block:
-; VEC-NEXT:    [[CMP_N:%.*]] = icmp eq i64 128, 128
-; VEC-NEXT:    br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]]
-; VEC:       for.body:
-; VEC-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 128, [[MIDDLE_BLOCK]] ]
-; VEC-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[INDVARS_IV]]
-; VEC-NEXT:    [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
-; VEC-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[TMP15]], 100
-; VEC-NEXT:    br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]]
-; VEC:       if.then:
-; VEC-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP15]], 20
-; VEC-NEXT:    store i32 [[ADD]], i32* [[ARRAYIDX]], align 4
-; VEC-NEXT:    br label [[FOR_INC]]
-; VEC:       for.inc:
-; VEC-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
-; VEC-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128
-; VEC-NEXT:    br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
+; VEC-NEXT:    br i1 [[TMP14]], label [[FOR_END:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
 ; VEC:       for.end:
 ; VEC-NEXT:    ret i32 0
 ;
@@ -230,7 +196,7 @@
 ; UNROLL-NEXT:    [[PREDPHI5]] = select i1 undef, i32 [[VEC_PHI2]], i32 [[TMP9]]
 ; UNROLL-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
 ; UNROLL-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; UNROLL-NEXT:    br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; UNROLL-NEXT:    br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
 ; UNROLL:       middle.block:
 ; UNROLL-NEXT:    [[BIN_RDX:%.*]] = add i32 [[PREDPHI5]], [[PREDPHI]]
 ; UNROLL-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
@@ -369,7 +335,7 @@
 ; VEC-NEXT:    [[PREDPHI]] = select <2 x i1> undef, <2 x i32> [[VEC_PHI]], <2 x i32> [[TMP9]]
 ; VEC-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
 ; VEC-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; VEC-NEXT:    br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; VEC-NEXT:    br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
 ; VEC:       middle.block:
 ; VEC-NEXT:    [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[PREDPHI]])
 ; VEC-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
@@ -458,27 +424,7 @@
 ; UNROLL-NEXT:    br label [[PRED_STORE_CONTINUE6]]
 ; UNROLL:       pred.store.continue6:
 ; UNROLL-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; UNROLL-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], undef
-; UNROLL-NEXT:    br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
-; UNROLL:       middle.block:
-; UNROLL-NEXT:    [[CMP_N:%.*]] = icmp eq i64 undef, undef
-; UNROLL-NEXT:    br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]]
-; UNROLL:       for.body:
-; UNROLL-NEXT:    [[TMP0:%.*]] = phi i64 [ [[TMP6:%.*]], [[FOR_INC:%.*]] ], [ undef, [[MIDDLE_BLOCK]] ]
-; UNROLL-NEXT:    [[TMP1:%.*]] = phi i64 [ [[TMP7:%.*]], [[FOR_INC]] ], [ undef, [[MIDDLE_BLOCK]] ]
-; UNROLL-NEXT:    [[TMP2:%.*]] = getelementptr i8, i8* undef, i64 [[TMP0]]
-; UNROLL-NEXT:    [[TMP3:%.*]] = load i8, i8* [[TMP2]], align 1
-; UNROLL-NEXT:    br i1 [[C]], label [[IF_THEN:%.*]], label [[FOR_INC]]
-; UNROLL:       if.then:
-; UNROLL-NEXT:    [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
-; UNROLL-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
-; UNROLL-NEXT:    store i8 [[TMP5]], i8* [[TMP2]], align 1
-; UNROLL-NEXT:    br label [[FOR_INC]]
-; UNROLL:       for.inc:
-; UNROLL-NEXT:    [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
-; UNROLL-NEXT:    [[TMP7]] = add i64 [[TMP1]], -1
-; UNROLL-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
-; UNROLL-NEXT:    br i1 [[TMP8]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; UNROLL-NEXT:    br i1 undef, label [[FOR_END:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
 ; UNROLL:       for.end:
 ; UNROLL-NEXT:    ret void
 ;
@@ -555,49 +501,23 @@
 ; VEC-NEXT:    [[TMP3:%.*]] = getelementptr i8, i8* [[TMP2]], i32 0
 ; VEC-NEXT:    [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <2 x i8>*
 ; VEC-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x i8>, <2 x i8>* [[TMP4]], align 1
-; VEC-NEXT:    [[TMP5:%.*]] = extractelement <2 x i1> [[BROADCAST_SPLAT]], i32 0
-; VEC-NEXT:    br i1 [[TMP5]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
+; VEC-NEXT:    br i1 [[C]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE3]]
 ; VEC:       pred.store.if:
-; VEC-NEXT:    [[TMP6:%.*]] = extractelement <2 x i8> [[WIDE_LOAD]], i32 0
-; VEC-NEXT:    [[TMP7:%.*]] = zext i8 [[TMP6]] to i32
-; VEC-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
-; VEC-NEXT:    [[TMP9:%.*]] = getelementptr i8, i8* undef, i64 [[TMP0]]
-; VEC-NEXT:    store i8 [[TMP8]], i8* [[TMP9]], align 1
-; VEC-NEXT:    br label [[PRED_STORE_CONTINUE]]
-; VEC:       pred.store.continue:
-; VEC-NEXT:    [[TMP10:%.*]] = extractelement <2 x i1> [[BROADCAST_SPLAT]], i32 1
-; VEC-NEXT:    br i1 [[TMP10]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]]
-; VEC:       pred.store.if2:
-; VEC-NEXT:    [[TMP11:%.*]] = add i64 [[INDEX]], 1
-; VEC-NEXT:    [[TMP12:%.*]] = extractelement <2 x i8> [[WIDE_LOAD]], i32 1
-; VEC-NEXT:    [[TMP13:%.*]] = zext i8 [[TMP12]] to i32
-; VEC-NEXT:    [[TMP14:%.*]] = trunc i32 [[TMP13]] to i8
-; VEC-NEXT:    [[TMP15:%.*]] = getelementptr i8, i8* undef, i64 [[TMP11]]
-; VEC-NEXT:    store i8 [[TMP14]], i8* [[TMP15]], align 1
+; VEC-NEXT:    [[TMP5:%.*]] = extractelement <2 x i8> [[WIDE_LOAD]], i32 0
+; VEC-NEXT:    [[TMP6:%.*]] = zext i8 [[TMP5]] to i32
+; VEC-NEXT:    [[TMP7:%.*]] = trunc i32 [[TMP6]] to i8
+; VEC-NEXT:    [[TMP8:%.*]] = getelementptr i8, i8* undef, i64 [[TMP0]]
+; VEC-NEXT:    store i8 [[TMP7]], i8* [[TMP8]], align 1
+; VEC-NEXT:    [[TMP9:%.*]] = add i64 [[INDEX]], 1
+; VEC-NEXT:    [[TMP10:%.*]] = extractelement <2 x i8> [[WIDE_LOAD]], i32 1
+; VEC-NEXT:    [[TMP11:%.*]] = zext i8 [[TMP10]] to i32
+; VEC-NEXT:    [[TMP12:%.*]] = trunc i32 [[TMP11]] to i8
+; VEC-NEXT:    [[TMP13:%.*]] = getelementptr i8, i8* undef, i64 [[TMP9]]
+; VEC-NEXT:    store i8 [[TMP12]], i8* [[TMP13]], align 1
 ; VEC-NEXT:    br label [[PRED_STORE_CONTINUE3]]
 ; VEC:       pred.store.continue3:
 ; VEC-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; VEC-NEXT:    [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], undef
-; VEC-NEXT:    br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
-; VEC:       middle.block:
-; VEC-NEXT:    [[CMP_N:%.*]] = icmp eq i64 undef, undef
-; VEC-NEXT:    br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]]
-; VEC:       for.body:
-; VEC-NEXT:    [[TMP0:%.*]] = phi i64 [ [[TMP6:%.*]], [[FOR_INC:%.*]] ], [ undef, [[MIDDLE_BLOCK]] ]
-; VEC-NEXT:    [[TMP1:%.*]] = phi i64 [ [[TMP7:%.*]], [[FOR_INC]] ], [ undef, [[MIDDLE_BLOCK]] ]
-; VEC-NEXT:    [[TMP2:%.*]] = getelementptr i8, i8* undef, i64 [[TMP0]]
-; VEC-NEXT:    [[TMP3:%.*]] = load i8, i8* [[TMP2]], align 1
-; VEC-NEXT:    br i1 [[C]], label [[IF_THEN:%.*]], label [[FOR_INC]]
-; VEC:       if.then:
-; VEC-NEXT:    [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
-; VEC-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
-; VEC-NEXT:    store i8 [[TMP5]], i8* [[TMP2]], align 1
-; VEC-NEXT:    br label [[FOR_INC]]
-; VEC:       for.inc:
-; VEC-NEXT:    [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
-; VEC-NEXT:    [[TMP7]] = add i64 [[TMP1]], -1
-; VEC-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
-; VEC-NEXT:    br i1 [[TMP8]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; VEC-NEXT:    br i1 undef, label [[FOR_END:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
 ; VEC:       for.end:
 ; VEC-NEXT:    ret void
 ;
@@ -647,7 +567,7 @@
 ; UNROLL-NEXT:    [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
 ; UNROLL-NEXT:    [[TMP7]] = add i64 [[TMP1]], -1
 ; UNROLL-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
-; UNROLL-NEXT:    br i1 [[TMP8]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; UNROLL-NEXT:    br i1 [[TMP8]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
 ; UNROLL:       for.end:
 ; UNROLL-NEXT:    ret void
 ;
@@ -732,7 +652,7 @@
 ; VEC-NEXT:    [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
 ; VEC-NEXT:    [[TMP7]] = add i64 [[TMP1]], -1
 ; VEC-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
-; VEC-NEXT:    br i1 [[TMP8]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; VEC-NEXT:    br i1 [[TMP8]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
 ; VEC:       for.end:
 ; VEC-NEXT:    ret void
 ;
Index: llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll
+++ llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll
@@ -11,8 +11,7 @@
 ; CHECK-NEXT:    [[C:%.*]] = icmp sle i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    br i1 [[C]], label [[COMMON_RET:%.*]], label [[BB1:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[D:%.*]] = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[D]], i32 927, i32 42
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 icmp sgt (i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), i32 0), i32 927, i32 42
 ; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 42, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[BB1]] ]
Index: llvm/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
+++ llvm/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
@@ -16,15 +16,13 @@
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 1, [[TMP0]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP3]], 31
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT:    br i1 [[TMP5]], label [[COMMON_RET]], label [[BB3:%.*]]
+; CHECK:       BB3:
 ; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x %0], [5 x %0]* @[[GLOB0:[0-9]+]], i32 0, i32 [[TMP0]]
-; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq %0* [[TMP6]], null
-; CHECK-NEXT:    [[OR_COND2:%.*]] = select i1 [[TMP5]], i1 true, i1 [[TMP7]]
-; CHECK-NEXT:    br i1 [[OR_COND2]], label [[COMMON_RET]], label [[BB4:%.*]]
+; CHECK-NEXT:    [[TMP7:%.*]] = icmp slt i32 [[TMP0]], 0
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
-; CHECK:       BB4:
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp slt i32 [[TMP0]], 0
-; CHECK-NEXT:    br label [[COMMON_RET]]
 ;
 Entry:
   %1 = icmp slt i32 %0, 0, !dbg !5
Index: llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
+++ llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
@@ -1002,8 +1002,7 @@
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* @global_pr49510, align 1
 ; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i16 [[TMP0]], 0
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i16 [[TMP0]], 0
-; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[TOBOOL]], [[CMP]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[FOR_COND]], label [[FOR_END:%.*]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_COND]], label [[FOR_END:%.*]]
 ; CHECK:       for.end:
 ; CHECK-NEXT:    ret void
 ;
Index: llvm/test/Transforms/SimplifyCFG/iterative-simplify.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/iterative-simplify.ll
+++ llvm/test/Transforms/SimplifyCFG/iterative-simplify.ll
@@ -11,9 +11,6 @@
 ; CHECK-NEXT:    [[Z16:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    %"alloca point" = bitcast i32 0 to i32
 ; CHECK-NEXT:    store i32 0, i32* [[I]], align 4
-; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i8 1, 0
-; CHECK-NEXT:    br i1 [[TOBOOL]], label [[COND_TRUE:%.*]], label [[COND_FALSE33:%.*]]
-; CHECK:       cond_true:
 ; CHECK-NEXT:    store i32 0, i32* [[Z]], align 4
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb:
@@ -26,8 +23,7 @@
 ; CHECK-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp sgt i32 [[TMP4]], 262144
 ; CHECK-NEXT:    [[TMP56:%.*]] = zext i1 [[TMP5]] to i8
-; CHECK-NEXT:    [[TOBOOL7:%.*]] = icmp ne i8 [[TMP56]], 0
-; CHECK-NEXT:    br i1 [[TOBOOL7]], label [[COND_TRUE8:%.*]], label [[COND_NEXT:%.*]]
+; CHECK-NEXT:    br i1 [[TMP5]], label [[COND_TRUE8:%.*]], label [[COND_NEXT:%.*]]
 ; CHECK:       cond_true8:
 ; CHECK-NEXT:    call void @abort()
 ; CHECK-NEXT:    unreachable
@@ -35,14 +31,10 @@
 ; CHECK-NEXT:    [[TMP9:%.*]] = load i32, i32* [[Z]], align 4
 ; CHECK-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
 ; CHECK-NEXT:    [[TMP1011:%.*]] = zext i1 [[TMP10]] to i8
-; CHECK-NEXT:    [[TOBOOL12:%.*]] = icmp ne i8 [[TMP1011]], 0
-; CHECK-NEXT:    br i1 [[TOBOOL12]], label [[BB]], label [[BB13:%.*]]
+; CHECK-NEXT:    br i1 [[TMP10]], label [[BB]], label [[BB13:%.*]]
 ; CHECK:       bb13:
 ; CHECK-NEXT:    call void @exit(i32 0)
 ; CHECK-NEXT:    unreachable
-; CHECK:       cond_false33:
-; CHECK-NEXT:    call void @exit(i32 0)
-; CHECK-NEXT:    unreachable
 ;
 entry:
   %retval = alloca i32, align 4		; <i32*> [#uses=1]
Index: llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll
+++ llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll
@@ -9,10 +9,9 @@
 define void @test1(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
-; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A_NOT]], i1 [[C]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK-NEXT:    [[B_NOT:%.*]] = xor i1 [[B:%.*]], true
+; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B_NOT]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF0:![0-9]+]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       Y:
@@ -43,10 +42,9 @@
 define void @fake_weights(i1 %a, i1 %b) {
 ; CHECK-LABEL: @fake_weights(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
-; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A_NOT]], i1 [[C]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1:![0-9]+]]
+; CHECK-NEXT:    [[B_NOT:%.*]] = xor i1 [[B:%.*]], true
+; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B_NOT]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF1:![0-9]+]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       Y:
@@ -74,9 +72,10 @@
 define void @test2(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
-; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF2:![0-9]+]]
+; CHECK-NEXT:    [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
+; CHECK-NEXT:    [[B_NOT:%.*]] = xor i1 [[B:%.*]], true
+; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B_NOT]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF2:![0-9]+]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       Y:
@@ -105,9 +104,10 @@
 define void @test3(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
-; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1]]
+; CHECK-NEXT:    [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
+; CHECK-NEXT:    [[B_NOT:%.*]] = xor i1 [[B:%.*]], true
+; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B_NOT]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF1]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       Y:
@@ -136,9 +136,10 @@
 define void @test4(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
-; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1]]
+; CHECK-NEXT:    [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
+; CHECK-NEXT:    [[B_NOT:%.*]] = xor i1 [[B:%.*]], true
+; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B_NOT]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF1]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       Y:
@@ -269,9 +270,8 @@
 define void @test1_swap(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1_swap(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
-; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF5:![0-9]+]]
+; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF0]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       Y:
@@ -300,9 +300,8 @@
 define void @test7(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
-; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]]
-; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF6:![0-9]+]]
+; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF5:![0-9]+]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       Y:
@@ -333,7 +332,7 @@
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[LT:%.*]] = icmp slt i64 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    br i1 [[LT]], label [[A:%.*]], label [[B:%.*]], !prof [[PROF7:![0-9]+]]
+; CHECK-NEXT:    br i1 [[LT]], label [[A:%.*]], label [[B:%.*]], !prof [[PROF6:![0-9]+]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       a:
@@ -372,7 +371,7 @@
 ; CHECK-NEXT:    i32 1, label [[END:%.*]]
 ; CHECK-NEXT:    i32 2, label [[END]]
 ; CHECK-NEXT:    i32 92, label [[END]]
-; CHECK-NEXT:    ], !prof [[PROF8:![0-9]+]]
+; CHECK-NEXT:    ], !prof [[PROF7:![0-9]+]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i1 [ [[RETA:%.*]], [[A]] ], [ [[RET:%.*]], [[END]] ]
 ; CHECK-NEXT:    ret i1 [[COMMON_RET_OP]]
@@ -414,7 +413,7 @@
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
-; CHECK-NEXT:    br i1 [[SWITCH]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]], !prof [[PROF9:![0-9]+]]
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]], !prof [[PROF8:![0-9]+]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       lor.rhs:
@@ -446,7 +445,7 @@
 ; CHECK-LABEL: @test11(
 ; CHECK-NEXT:    [[I:%.*]] = shl i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[I]], 24
-; CHECK-NEXT:    br i1 [[COND]], label [[C:%.*]], label [[A:%.*]], !prof [[PROF10:![0-9]+]]
+; CHECK-NEXT:    br i1 [[COND]], label [[C:%.*]], label [[A:%.*]], !prof [[PROF9:![0-9]+]]
 ; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       a:
@@ -534,7 +533,7 @@
 ; CHECK-NEXT:    [[V3:%.*]] = load i32, i32* @max_regno, align 4
 ; CHECK-NEXT:    [[CMP4:%.*]] = icmp eq i32 [[I_1]], [[V3]]
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[CMP4]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[FOR_EXIT:%.*]], label [[FOR_INC]], !prof [[PROF11:![0-9]+]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[FOR_EXIT:%.*]], label [[FOR_INC]], !prof [[PROF10:![0-9]+]]
 ; CHECK:       for.inc:
 ; CHECK-NEXT:    [[SHL]] = shl i32 [[BIT_0]], 1
 ; CHECK-NEXT:    [[INC19]] = add nsw i32 [[I_1]], 1
@@ -567,7 +566,7 @@
 ; CHECK-LABEL: @HoistThenElseCodeToIf(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[N:%.*]], 0
-; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[TOBOOL]], i32 1, i32 234, !prof [[PROF12:![0-9]+]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[TOBOOL]], i32 1, i32 234, !prof [[PROF11:![0-9]+]]
 ; CHECK-NEXT:    ret i32 [[DOT]]
 ;
 entry:
@@ -591,8 +590,8 @@
 ; CHECK-LABEL: @SimplifyCondBranchToCondBranch(
 ; CHECK-NEXT:  block1:
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[CMPA:%.*]], i1 true, i1 [[CMPB:%.*]]
-; CHECK-NEXT:    [[DOTMUX:%.*]] = select i1 [[CMPA]], i32 0, i32 2, !prof [[PROF13:![0-9]+]]
-; CHECK-NEXT:    [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF14:![0-9]+]]
+; CHECK-NEXT:    [[DOTMUX:%.*]] = select i1 [[CMPA]], i32 0, i32 2, !prof [[PROF12:![0-9]+]]
+; CHECK-NEXT:    [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF13:![0-9]+]]
 ; CHECK-NEXT:    ret i32 [[OUTVAL]]
 ;
 block1:
@@ -618,8 +617,8 @@
 ; CHECK-NEXT:    [[CMPA_NOT:%.*]] = xor i1 [[CMPA:%.*]], true
 ; CHECK-NEXT:    [[CMPB_NOT:%.*]] = xor i1 [[CMPB:%.*]], true
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[CMPA_NOT]], i1 true, i1 [[CMPB_NOT]]
-; CHECK-NEXT:    [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof [[PROF15:![0-9]+]]
-; CHECK-NEXT:    [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF16:![0-9]+]]
+; CHECK-NEXT:    [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof [[PROF14:![0-9]+]]
+; CHECK-NEXT:    [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF15:![0-9]+]]
 ; CHECK-NEXT:    ret i32 [[OUTVAL]]
 ;
 block1:
@@ -643,8 +642,8 @@
 ; CHECK-NEXT:    [[CMPA_NOT:%.*]] = xor i1 [[CMPA:%.*]], true
 ; CHECK-NEXT:    [[CMPB_NOT:%.*]] = xor i1 [[CMPB:%.*]], true
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[CMPA_NOT]], i1 true, i1 [[CMPB_NOT]]
-; CHECK-NEXT:    [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof [[PROF17:![0-9]+]]
-; CHECK-NEXT:    [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF18:![0-9]+]]
+; CHECK-NEXT:    [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof [[PROF16:![0-9]+]]
+; CHECK-NEXT:    [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF17:![0-9]+]]
 ; CHECK-NEXT:    ret i32 [[OUTVAL]]
 ;
 block1:
@@ -669,7 +668,7 @@
 ; CHECK-LABEL: @or_icmps_harmful(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[EXPECTED_TRUE:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    br i1 [[EXPECTED_TRUE]], label [[EXIT:%.*]], label [[RARE:%.*]], !prof [[PROF19:![0-9]+]]
+; CHECK-NEXT:    br i1 [[EXPECTED_TRUE]], label [[EXIT:%.*]], label [[RARE:%.*]], !prof [[PROF18:![0-9]+]]
 ; CHECK:       rare:
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    br i1 [[EXPENSIVE]], label [[EXIT]], label [[FALSE:%.*]]
@@ -702,7 +701,7 @@
 ; CHECK-LABEL: @or_icmps_harmful_inverted(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[EXPECTED_FALSE:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    br i1 [[EXPECTED_FALSE]], label [[RARE:%.*]], label [[EXIT:%.*]], !prof [[PROF20:![0-9]+]]
+; CHECK-NEXT:    br i1 [[EXPECTED_FALSE]], label [[RARE:%.*]], label [[EXIT:%.*]], !prof [[PROF19:![0-9]+]]
 ; CHECK:       rare:
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    br i1 [[EXPENSIVE]], label [[EXIT]], label [[FALSE:%.*]]
@@ -735,7 +734,7 @@
 ; CHECK-NEXT:    [[EXPECTED_TRUE:%.*]] = icmp sgt i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_TRUE]], i1 true, i1 [[EXPENSIVE]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF21:![0-9]+]], !unpredictable !22
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF20:![0-9]+]], !unpredictable !21
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -767,7 +766,7 @@
 ; CHECK-NEXT:    [[EXPECTED_TRUE:%.*]] = icmp sgt i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_TRUE]], i1 true, i1 [[EXPENSIVE]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF23:![0-9]+]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF22:![0-9]+]]
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -799,7 +798,7 @@
 ; CHECK-NEXT:    [[EXPECTED_TRUE:%.*]] = icmp sgt i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_TRUE]], i1 true, i1 [[EXPENSIVE]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF24:![0-9]+]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF23:![0-9]+]]
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -830,7 +829,7 @@
 ; CHECK-NEXT:    [[EXPECTED_TRUE:%.*]] = icmp sle i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_TRUE]], i1 true, i1 [[EXPENSIVE]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF25:![0-9]+]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF24:![0-9]+]]
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -861,7 +860,7 @@
 ; CHECK-NEXT:    [[EXPECTED_FALSE:%.*]] = icmp sgt i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_FALSE]], i1 true, i1 [[EXPENSIVE]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF25]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[EXIT:%.*]], label [[FALSE:%.*]], !prof [[PROF24]]
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -922,7 +921,7 @@
 ; CHECK-LABEL: @and_icmps_harmful(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[EXPECTED_FALSE:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    br i1 [[EXPECTED_FALSE]], label [[RARE:%.*]], label [[EXIT:%.*]], !prof [[PROF20]]
+; CHECK-NEXT:    br i1 [[EXPECTED_FALSE]], label [[RARE:%.*]], label [[EXIT:%.*]], !prof [[PROF19]]
 ; CHECK:       rare:
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    br i1 [[EXPENSIVE]], label [[FALSE:%.*]], label [[EXIT]]
@@ -955,7 +954,7 @@
 ; CHECK-LABEL: @and_icmps_harmful_inverted(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[EXPECTED_TRUE:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    br i1 [[EXPECTED_TRUE]], label [[EXIT:%.*]], label [[RARE:%.*]], !prof [[PROF19]]
+; CHECK-NEXT:    br i1 [[EXPECTED_TRUE]], label [[EXIT:%.*]], label [[RARE:%.*]], !prof [[PROF18]]
 ; CHECK:       rare:
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    br i1 [[EXPENSIVE]], label [[FALSE:%.*]], label [[EXIT]]
@@ -990,7 +989,7 @@
 ; CHECK-NEXT:    [[EXPECTED_FALSE:%.*]] = icmp sgt i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_FALSE]], i1 [[EXPENSIVE]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[FALSE:%.*]], label [[EXIT:%.*]], !prof [[PROF26:![0-9]+]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[FALSE:%.*]], label [[EXIT:%.*]], !prof [[PROF25:![0-9]+]]
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -1022,7 +1021,7 @@
 ; CHECK-NEXT:    [[EXPECTED_TRUE:%.*]] = icmp sle i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_TRUE]], i1 [[EXPENSIVE]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[FALSE:%.*]], label [[EXIT:%.*]], !prof [[PROF26]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[FALSE:%.*]], label [[EXIT:%.*]], !prof [[PROF25]]
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -1053,7 +1052,7 @@
 ; CHECK-NEXT:    [[EXPECTED_TRUE:%.*]] = icmp sgt i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_TRUE]], i1 [[EXPENSIVE]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[FALSE:%.*]], label [[EXIT:%.*]], !prof [[PROF27:![0-9]+]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[FALSE:%.*]], label [[EXIT:%.*]], !prof [[PROF26:![0-9]+]]
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -1084,7 +1083,7 @@
 ; CHECK-NEXT:    [[EXPECTED_FALSE:%.*]] = icmp sle i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[EXPENSIVE:%.*]] = icmp eq i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[EXPECTED_FALSE]], i1 [[EXPENSIVE]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[FALSE:%.*]], label [[EXIT:%.*]], !prof [[PROF27]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[FALSE:%.*]], label [[EXIT:%.*]], !prof [[PROF26]]
 ; CHECK:       false:
 ; CHECK-NEXT:    store i8 42, i8* [[P:%.*]], align 1
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -1135,32 +1134,31 @@
 ; CHECK: attributes #[[ATTR1]] = { nounwind }
 ; CHECK: attributes #[[ATTR2:[0-9]+]] = { noredzone nounwind readnone ssp }
 ;.
-; CHECK: [[PROF0]] = !{!"branch_weights", i32 5, i32 11}
-; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 3}
-; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 5}
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 11, i32 5}
+; CHECK: [[PROF1]] = !{!"branch_weights", i32 3, i32 1}
+; CHECK: [[PROF2]] = !{!"branch_weights", i32 5, i32 1}
 ; CHECK: [[PROF3]] = !{!"branch_weights", i32 7, i32 1, i32 2}
 ; CHECK: [[PROF4]] = !{!"branch_weights", i32 49, i32 12, i32 24, i32 35}
-; CHECK: [[PROF5]] = !{!"branch_weights", i32 11, i32 5}
-; CHECK: [[PROF6]] = !{!"branch_weights", i32 17, i32 15}
-; CHECK: [[PROF7]] = !{!"branch_weights", i32 9, i32 7}
-; CHECK: [[PROF8]] = !{!"branch_weights", i32 17, i32 9, i32 8, i32 7, i32 17}
-; CHECK: [[PROF9]] = !{!"branch_weights", i32 24, i32 33}
-; CHECK: [[PROF10]] = !{!"branch_weights", i32 8, i32 33}
-; CHECK: [[PROF11]] = !{!"branch_weights", i32 112017436, i32 -735157296}
-; CHECK: [[PROF12]] = !{!"branch_weights", i32 3, i32 5}
-; CHECK: [[PROF13]] = !{!"branch_weights", i32 22, i32 12}
-; CHECK: [[PROF14]] = !{!"branch_weights", i32 34, i32 21}
-; CHECK: [[PROF15]] = !{!"branch_weights", i32 33, i32 14}
-; CHECK: [[PROF16]] = !{!"branch_weights", i32 47, i32 8}
-; CHECK: [[PROF17]] = !{!"branch_weights", i32 6, i32 2}
-; CHECK: [[PROF18]] = !{!"branch_weights", i32 8, i32 2}
-; CHECK: [[PROF19]] = !{!"branch_weights", i32 99, i32 1}
-; CHECK: [[PROF20]] = !{!"branch_weights", i32 1, i32 99}
-; CHECK: [[PROF21]] = !{!"branch_weights", i32 199, i32 1}
-; CHECK: [[META22:![0-9]+]] = !{}
-; CHECK: [[PROF23]] = !{!"branch_weights", i32 197, i32 1}
-; CHECK: [[PROF24]] = !{!"branch_weights", i32 100, i32 98}
-; CHECK: [[PROF25]] = !{!"branch_weights", i32 101, i32 99}
-; CHECK: [[PROF26]] = !{!"branch_weights", i32 1, i32 197}
-; CHECK: [[PROF27]] = !{!"branch_weights", i32 99, i32 101}
+; CHECK: [[PROF5]] = !{!"branch_weights", i32 17, i32 15}
+; CHECK: [[PROF6]] = !{!"branch_weights", i32 9, i32 7}
+; CHECK: [[PROF7]] = !{!"branch_weights", i32 17, i32 9, i32 8, i32 7, i32 17}
+; CHECK: [[PROF8]] = !{!"branch_weights", i32 24, i32 33}
+; CHECK: [[PROF9]] = !{!"branch_weights", i32 8, i32 33}
+; CHECK: [[PROF10]] = !{!"branch_weights", i32 112017436, i32 -735157296}
+; CHECK: [[PROF11]] = !{!"branch_weights", i32 3, i32 5}
+; CHECK: [[PROF12]] = !{!"branch_weights", i32 22, i32 12}
+; CHECK: [[PROF13]] = !{!"branch_weights", i32 34, i32 21}
+; CHECK: [[PROF14]] = !{!"branch_weights", i32 33, i32 14}
+; CHECK: [[PROF15]] = !{!"branch_weights", i32 47, i32 8}
+; CHECK: [[PROF16]] = !{!"branch_weights", i32 6, i32 2}
+; CHECK: [[PROF17]] = !{!"branch_weights", i32 8, i32 2}
+; CHECK: [[PROF18]] = !{!"branch_weights", i32 99, i32 1}
+; CHECK: [[PROF19]] = !{!"branch_weights", i32 1, i32 99}
+; CHECK: [[PROF20]] = !{!"branch_weights", i32 199, i32 1}
+; CHECK: [[META21:![0-9]+]] = !{}
+; CHECK: [[PROF22]] = !{!"branch_weights", i32 197, i32 1}
+; CHECK: [[PROF23]] = !{!"branch_weights", i32 100, i32 98}
+; CHECK: [[PROF24]] = !{!"branch_weights", i32 101, i32 99}
+; CHECK: [[PROF25]] = !{!"branch_weights", i32 1, i32 197}
+; CHECK: [[PROF26]] = !{!"branch_weights", i32 99, i32 101}
 ;.
Index: llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll
+++ llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll
@@ -486,13 +486,10 @@
 define void @test12() nounwind {
 ; CHECK-LABEL: @test12(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A_OLD:%.*]] = icmp eq i32 undef, undef
-; CHECK-NEXT:    br i1 [[A_OLD]], label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
+; CHECK-NEXT:    br i1 undef, label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
 ; CHECK:       bb55.us.us:
 ; CHECK-NEXT:    [[B:%.*]] = icmp ugt i32 undef, undef
-; CHECK-NEXT:    [[A:%.*]] = icmp eq i32 undef, undef
-; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[B]], [[A]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB55_US_US]], label [[MALFORMED]]
+; CHECK-NEXT:    br label [[BB55_US_US]]
 ; CHECK:       malformed:
 ; CHECK-NEXT:    ret void
 ;
Index: llvm/test/Transforms/SimplifyCFG/switch_create.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/switch_create.ll
+++ llvm/test/Transforms/SimplifyCFG/switch_create.ll
@@ -639,13 +639,10 @@
 define void @test12() nounwind {
 ; CHECK-LABEL: @test12(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A_OLD:%.*]] = icmp eq i32 undef, undef
-; CHECK-NEXT:    br i1 [[A_OLD]], label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
+; CHECK-NEXT:    br i1 undef, label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
 ; CHECK:       bb55.us.us:
 ; CHECK-NEXT:    [[B:%.*]] = icmp ugt i32 undef, undef
-; CHECK-NEXT:    [[A:%.*]] = icmp eq i32 undef, undef
-; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[B]], [[A]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB55_US_US]], label [[MALFORMED]]
+; CHECK-NEXT:    br label [[BB55_US_US]]
 ; CHECK:       malformed:
 ; CHECK-NEXT:    ret void
 ;
Index: llvm/test/Transforms/SimplifyCFG/two-entry-phi-fold-crash.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/two-entry-phi-fold-crash.ll
+++ llvm/test/Transforms/SimplifyCFG/two-entry-phi-fold-crash.ll
@@ -22,10 +22,7 @@
 ; CHECK-NEXT:    br label [[BB8]]
 ; CHECK:       bb8:
 ; CHECK-NEXT:    [[BORG10]] = phi i32 [ [[BORG4]], [[BB6]] ], [ [[BORG3]], [[BB2]] ]
-; CHECK-NEXT:    [[BORG11:%.*]] = icmp ult i32 [[BORG]], 2
-; CHECK-NEXT:    br i1 [[BORG11]], label [[BB2]], label [[BB12:%.*]]
-; CHECK:       bb12:
-; CHECK-NEXT:    ret i32 1
+; CHECK-NEXT:    br label [[BB2]]
 ;
 bb:
   br label %bb2
Index: llvm/test/Transforms/SimplifyCFG/undef_phi.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/undef_phi.ll
+++ llvm/test/Transforms/SimplifyCFG/undef_phi.ll
@@ -4,17 +4,11 @@
 
 declare void @foo()
 
-; FIXME: We can replace %phi with true.
 define void @test_01(i1 %cond) {
 ; CHECK-LABEL: @test_01(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND:%.*]], i1 true, i1 undef
-; CHECK-NEXT:    br i1 [[DOT]], label [[RET_1:%.*]], label [[COMMON_RET:%.*]]
-; CHECK:       common.ret:
-; CHECK-NEXT:    ret void
-; CHECK:       ret_1:
 ; CHECK-NEXT:    call void @foo()
-; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 %cond, label %if.true, label %if.false