This is an archive of the discontinued LLVM Phabricator instance.

Differential D112614

[WIP] [RISCV] Emit cfi directives for function epilogue
AbandonedPublicDraft

Authored by xgupta on Oct 27 2021, 5:12 AM.

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Unit TestsFailed

TimeTest
90 msx64 debian > Flang.Fir::affine-demotion.fir

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Diff 382646

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll

llvm/test/CodeGen/RISCV/addimm-mulimm.ll

llvm/test/CodeGen/RISCV/addrspacecast.ll

llvm/test/CodeGen/RISCV/aext-to-sext.ll

llvm/test/CodeGen/RISCV/alu32.ll

llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll

llvm/test/CodeGen/RISCV/double-convert.ll

llvm/test/CodeGen/RISCV/exception-pointer-register.ll

llvm/test/CodeGen/RISCV/float-convert.ll

llvm/test/CodeGen/RISCV/fpenv.ll

llvm/test/CodeGen/RISCV/frame-info.ll

llvm/test/CodeGen/RISCV/half-convert.ll

llvm/test/CodeGen/RISCV/imm.ll

llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll

llvm/test/CodeGen/RISCV/large-stack.ll

llvm/test/CodeGen/RISCV/neg-abs.ll

llvm/test/CodeGen/RISCV/patchable-function-entry.ll

llvm/test/CodeGen/RISCV/rv32zba.ll

llvm/test/CodeGen/RISCV/rv32zbb.ll

llvm/test/CodeGen/RISCV/rv32zbp.ll

llvm/test/CodeGen/RISCV/rv32zbs.ll

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

llvm/test/CodeGen/RISCV/rv64zba.ll

llvm/test/CodeGen/RISCV/rv64zbb.ll

llvm/test/CodeGen/RISCV/rv64zbp.ll

llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

llvm/test/CodeGen/RISCV/rvv/calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/combine-sats.ll

llvm/test/CodeGen/RISCV/rvv/combine-splats.ll

llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll

llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll

llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir

llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll

llvm/test/CodeGen/RISCV/rvv/load-mask.ll

llvm/test/CodeGen/RISCV/rvv/localvar.ll

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll

llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

llvm/test/CodeGen/RISCV/rvv/memory-args.ll

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll

llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll

llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/select-fp.ll

llvm/test/CodeGen/RISCV/rvv/select-int.ll

llvm/test/CodeGen/RISCV/rvv/select-sra.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vand-vp.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vor-vp.ll

llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vpload.ll

llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vpstore.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll

llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll

llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll

llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll

llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll

llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

llvm/test/CodeGen/RISCV/scalable-vector-struct.ll

llvm/test/CodeGen/RISCV/select-binop-identity.ll

llvm/test/CodeGen/RISCV/select-constant-xor.ll

llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

llvm/test/CodeGen/RISCV/shadowcallstack.ll

llvm/test/CodeGen/RISCV/shift-and.ll

llvm/test/CodeGen/RISCV/shlimm-addimm.ll

llvm/test/CodeGen/RISCV/split-offsets.ll

llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll

llvm/test/CodeGen/RISCV/stack-realignment.ll

llvm/test/CodeGen/RISCV/tail-calls.ll

llvm/test/CodeGen/RISCV/vararg.ll

llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

llvm/test/CodeGen/RISCV/xaluo.ll

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_function_name.ll.expected