diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -1355,7 +1355,7 @@ class MatrixTileListOperand : Operand { let ParserMatchClass = MatrixTileListAsmOperand<>; - let DecoderMethod = "DecodeMatrixTileListRegisterClass"; + let DecoderMethod = "decodeMatrixTileListRegisterClass"; let EncoderMethod = "EncodeMatrixTileListRegisterClass"; let PrintMethod = "printMatrixTileList"; } diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -37,95 +37,92 @@ // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, +static DecodeStatus decodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, +static DecodeStatus decodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, +static DecodeStatus decodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeMatrixIndexGPR32_12_15RegisterClass( + MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, +static DecodeStatus decodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); template static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, +static DecodeStatus decodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const void *Decoder); -static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -217,11 +214,11 @@ uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, +static DecodeStatus decodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, +static DecodeStatus decodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder); @@ -392,7 +389,7 @@ createAArch64ExternalSymbolizer); } -static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -404,15 +401,15 @@ return Success; } -static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 15) return Fail; - return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); + return decodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); } -static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -424,7 +421,7 @@ return Success; } -static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -436,7 +433,7 @@ return Success; } -static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -448,7 +445,7 @@ return Success; } -static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -460,7 +457,7 @@ return Success; } -static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 30) @@ -473,7 +470,7 @@ return Success; } -static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -485,7 +482,7 @@ return Success; } -static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, +static DecodeStatus decodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { @@ -501,7 +498,7 @@ return Success; } -static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -512,10 +509,9 @@ return Success; } -static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +decodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder) { if (RegNo > 3) return Fail; @@ -526,7 +522,7 @@ return Success; } -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -538,7 +534,7 @@ return Success; } -static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -550,9 +546,9 @@ return Success; } -static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void* Decoder) { + const void *Decoder) { if (RegNo > 31) return Fail; @@ -562,25 +558,25 @@ return Success; } -static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) return Fail; - return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); + return decodeZPRRegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) return Fail; - return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); + return decodeZPRRegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void* Decoder) { + const void *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -589,9 +585,9 @@ return Success; } -static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void* Decoder) { + const void *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -600,9 +596,9 @@ return Success; } -static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void* Decoder) { + const void *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -611,7 +607,7 @@ return Success; } -static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, +static DecodeStatus decodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const void *Decoder) { @@ -644,7 +640,7 @@ return Success; } -static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 15) return Fail; @@ -655,17 +651,17 @@ return Success; } -static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void* Decoder) { + const void *Decoder) { if (RegNo > 7) return Fail; // Just reuse the PPR decode table - return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); + return decodePPRRegisterClass(Inst, RegNo, Addr, Decoder); } -static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) return Fail; @@ -675,7 +671,7 @@ return Success; } -static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) return Fail; @@ -685,7 +681,7 @@ return Success; } -static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -696,7 +692,7 @@ return Success; } -static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) return Fail; @@ -706,7 +702,7 @@ return Success; } -static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) return Fail; @@ -716,7 +712,7 @@ return Success; } -static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 31) @@ -794,11 +790,11 @@ unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); if (IsToVec) { - DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); - DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); + decodeFPR128RegisterClass(Inst, Rd, Address, Decoder); + decodeGPR64RegisterClass(Inst, Rn, Address, Decoder); } else { - DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); - DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); + decodeGPR64RegisterClass(Inst, Rd, Address, Decoder); + decodeFPR128RegisterClass(Inst, Rn, Address, Decoder); } // Add the lane @@ -908,9 +904,9 @@ // if sf == '0' and imm6<5> == '1' then ReservedValue() if (shiftLo >> 5 == 1) return Fail; - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; } case AArch64::ADDXrs: @@ -929,9 +925,9 @@ case AArch64::ORNXrs: case AArch64::EORXrs: case AArch64::EONXrs: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); break; } @@ -954,12 +950,12 @@ case AArch64::MOVKWi: if (shift & (1U << 5)) return Fail; - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); break; case AArch64::MOVZXi: case AArch64::MOVNXi: case AArch64::MOVKXi: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); break; } @@ -996,38 +992,38 @@ case AArch64::LDRSHWui: case AArch64::STRWui: case AArch64::LDRWui: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDRSBXui: case AArch64::LDRSHXui: case AArch64::LDRSWui: case AArch64::STRXui: case AArch64::LDRXui: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDRQui: case AArch64::STRQui: - DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDRDui: case AArch64::STRDui: - DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDRSui: case AArch64::STRSui: - DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDRHui: case AArch64::STRHui: - DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDRBui: case AArch64::STRBui: - DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); break; } - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) Inst.addOperand(MCOperand::createImm(offset)); return Success; @@ -1095,7 +1091,7 @@ case AArch64::STRBpre: case AArch64::LDRBpost: case AArch64::STRBpost: - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); break; } @@ -1146,7 +1142,7 @@ case AArch64::LDAPURHi: case AArch64::LDAPURSHWi: case AArch64::LDAPURi: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDURSBXi: case AArch64::LDURSHXi: @@ -1173,7 +1169,7 @@ case AArch64::LDAPURSBXi: case AArch64::STLURXi: case AArch64::LDAPURXi: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDURQi: case AArch64::STURQi: @@ -1181,7 +1177,7 @@ case AArch64::STRQpre: case AArch64::LDRQpost: case AArch64::STRQpost: - DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDURDi: case AArch64::STURDi: @@ -1189,7 +1185,7 @@ case AArch64::STRDpre: case AArch64::LDRDpost: case AArch64::STRDpost: - DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDURSi: case AArch64::STURSi: @@ -1197,7 +1193,7 @@ case AArch64::STRSpre: case AArch64::LDRSpost: case AArch64::STRSpost: - DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDURHi: case AArch64::STURHi: @@ -1205,7 +1201,7 @@ case AArch64::STRHpre: case AArch64::LDRHpost: case AArch64::STRHpost: - DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::LDURBi: case AArch64::STURBi: @@ -1213,11 +1209,11 @@ case AArch64::STRBpre: case AArch64::LDRBpost: case AArch64::STRBpost: - DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); break; } - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); Inst.addOperand(MCOperand::createImm(offset)); bool IsLoad = fieldFromInstruction(insn, 22, 1); @@ -1249,7 +1245,7 @@ case AArch64::STXRW: case AArch64::STXRB: case AArch64::STXRH: - DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); LLVM_FALLTHROUGH; case AArch64::LDARW: case AArch64::LDARB: @@ -1269,11 +1265,11 @@ case AArch64::LDLARW: case AArch64::LDLARB: case AArch64::LDLARH: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::STLXRX: case AArch64::STXRX: - DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); LLVM_FALLTHROUGH; case AArch64::LDARX: case AArch64::LDAXRX: @@ -1281,29 +1277,29 @@ case AArch64::STLRX: case AArch64::LDLARX: case AArch64::STLLRX: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64::STLXPW: case AArch64::STXPW: - DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); LLVM_FALLTHROUGH; case AArch64::LDAXPW: case AArch64::LDXPW: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64::STLXPX: case AArch64::STXPX: - DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); LLVM_FALLTHROUGH; case AArch64::LDAXPX: case AArch64::LDXPX: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); break; } - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); // You shouldn't load to the same register twice in an instruction... if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || @@ -1359,7 +1355,7 @@ case AArch64::STPSpre: case AArch64::STGPpre: case AArch64::STGPpost: - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); break; } @@ -1382,8 +1378,8 @@ case AArch64::STPXi: case AArch64::LDPSWi: case AArch64::STGPi: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64::LDPWpost: case AArch64::STPWpost: @@ -1395,8 +1391,8 @@ case AArch64::STNPWi: case AArch64::LDPWi: case AArch64::STPWi: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64::LDNPQi: case AArch64::STNPQi: @@ -1406,8 +1402,8 @@ case AArch64::STPQi: case AArch64::LDPQpre: case AArch64::STPQpre: - DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); - DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); + decodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64::LDNPDi: case AArch64::STNPDi: @@ -1417,8 +1413,8 @@ case AArch64::STPDi: case AArch64::LDPDpre: case AArch64::STPDpre: - DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); - DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); + decodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64::LDNPSi: case AArch64::STNPSi: @@ -1428,12 +1424,12 @@ case AArch64::STPSi: case AArch64::LDPSpre: case AArch64::STPSpre: - DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); - DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); + decodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); break; } - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); Inst.addOperand(MCOperand::createImm(offset)); // You shouldn't load to the same register twice in an instruction... @@ -1462,7 +1458,7 @@ return Fail; case AArch64::LDRAAwriteback: case AArch64::LDRABwriteback: - DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, + decodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, Decoder); break; case AArch64::LDRAAindexed: @@ -1470,8 +1466,8 @@ break; } - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); DecodeSImm<10>(Inst, offset, Addr, Decoder); if (writeback && Rt == Rn && Rn != 31) { @@ -1498,39 +1494,39 @@ return Fail; case AArch64::ADDWrx: case AArch64::SUBWrx: - DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + decodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64::ADDSWrx: case AArch64::SUBSWrx: - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64::ADDXrx: case AArch64::SUBXrx: - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64::ADDSXrx: case AArch64::SUBSXrx: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64::ADDXrx64: case AArch64::SUBXrx64: - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64::SUBSXrx64: case AArch64::ADDSXrx64: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); break; } @@ -1548,19 +1544,19 @@ if (Datasize) { if (Inst.getOpcode() == AArch64::ANDSXri) - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); else - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); imm = fieldFromInstruction(insn, 10, 13); if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) return Fail; } else { if (Inst.getOpcode() == AArch64::ANDSWri) - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); else - DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); imm = fieldFromInstruction(insn, 10, 12); if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) return Fail; @@ -1578,9 +1574,9 @@ imm |= fieldFromInstruction(insn, 5, 5); if (Inst.getOpcode() == AArch64::MOVID) - DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); + decodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); else - DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); + decodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); Inst.addOperand(MCOperand::createImm(imm)); @@ -1617,8 +1613,8 @@ imm |= fieldFromInstruction(insn, 5, 5); // Tied operands added twice. - DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); - DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); + decodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); + decodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); @@ -1638,7 +1634,7 @@ if (imm & (1 << (21 - 1))) imm |= ~((1LL << 21) - 1); - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) Inst.addOperand(MCOperand::createImm(imm)); @@ -1663,16 +1659,16 @@ if (Datasize) { if (Rd == 31 && !S) - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); else - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); } else { if (Rd == 31 && !S) - DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); else - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + decodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); } if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) @@ -1742,9 +1738,9 @@ dst |= ~((1LL << 14) - 1); if (fieldFromInstruction(insn, 31, 1) == 0) - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); else - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); Inst.addOperand(MCOperand::createImm(bit)); if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) Inst.addOperand(MCOperand::createImm(dst)); @@ -1752,7 +1748,7 @@ return Success; } -static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, +static DecodeStatus decodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, @@ -1766,22 +1762,20 @@ return Success; } -static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, +static DecodeStatus decodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { - return DecodeGPRSeqPairsClassRegisterClass(Inst, - AArch64::WSeqPairsClassRegClassID, - RegNo, Addr, Decoder); + return decodeGPRSeqPairsClassRegisterClass( + Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder); } -static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, +static DecodeStatus decodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { - return DecodeGPRSeqPairsClassRegisterClass(Inst, - AArch64::XSeqPairsClassRegClassID, - RegNo, Addr, Decoder); + return decodeGPRSeqPairsClassRegisterClass( + Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder); } static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, @@ -1793,9 +1787,9 @@ return Fail; // The same (tied) operand is added twice to the instruction. - DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + decodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); if (Inst.getOpcode() != AArch64::DUPM_ZI) - DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + decodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); Inst.addOperand(MCOperand::createImm(imm)); return Success; } diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -110,8 +110,8 @@ return addOperand(Inst, DAsm->DecoderName(Imm)); \ } -#define DECODE_OPERAND_REG(RegClass) \ -DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) +#define DECODE_OPERAND_REG(RegClass) \ + DECODE_OPERAND(decode##RegClass##RegisterClass, decodeOperand_##RegClass) DECODE_OPERAND_REG(VGPR_32) DECODE_OPERAND_REG(VRegOrLds_32) @@ -342,32 +342,28 @@ return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); } -static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW32, Decoder); } -static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW64, Decoder); } -static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW96, Decoder); } -static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return decodeOperand_AVLdSt_Any(Inst, Imm, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -1016,7 +1016,7 @@ defm VSrc : RegImmOperand<"VS", "VSrc">; def VSrc_128 : RegisterOperand { - let DecoderMethod = "DecodeVS_128RegisterClass"; + let DecoderMethod = "decodeVS_128RegisterClass"; } //===----------------------------------------------------------------------===// @@ -1051,7 +1051,7 @@ // but only allows VGPRs. def VRegSrc_32 : RegisterOperand { //let ParserMatchClass = RegImmMatcher<"VRegSrc32">; - let DecoderMethod = "DecodeVS_32RegisterClass"; + let DecoderMethod = "decodeVS_32RegisterClass"; } //===----------------------------------------------------------------------===// @@ -1059,7 +1059,7 @@ //===----------------------------------------------------------------------===// def ARegSrc_32 : RegisterOperand { - let DecoderMethod = "DecodeAGPR_32RegisterClass"; + let DecoderMethod = "decodeAGPR_32RegisterClass"; let EncoderMethod = "getAVOperandEncoding"; } @@ -1087,37 +1087,37 @@ //===----------------------------------------------------------------------===// def AVSrc_32 : RegisterOperand { - let DecoderMethod = "DecodeAV_32RegisterClass"; + let DecoderMethod = "decodeAV_32RegisterClass"; let EncoderMethod = "getAVOperandEncoding"; } def AVSrc_64 : RegisterOperand { - let DecoderMethod = "DecodeAV_64RegisterClass"; + let DecoderMethod = "decodeAV_64RegisterClass"; let EncoderMethod = "getAVOperandEncoding"; } def AVLdSt_32 : RegisterOperand { - let DecoderMethod = "DecodeAVLdSt_32RegisterClass"; + let DecoderMethod = "decodeAVLdSt_32RegisterClass"; let EncoderMethod = "getAVOperandEncoding"; } def AVLdSt_64 : RegisterOperand { - let DecoderMethod = "DecodeAVLdSt_64RegisterClass"; + let DecoderMethod = "decodeAVLdSt_64RegisterClass"; let EncoderMethod = "getAVOperandEncoding"; } def AVLdSt_96 : RegisterOperand { - let DecoderMethod = "DecodeAVLdSt_96RegisterClass"; + let DecoderMethod = "decodeAVLdSt_96RegisterClass"; let EncoderMethod = "getAVOperandEncoding"; } def AVLdSt_128 : RegisterOperand { - let DecoderMethod = "DecodeAVLdSt_128RegisterClass"; + let DecoderMethod = "decodeAVLdSt_128RegisterClass"; let EncoderMethod = "getAVOperandEncoding"; } def AVLdSt_160 : RegisterOperand { - let DecoderMethod = "DecodeAVLdSt_160RegisterClass"; + let DecoderMethod = "decodeAVLdSt_160RegisterClass"; let EncoderMethod = "getAVOperandEncoding"; } diff --git a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp --- a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp +++ b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp @@ -126,7 +126,7 @@ ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP, ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK}; -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) { @@ -146,7 +146,7 @@ if (RegNo > 3) RegNo += 8; // 4 for r12, etc... - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); + return decodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } #include "ARCGenDisassemblerTables.inc" @@ -169,7 +169,7 @@ // We have the 9-bit immediate in the low bits, 6-bit register in high bits. unsigned S9 = Insn & 0x1ff; unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9; - DecodeGPR32RegisterClass(Inst, R, Address, Dec); + decodeGPR32RegisterClass(Inst, R, Address, Dec); Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9))); return MCDisassembler::Success; } @@ -234,7 +234,7 @@ return MCDisassembler::Fail; } SrcC = decodeCField(Insn); - DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder); + decodeGPR32RegisterClass(Inst, SrcC, Address, Decoder); LImm = (Insn >> 32); Inst.addOperand(MCOperand::createImm(LImm)); Inst.addOperand(MCOperand::createImm(0)); @@ -252,7 +252,7 @@ return MCDisassembler::Fail; } DstA = decodeAField(Insn); - DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder); + decodeGPR32RegisterClass(Inst, DstA, Address, Decoder); LImm = (Insn >> 32); Inst.addOperand(MCOperand::createImm(LImm)); Inst.addOperand(MCOperand::createImm(0)); @@ -265,9 +265,9 @@ unsigned DstA, SrcB; LLVM_DEBUG(dbgs() << "Decoding LdRLimm\n"); DstA = decodeAField(Insn); - DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder); + decodeGPR32RegisterClass(Inst, DstA, Address, Decoder); SrcB = decodeBField(Insn); - DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder); + decodeGPR32RegisterClass(Inst, SrcB, Address, Decoder); if (decodeCField(Insn) != 62) { LLVM_DEBUG(dbgs() << "Decoding LdRLimm found non-limm register."); return MCDisassembler::Fail; @@ -293,7 +293,7 @@ return MCDisassembler::Success; } - return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder); + return decodeGPR32RegisterClass(Inst, RegNum, Address, Decoder); }; if (MCDisassembler::Success != DecodeRegisterOrImm(G, 0)) @@ -308,7 +308,7 @@ unsigned DstB; LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n"); DstB = decodeBField(Insn); - DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); + decodeGPR32RegisterClass(Inst, DstB, Address, Decoder); using Field = decltype(Insn); Field U6Field = fieldFromInstruction(Insn, 6, 6); Inst.addOperand(MCOperand::createImm(U6Field)); @@ -320,7 +320,7 @@ static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn, uint64_t Address, const void *Decoder) { unsigned DstB = decodeBField(Insn); - DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); + decodeGPR32RegisterClass(Inst, DstB, Address, Decoder); using Field = decltype(Insn); Field U6 = fieldFromInstruction(Insn, 6, 6); Inst.addOperand(MCOperand::createImm(U6)); @@ -330,7 +330,7 @@ static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn, uint64_t Address, const void *Decoder) { unsigned DstB = decodeBField(Insn); - DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); + decodeGPR32RegisterClass(Inst, DstB, Address, Decoder); using Field = decltype(Insn); Field Lower = fieldFromInstruction(Insn, 6, 6); Field Upper = fieldFromInstruction(Insn, 0, 5); diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1282,7 +1282,7 @@ let PrintMethod = "printAddrMode6OffsetOperand"; let MIOperandInfo = (ops GPR); let EncoderMethod = "getAddrMode6OffsetOpValue"; - let DecoderMethod = "DecodeGPRRegisterClass"; + let DecoderMethod = "decodeGPRRegisterClass"; } // Special version of addrmode6 to handle alignment encoding for VST1/VLD1 @@ -1467,7 +1467,7 @@ def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; } def t_addr_offset_none : MemOperand { let PrintMethod = "printAddrMode7Operand"; - let DecoderMethod = "DecodetGPRRegisterClass"; + let DecoderMethod = "decodetGPRRegisterClass"; let ParserMatchClass = MemNoOffsetTAsmOperand; let MIOperandInfo = (ops tGPR:$base); } @@ -4126,11 +4126,11 @@ def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos), (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>; def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), - (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; + (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), (SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), - (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; + (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -173,7 +173,7 @@ : AsmOperandClass { let Name = "MemNoOffsetT2"; } def t2_addr_offset_none : MemOperand { let PrintMethod = "printAddrMode7Operand"; - let DecoderMethod = "DecodeGPRnopcRegisterClass"; + let DecoderMethod = "decodeGPRnopcRegisterClass"; let ParserMatchClass = MemNoOffsetT2AsmOperand; let MIOperandInfo = (ops GPRnopc:$base); } @@ -183,7 +183,7 @@ : AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; } def t2_nosp_addr_offset_none : MemOperand { let PrintMethod = "printAddrMode7Operand"; - let DecoderMethod = "DecoderGPRRegisterClass"; + let DecoderMethod = "decoderGPRRegisterClass"; let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand; let MIOperandInfo = (ops rGPR:$base); } @@ -3124,7 +3124,7 @@ def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)), (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; -def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, +def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, (sext_bottom_16 rGPR:$Rm))), (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -174,70 +174,88 @@ // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); +static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); static DecodeStatus -DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, +decodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, +static DecodeStatus decodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, +static DecodeStatus decodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeGPRwithZRnospRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRwithZRnospRegisterClass( - MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); +static DecodeStatus decodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus decodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); @@ -1135,8 +1153,9 @@ ARM::R12, 0, ARM::LR, ARM::APSR }; -static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; @@ -1145,7 +1164,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) @@ -1159,22 +1178,22 @@ return MCDisassembler::Success; } -static DecodeStatus -DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 15) S = MCDisassembler::SoftFail; - Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + Check(S, decodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } -static DecodeStatus -DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 15) @@ -1183,13 +1202,13 @@ return MCDisassembler::Success; } - Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + Check(S, decodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } -static DecodeStatus -DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 15) @@ -1201,25 +1220,27 @@ if (RegNo == 13) Check(S, MCDisassembler::SoftFail); - Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + Check(S, decodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } -static DecodeStatus -DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeGPRwithZRnospRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 13) return MCDisassembler::Fail; - Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); + Check(S, decodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } -static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; - return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); + return decodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } static const uint16_t GPRPairDecoderTable[] = { @@ -1227,8 +1248,9 @@ ARM::R8_R9, ARM::R10_R11, ARM::R12_SP }; -static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { DecodeStatus S = MCDisassembler::Success; // According to the Arm ARM RegNo = 14 is undefined, but we return fail @@ -1244,8 +1266,9 @@ return S; } -static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 13) return MCDisassembler::Fail; @@ -1257,7 +1280,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo != 13) @@ -1268,8 +1291,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { unsigned Register = 0; switch (RegNo) { case 0: @@ -1298,8 +1322,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { DecodeStatus S = MCDisassembler::Success; const FeatureBitset &featureBits = @@ -1308,7 +1333,7 @@ if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) S = MCDisassembler::SoftFail; - Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + Check(S, decodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } @@ -1323,8 +1348,9 @@ ARM::S28, ARM::S29, ARM::S30, ARM::S31 }; -static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -1333,9 +1359,10 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { - return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); +static DecodeStatus decodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + return decodeSPRRegisterClass(Inst, RegNo, Address, Decoder); } static const uint16_t DPRDecoderTable[] = { @@ -1349,8 +1376,9 @@ ARM::D28, ARM::D29, ARM::D30, ARM::D31 }; -static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { const FeatureBitset &featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); @@ -1364,26 +1392,28 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; - return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); + return decodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; - return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); + return decodeSPRRegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus -DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; - return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); + return decodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } static const uint16_t QPRDecoderTable[] = { @@ -1393,8 +1423,9 @@ ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 }; -static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 31 || (RegNo & 1) != 0) return MCDisassembler::Fail; RegNo >>= 1; @@ -1413,8 +1444,9 @@ ARM::Q15 }; -static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 30) return MCDisassembler::Fail; @@ -1434,8 +1466,7 @@ ARM::D28_D30, ARM::D29_D31 }; -static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 29) @@ -1481,7 +1512,7 @@ unsigned imm = fieldFromInstruction(Val, 7, 5); // Register-immediate - if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; ARM_AM::ShiftOpc Shift = ARM_AM::lsl; @@ -1518,9 +1549,9 @@ unsigned Rs = fieldFromInstruction(Val, 8, 4); // Register-register - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) return MCDisassembler::Fail; ARM_AM::ShiftOpc Shift = ARM_AM::lsl; @@ -1575,11 +1606,11 @@ for (unsigned i = 0; i < 16; ++i) { if (Val & (1 << i)) { if (CLRM) { - if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { + if (!Check(S, decodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { return MCDisassembler::Fail; } } else { - if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, i, Address, Decoder))) return MCDisassembler::Fail; // Writeback not allowed if Rn is in the target list. if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) @@ -1605,10 +1636,10 @@ S = MCDisassembler::SoftFail; } - if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) + if (!Check(S, decodeSPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail; for (unsigned i = 0; i < (regs - 1); ++i) { - if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) + if (!Check(S, decodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) return MCDisassembler::Fail; } @@ -1630,10 +1661,10 @@ S = MCDisassembler::SoftFail; } - if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler::Fail; for (unsigned i = 0; i < (regs - 1); ++i) { - if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) return MCDisassembler::Fail; } @@ -1754,7 +1785,7 @@ Inst.addOperand(MCOperand::createImm(coproc)); Inst.addOperand(MCOperand::createImm(CRd)); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; switch (Inst.getOpcode()) { @@ -1869,14 +1900,14 @@ case ARM::STRT_POST_IMM: case ARM::STRBT_POST_REG: case ARM::STRBT_POST_IMM: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; break; default: break; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; // On loads, the writeback operand comes after Rt. @@ -1889,14 +1920,14 @@ case ARM::LDRBT_POST_IMM: case ARM::LDRT_POST_REG: case ARM::LDRT_POST_IMM: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; break; default: break; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; ARM_AM::AddrOpc Op = ARM_AM::add; @@ -1914,7 +1945,7 @@ S = MCDisassembler::SoftFail; // UNPREDICTABLE if (reg) { - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; ARM_AM::ShiftOpc Opc = ARM_AM::lsl; switch( fieldFromInstruction(Insn, 5, 2)) { @@ -1980,9 +2011,9 @@ if (ShOp == ARM_AM::ror && imm == 0) ShOp = ARM_AM::rrx; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; unsigned shift; if (U) @@ -2119,7 +2150,7 @@ case ARM::STRH: case ARM::STRH_PRE: case ARM::STRH_POST: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -2127,7 +2158,7 @@ } } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; switch (Inst.getOpcode()) { case ARM::STRD: @@ -2136,7 +2167,7 @@ case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt + 1, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -2160,7 +2191,7 @@ case ARM::LDRSB_POST: case ARM::LDRHTr: case ARM::LDRSBTr: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -2168,15 +2199,15 @@ } } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (type) { Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); } else { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(U)); } @@ -2209,7 +2240,7 @@ } Inst.addOperand(MCOperand::createImm(mode)); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; return S; @@ -2227,11 +2258,11 @@ if (pred == 0xF) return DecodeCPSInstruction(Inst, Insn, Address, Decoder); - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -2317,9 +2348,9 @@ return DecodeRFEInstruction(Inst, Insn, Address, Decoder); } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; // Tied if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -2454,9 +2485,9 @@ imm |= (fieldFromInstruction(Insn, 26, 1) << 11); if (Inst.getOpcode() == ARM::t2MOVTi16) - if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) @@ -2477,10 +2508,10 @@ imm |= (fieldFromInstruction(Insn, 16, 4) << 12); if (Inst.getOpcode() == ARM::MOVTi16) - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) @@ -2505,13 +2536,13 @@ if (pred == 0xF) return DecodeCPSInstruction(Inst, Insn, Address, Decoder); - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) @@ -2531,9 +2562,9 @@ if (Pred == 0xF) return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) return MCDisassembler::Fail; @@ -2577,7 +2608,7 @@ unsigned imm = fieldFromInstruction(Val, 0, 12); unsigned Rn = fieldFromInstruction(Val, 13, 4); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!add) imm *= -1; @@ -2598,7 +2629,7 @@ unsigned U = fieldFromInstruction(Val, 8, 1); unsigned imm = fieldFromInstruction(Val, 0, 8); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (U) @@ -2618,7 +2649,7 @@ unsigned U = fieldFromInstruction(Val, 8, 1); unsigned imm = fieldFromInstruction(Val, 0, 8); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (U) @@ -2631,7 +2662,7 @@ static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); + return decodeGPRRegisterClass(Inst, Val, Address, Decoder); } static DecodeStatus @@ -2698,7 +2729,7 @@ unsigned Rm = fieldFromInstruction(Val, 0, 4); unsigned align = fieldFromInstruction(Val, 4, 2); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; if (!align) Inst.addOperand(MCOperand::createImm(0)); @@ -2730,7 +2761,7 @@ case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: - if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPairRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VLD2b16: @@ -2742,11 +2773,11 @@ case ARM::VLD2b32wb_register: case ARM::VLD2b8wb_fixed: case ARM::VLD2b8wb_register: - if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; } @@ -2764,7 +2795,8 @@ case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VLD3q8: @@ -2779,7 +2811,8 @@ case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -2800,7 +2833,8 @@ case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VLD3q8: @@ -2815,7 +2849,8 @@ case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -2830,7 +2865,8 @@ case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VLD4q8: @@ -2839,7 +2875,8 @@ case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -2912,7 +2949,7 @@ case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, wb, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -2966,7 +3003,7 @@ // variant encodes Rm == 0xf. Anything else is a register offset post- // increment and we need to add the register operand to the instruction. if (Rm != 0xD && Rm != 0xF && - !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + !Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VLD2d8wb_fixed: @@ -3114,7 +3151,7 @@ case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, wb, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -3131,7 +3168,7 @@ if (Rm == 0xD) Inst.addOperand(MCOperand::createReg(0)); else if (Rm != 0xF) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } break; @@ -3186,7 +3223,7 @@ case ARM::VST2d32wb_register: case ARM::VST2d8wb_fixed: case ARM::VST2d8wb_register: - if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPairRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VST2b16: @@ -3198,11 +3235,11 @@ case ARM::VST2b32wb_register: case ARM::VST2b8wb_fixed: case ARM::VST2b8wb_register: - if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; } @@ -3220,7 +3257,8 @@ case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VST3q8: @@ -3235,7 +3273,8 @@ case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -3256,7 +3295,8 @@ case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VST3q8: @@ -3271,7 +3311,8 @@ case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -3286,7 +3327,8 @@ case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VST4q8: @@ -3295,7 +3337,8 @@ case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -3325,20 +3368,20 @@ case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: - if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPairRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; } if (Rm != 0xF) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); @@ -3346,7 +3389,7 @@ // variant encodes Rm == 0xf. Anything else is a register offset post- // increment and we need to add the register operand to the instruction. if (Rm != 0xD && Rm != 0xF && - !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + !Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; return S; @@ -3369,18 +3412,18 @@ case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: - if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPairRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: - if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; } @@ -3388,12 +3431,12 @@ if (Rm != 0xF) Inst.addOperand(MCOperand::createImm(0)); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xD && Rm != 0xF) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } @@ -3410,25 +3453,27 @@ unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, Address, + Decoder))) return MCDisassembler::Fail; if (Rm != 0xF) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(0)); if (Rm == 0xD) Inst.addOperand(MCOperand::createReg(0)); else if (Rm != 0xF) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } @@ -3460,27 +3505,30 @@ } } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) + if (!Check(S, + decodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, Address, + Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, (Rd + 3 * inc) % 32, Address, + Decoder))) return MCDisassembler::Fail; if (Rm != 0xF) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm == 0xD) Inst.addOperand(MCOperand::createReg(0)); else if (Rm != 0xF) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } @@ -3502,11 +3550,11 @@ unsigned Q = fieldFromInstruction(Insn, 6, 1); if (Q) { - if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; } else { - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; } Inst.addOperand(MCOperand::createImm(imm)); @@ -3516,14 +3564,14 @@ case ARM::VORRiv2i32: case ARM::VBICiv4i16: case ARM::VBICiv2i32: - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::VORRiv8i16: case ARM::VORRiv4i32: case ARM::VBICiv8i16: case ARM::VBICiv4i32: - if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; break; default: @@ -3550,7 +3598,7 @@ if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) return MCDisassembler::Fail; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(imm)); @@ -3568,17 +3616,17 @@ unsigned Qd = fieldFromInstruction(Insn, 13, 3); Qd |= fieldFromInstruction(Insn, 22, 1) << 3; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); unsigned Qn = fieldFromInstruction(Insn, 17, 3); Qn |= fieldFromInstruction(Insn, 7, 1) << 3; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) return MCDisassembler::Fail; unsigned Qm = fieldFromInstruction(Insn, 1, 3); Qm |= fieldFromInstruction(Insn, 5, 1) << 3; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) return MCDisassembler::Fail; if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); @@ -3597,9 +3645,9 @@ Rm |= fieldFromInstruction(Insn, 5, 1) << 4; unsigned size = fieldFromInstruction(Insn, 18, 2); - if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(8 << size)); @@ -3642,25 +3690,25 @@ Rm |= fieldFromInstruction(Insn, 5, 1) << 4; unsigned op = fieldFromInstruction(Insn, 6, 1); - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if (op) { - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler::Fail; // Writeback + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; // Writeback } switch (Inst.getOpcode()) { case ARM::VTBL2: case ARM::VTBX2: - if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeDPairRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; return S; @@ -3673,7 +3721,7 @@ unsigned dst = fieldFromInstruction(Insn, 8, 3); unsigned imm = fieldFromInstruction(Insn, 0, 8); - if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) + if (!Check(S, decodetGPRRegisterClass(Inst, dst, Address, Decoder))) return MCDisassembler::Fail; switch(Inst.getOpcode()) { @@ -3721,9 +3769,9 @@ unsigned Rn = fieldFromInstruction(Val, 0, 3); unsigned Rm = fieldFromInstruction(Val, 3, 3); - if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodetGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; return S; @@ -3736,7 +3784,7 @@ unsigned Rn = fieldFromInstruction(Val, 0, 3); unsigned imm = fieldFromInstruction(Val, 3, 5); - if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(imm)); @@ -3781,9 +3829,9 @@ break; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(imm)); @@ -3860,7 +3908,7 @@ return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; } @@ -3948,7 +3996,7 @@ return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; } @@ -4028,7 +4076,7 @@ return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; } @@ -4069,7 +4117,7 @@ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); } - if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4113,7 +4161,7 @@ return MCDisassembler::Fail; break; default: - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; } @@ -4165,7 +4213,7 @@ unsigned Rn = fieldFromInstruction(Val, 9, 4); unsigned imm = fieldFromInstruction(Val, 0, 9); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4181,7 +4229,7 @@ unsigned Rn = fieldFromInstruction(Val, 8, 4); unsigned imm = fieldFromInstruction(Val, 0, 8); - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4196,7 +4244,7 @@ unsigned Rn = fieldFromInstruction(Val, 8, 4); unsigned imm = fieldFromInstruction(Val, 0, 8); - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(imm)); @@ -4269,7 +4317,7 @@ break; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4286,7 +4334,7 @@ unsigned Rn = fieldFromInstruction(Val, 8, 3); unsigned imm = fieldFromInstruction(Val, 0, 8); - if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeT2Imm7(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4303,9 +4351,9 @@ unsigned Rn = fieldFromInstruction(Val, 8, 4); unsigned imm = fieldFromInstruction(Val, 0, 8); if (WriteBack) { - if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + } else if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeT2Imm7(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4356,15 +4404,15 @@ } if (!load) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; if (load) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } @@ -4393,7 +4441,7 @@ break; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(imm)); @@ -4419,18 +4467,18 @@ unsigned Rdm = fieldFromInstruction(Insn, 0, 3); Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(ARM::SP)); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler::Fail; } else if (Inst.getOpcode() == ARM::tADDspr) { unsigned Rm = fieldFromInstruction(Insn, 3, 4); Inst.addOperand(MCOperand::createReg(ARM::SP)); Inst.addOperand(MCOperand::createReg(ARM::SP)); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } return S; @@ -4453,7 +4501,7 @@ unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned add = fieldFromInstruction(Insn, 4, 1); - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(add)); @@ -4466,9 +4514,9 @@ unsigned Rn = fieldFromInstruction(Insn, 3, 4); unsigned Qm = fieldFromInstruction(Insn, 0, 3); - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) return MCDisassembler::Fail; return S; @@ -4481,7 +4529,7 @@ unsigned Qm = fieldFromInstruction(Insn, 8, 3); int imm = fieldFromInstruction(Insn, 0, 7); - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) return MCDisassembler::Fail; if(!fieldFromInstruction(Insn, 7, 1)) { @@ -4547,9 +4595,9 @@ unsigned Rm = fieldFromInstruction(Insn, 0, 4); if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; return S; } @@ -4787,9 +4835,9 @@ if (Rn == 0xF) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -4807,15 +4855,15 @@ unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4); - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -4836,9 +4884,9 @@ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4863,9 +4911,9 @@ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; if (Rm == 0xF) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4888,9 +4936,9 @@ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4913,9 +4961,9 @@ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail; @@ -4968,24 +5016,24 @@ break; } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if (Rm != 0xF) { // Writeback - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else Inst.addOperand(MCOperand::createReg(0)); } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(index)); @@ -5036,21 +5084,21 @@ } if (Rm != 0xF) { // Writeback - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } else Inst.addOperand(MCOperand::createReg(0)); } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(index)); @@ -5096,28 +5144,28 @@ break; } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; if (Rm != 0xF) { // Writeback - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else Inst.addOperand(MCOperand::createReg(0)); } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(index)); @@ -5164,23 +5212,23 @@ } if (Rm != 0xF) { // Writeback - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else Inst.addOperand(MCOperand::createReg(0)); } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(index)); @@ -5224,33 +5272,33 @@ break; } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) return MCDisassembler::Fail; if (Rm != 0xF) { // Writeback - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } else Inst.addOperand(MCOperand::createReg(0)); } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(index)); @@ -5295,25 +5343,25 @@ } if (Rm != 0xF) { // Writeback - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } else Inst.addOperand(MCOperand::createReg(0)); } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(index)); @@ -5364,37 +5412,37 @@ break; } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder))) return MCDisassembler::Fail; if (Rm != 0xF) { // Writeback - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else Inst.addOperand(MCOperand::createReg(0)); } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(index)); @@ -5446,27 +5494,27 @@ } if (Rm != 0xF) { // Writeback - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; } - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler::Fail; + if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } else Inst.addOperand(MCOperand::createReg(0)); } - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(index)); @@ -5485,13 +5533,13 @@ if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) + if (!Check(S, decodeSPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) + if (!Check(S, decodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -5511,13 +5559,13 @@ if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) + if (!Check(S, decodeSPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) + if (!Check(S, decodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -5576,13 +5624,13 @@ Check(S, MCDisassembler::SoftFail); // Rt - if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; // Rt2 - if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; // Writeback operand - if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; // addr if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) @@ -5611,13 +5659,13 @@ Check(S, MCDisassembler::SoftFail); // Writeback operand - if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; // Rt - if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; // Rt2 - if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; // addr if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) @@ -5633,7 +5681,7 @@ if (sign1 != sign2) return MCDisassembler::Fail; const unsigned Rd = fieldFromInstruction(Insn, 8, 4); assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); - DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); + DecodeStatus S = decoderGPRRegisterClass(Inst, Rd, Address, Decoder); unsigned Val = fieldFromInstruction(Insn, 0, 8); Val |= fieldFromInstruction(Insn, 12, 3) << 8; @@ -5678,11 +5726,11 @@ if (Rt == Rn || Rn == Rt2) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -5740,9 +5788,9 @@ if (!(imm & 0x20)) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(64 - imm)); @@ -5799,9 +5847,9 @@ if (!(imm & 0x20)) return MCDisassembler::Fail; - if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) + if (!Check(S, decodeQPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) + if (!Check(S, decodeQPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(64 - imm)); @@ -5823,7 +5871,7 @@ DecodeStatus S = MCDisassembler::Success; - auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; + auto DestRegDecoder = q ? decodeQPRRegisterClass : decodeDPRRegisterClass; if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail; @@ -5831,7 +5879,7 @@ return MCDisassembler::Fail; if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) + if (!Check(S, decodeDPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler::Fail; // The lane index does not have any bits in the encoding, because it can only // be 0. @@ -5854,9 +5902,9 @@ if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) S = MCDisassembler::SoftFail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; @@ -5895,17 +5943,17 @@ // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] if (Inst.getOpcode() == ARM::MRRC2) { - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; } Inst.addOperand(MCOperand::createImm(cop)); Inst.addOperand(MCOperand::createImm(opc1)); if (Inst.getOpcode() == ARM::MCRR2) { - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; } Inst.addOperand(MCOperand::createImm(CRm)); @@ -5937,9 +5985,9 @@ if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { if (Rt == 13 || Rt == 15) S = MCDisassembler::SoftFail; - Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)); } else - Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); + Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); } // Add explicit operand for the source sysreg, similarly to above. @@ -6032,10 +6080,10 @@ case ARM::MVE_WLSTP_64: Inst.addOperand(MCOperand::createReg(ARM::LR)); if (!Check(S, - DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), + decoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), Address, Decoder)) || !Check(S, DecodeBFLabelOperand( - Inst, Imm, Address, Decoder))) + Inst, Imm, Address, Decoder))) return MCDisassembler::Fail; break; case ARM::t2DLS: @@ -6057,7 +6105,7 @@ Inst.setOpcode(ARM::MVE_LCTP); } else { Inst.addOperand(MCOperand::createReg(ARM::LR)); - if (!Check(S, DecoderGPRRegisterClass(Inst, + if (!Check(S, decoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), Address, Decoder))) return MCDisassembler::Fail; @@ -6080,8 +6128,9 @@ return S; } -static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if ((RegNo) + 1 > 11) return MCDisassembler::Fail; @@ -6090,8 +6139,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if ((RegNo) > 14) return MCDisassembler::Fail; @@ -6101,7 +6151,7 @@ } static DecodeStatus -DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, +decodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo == 15) { Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); @@ -6143,9 +6193,9 @@ return S; } -static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; @@ -6159,7 +6209,7 @@ ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 }; -static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 6) @@ -6175,7 +6225,7 @@ ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 }; -static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 4) @@ -6373,7 +6423,7 @@ (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); if (Writeback) { - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; } if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) @@ -6396,7 +6446,7 @@ if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) return MCDisassembler::Fail; @@ -6409,17 +6459,15 @@ uint64_t Address, const void *Decoder) { return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, fieldFromInstruction(Val, 16, 3), - DecodetGPRRegisterClass, - DecodeTAddrModeImm7); + decodetGPRRegisterClass, DecodeTAddrModeImm7); } template static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, - fieldFromInstruction(Val, 16, 4), - DecoderGPRRegisterClass, - DecodeT2AddrModeImm7); + return DecodeMVE_MEM_pre( + Inst, Val, Address, Decoder, fieldFromInstruction(Val, 16, 4), + decoderGPRRegisterClass, DecodeT2AddrModeImm7); } template @@ -6427,8 +6475,7 @@ uint64_t Address, const void *Decoder) { return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, fieldFromInstruction(Val, 17, 3), - DecodeMQPRRegisterClass, - DecodeMveAddrModeQ); + decodeMQPRRegisterClass, DecodeMveAddrModeQ); } template @@ -6464,11 +6511,11 @@ fieldFromInstruction(Insn, 13, 3)); unsigned index = fieldFromInstruction(Insn, 4, 1); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) return MCDisassembler::Fail; @@ -6487,13 +6534,13 @@ fieldFromInstruction(Insn, 13, 3)); unsigned index = fieldFromInstruction(Insn, 4, 1); - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + if (!Check(S, decodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) return MCDisassembler::Fail; @@ -6533,15 +6580,15 @@ } // Rda as output parameter - if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rda, Address, Decoder))) return MCDisassembler::Fail; // Rda again as input parameter - if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rda, Address, Decoder))) return MCDisassembler::Fail; // Rm, the amount to shift by - if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; if (fieldFromInstruction (Insn, 6, 3) != 4) @@ -6557,19 +6604,19 @@ // put into Inst. Those all look the same: // RdaLo,RdaHi as output parameters - if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) + if (!Check(S, decodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) + if (!Check(S, decodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) return MCDisassembler::Fail; // RdaLo,RdaHi again as input parameters - if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) + if (!Check(S, decodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) + if (!Check(S, decodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) return MCDisassembler::Fail; // Rm, the amount to shift by - if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; if (Inst.getOpcode() == ARM::MVE_SQRSHRL || @@ -6591,9 +6638,9 @@ fieldFromInstruction(Insn, 1, 3)); unsigned imm6 = fieldFromInstruction(Insn, 16, 6); - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) return MCDisassembler::Fail; @@ -6607,7 +6654,7 @@ DecodeStatus S = MCDisassembler::Success; Inst.addOperand(MCOperand::createReg(ARM::VPR)); unsigned Qn = fieldFromInstruction(Insn, 17, 3); - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) return MCDisassembler::Fail; unsigned fc; @@ -6617,7 +6664,7 @@ fieldFromInstruction(Insn, 7, 1) | fieldFromInstruction(Insn, 5, 1) << 1; unsigned Rm = fieldFromInstruction(Insn, 0, 4); - if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) + if (!Check(S, decodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else { fc = fieldFromInstruction(Insn, 12, 1) << 2 | @@ -6625,7 +6672,7 @@ fieldFromInstruction(Insn, 0, 1) << 1; unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | fieldFromInstruction(Insn, 1, 3); - if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) return MCDisassembler::Fail; } @@ -6644,7 +6691,7 @@ DecodeStatus S = MCDisassembler::Success; Inst.addOperand(MCOperand::createReg(ARM::VPR)); unsigned Rn = fieldFromInstruction(Insn, 16, 4); - if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + if (!Check(S, decoderGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; return S; } @@ -6674,8 +6721,8 @@ // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) DecodeStatus DS = MCDisassembler::Success; if ((!Check(DS, - DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst - (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) + decodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst + (!Check(DS, decodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) return MCDisassembler::Fail; if (TypeT3) { Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp --- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp +++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp @@ -64,7 +64,7 @@ AVR::R28, AVR::R29, AVR::R30, AVR::R31, }; -static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -75,7 +75,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) @@ -86,7 +86,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { // Note: this function must be defined but does not seem to be called. @@ -133,7 +133,7 @@ addr |= fieldFromInstruction(Insn, 9, 2) << 4; unsigned reg = fieldFromInstruction(Insn, 4, 5); Inst.addOperand(MCOperand::createImm(addr)); - if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, reg, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; return MCDisassembler::Success; @@ -145,7 +145,7 @@ addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 9, 2) << 4; unsigned reg = fieldFromInstruction(Insn, 4, 5); - if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, reg, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(addr)); @@ -172,7 +172,7 @@ static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned d = fieldFromInstruction(Insn, 4, 5); - if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; return MCDisassembler::Success; @@ -190,10 +190,10 @@ uint64_t Address, const void *Decoder) { unsigned d = fieldFromInstruction(Insn, 4, 3) + 16; unsigned r = fieldFromInstruction(Insn, 0, 3) + 16; - if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; - if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, r, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; return MCDisassembler::Success; @@ -203,10 +203,10 @@ uint64_t Address, const void *Decoder) { unsigned r = fieldFromInstruction(Insn, 4, 4) * 2; unsigned d = fieldFromInstruction(Insn, 0, 4) * 2; - if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, r, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; - if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; return MCDisassembler::Success; @@ -218,10 +218,10 @@ unsigned k = 0; k |= fieldFromInstruction(Insn, 0, 4); k |= fieldFromInstruction(Insn, 6, 2) << 4; - if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; - if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(k)); @@ -232,10 +232,10 @@ uint64_t Address, const void *Decoder) { unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16; unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16; - if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, rd, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; - if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) == + if (decodeGPR8RegisterClass(Inst, rr, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; return MCDisassembler::Success; diff --git a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp --- a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp +++ b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp @@ -97,7 +97,7 @@ BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11}; -static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void * /*Decoder*/) { if (RegNo > 11) @@ -112,7 +112,7 @@ BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W10, BPF::W11}; -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void * /*Decoder*/) { if (RegNo > 11) diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -93,61 +93,59 @@ // Forward declare these because the auto-generated code will reference them. // Definitions are further down. -static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, +static DecodeStatus decodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus -DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, +decodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); - static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, @@ -532,7 +530,7 @@ return Result; } -static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef Table) { if (RegNo < Table.size()) { Inst.addOperand(MCOperand::createReg(Table[RegNo])); @@ -542,13 +540,13 @@ return MCDisassembler::Fail; } -static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); + return decodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { static const MCPhysReg IntRegDecoderTable[] = { @@ -560,10 +558,10 @@ Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, Hexagon::R30, Hexagon::R31}; - return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); + return decodeRegisterClass(Inst, RegNo, IntRegDecoderTable); } -static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, +static DecodeStatus decodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { @@ -574,10 +572,10 @@ Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, }; - return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); + return decodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); } -static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg HvxVRDecoderTable[] = { @@ -589,10 +587,10 @@ Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31}; - return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); + return decodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); } -static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg DoubleRegDecoderTable[] = { @@ -601,19 +599,19 @@ Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; - return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); + return decodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); } -static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( +static DecodeStatus decodeGeneralDoubleLow8RegsRegisterClass( MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; - return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); + return decodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); } -static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg HvxWRDecoderTable[] = { @@ -626,40 +624,39 @@ Hexagon::W15, Hexagon::WR15, }; - return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable); + return decodeRegisterClass(Inst, RegNo, HvxWRDecoderTable); } -LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. -static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. + static DecodeStatus + decodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg HvxVQRDecoderTable[] = { Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7}; - return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable); + return decodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable); } -static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3}; - return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); + return decodeRegisterClass(Inst, RegNo, PredRegDecoderTable); } -static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3}; - return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); + return decodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); } -static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { using namespace Hexagon; @@ -687,7 +684,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { using namespace Hexagon; @@ -715,7 +712,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { unsigned Register = 0; @@ -797,7 +794,7 @@ Hexagon::S78, Hexagon::S79, Hexagon::S80, }; -static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0])) @@ -824,7 +821,7 @@ Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78, }; -static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { RegNo = RegNo >> 1; @@ -839,7 +836,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { using namespace Hexagon; @@ -865,7 +862,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { using namespace Hexagon; diff --git a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp --- a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp +++ b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp @@ -43,7 +43,7 @@ // Forward declare because the autogenerated code will reference this. // Definition is further down. -static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -156,7 +156,7 @@ Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29, Lanai::R30, Lanai::R31}; -DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, +DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void * /*Decoder*/) { if (RegNo > 31) diff --git a/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp b/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp --- a/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp +++ b/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp @@ -70,7 +70,7 @@ MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B }; -static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo, +static DecodeStatus decodeGR8RegisterClass(MCInst &MI, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) @@ -88,7 +88,7 @@ MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 }; -static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo, +static DecodeStatus decodeGR16RegisterClass(MCInst &MI, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) @@ -131,10 +131,10 @@ unsigned Reg = Bits & 15; unsigned Imm = Bits >> 4; - if (DecodeGR16RegisterClass(MI, Reg, Address, Decoder) != + if (decodeGR16RegisterClass(MI, Reg, Address, Decoder) != MCDisassembler::Success) return MCDisassembler::Fail; - + MI.addOperand(MCOperand::createImm((int16_t)Imm)); return MCDisassembler::Success; } diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.td b/llvm/lib/Target/MSP430/MSP430InstrInfo.td --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.td +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.td @@ -31,7 +31,7 @@ def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>; def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, - SDTCisSameAs<1, 2>, + SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; def SDT_MSP430DAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, @@ -100,7 +100,7 @@ let PrintMethod = "printIndRegOperand"; let MIOperandInfo = (ops GR16); let ParserMatchClass = IndRegAsmOperand; - let DecoderMethod = "DecodeGR16RegisterClass"; + let DecoderMethod = "decodeGR16RegisterClass"; } def PostIndRegAsmOperand : AsmOperandClass { @@ -112,7 +112,7 @@ let PrintMethod = "printPostIndRegOperand"; let MIOperandInfo = (ops GR16); let ParserMatchClass = PostIndRegAsmOperand; - let DecoderMethod = "DecodeGR16RegisterClass"; + let DecoderMethod = "decodeGR16RegisterClass"; } // Short jump targets have OtherVT type and are printed as pcrel imm values. @@ -520,12 +520,12 @@ (implicit SR)]>; def 8mm : I8mm; def 16mm : I16mm; def 8mn : I8mn; def CMP16rm : I16rm<0b1001, (outs), (ins GR16:$rd, memsrc:$src), @@ -807,7 +807,7 @@ def CMP16mr : I16mr<0b1001, (outs), (ins memsrc:$dst, GR16:$rs), "cmp\t$rs, $dst", - [(MSP430cmp (load addr:$dst), GR16:$rs), + [(MSP430cmp (load addr:$dst), GR16:$rs), (implicit SR)]>; def CMP8mm : I8mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src), diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -79,127 +79,104 @@ // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, +static DecodeStatus decodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, - unsigned Insn, +static DecodeStatus decodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, - unsigned Insn, +static DecodeStatus decodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -587,16 +564,16 @@ DecodeFN RegDecoder = nullptr; if ((tmp & 0x18) == 0x00) { // INSVE_B NSize = 4; - RegDecoder = DecodeMSA128BRegisterClass; + RegDecoder = decodeMSA128BRegisterClass; } else if ((tmp & 0x1c) == 0x10) { // INSVE_H NSize = 3; - RegDecoder = DecodeMSA128HRegisterClass; + RegDecoder = decodeMSA128HRegisterClass; } else if ((tmp & 0x1e) == 0x18) { // INSVE_W NSize = 2; - RegDecoder = DecodeMSA128WRegisterClass; + RegDecoder = decodeMSA128WRegisterClass; } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D NSize = 1; - RegDecoder = DecodeMSA128DRegisterClass; + RegDecoder = decodeMSA128DRegisterClass; } else llvm_unreachable("Invalid encoding"); @@ -1384,15 +1361,13 @@ return MCDisassembler::Fail; } -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { return MCDisassembler::Fail; } -static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -1403,8 +1378,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) @@ -1414,8 +1388,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) @@ -1425,7 +1398,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, +static DecodeStatus decodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { @@ -1436,8 +1409,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -1447,25 +1419,22 @@ return MCDisassembler::Success; } -static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (static_cast(Decoder)->isGP64()) - return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); + return decodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); + return decodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); + return decodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -1476,8 +1445,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -1488,8 +1456,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -1499,8 +1466,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) @@ -1510,7 +1476,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -1751,8 +1717,8 @@ case Mips::LBU16_MM: case Mips::LHU16_MM: case Mips::LW16_MM: - if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler::Fail) + if (decodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) == + MCDisassembler::Fail) return MCDisassembler::Fail; break; case Mips::SB16_MM: @@ -1761,14 +1727,14 @@ case Mips::SH16_MMR6: case Mips::SW16_MM: case Mips::SW16_MMR6: - if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler::Fail) + if (decodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) == + MCDisassembler::Fail) return MCDisassembler::Fail; break; } - if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) - == MCDisassembler::Fail) + if (decodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) == + MCDisassembler::Fail) return MCDisassembler::Fail; switch (Inst.getOpcode()) { @@ -2056,8 +2022,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { // Currently only hardware register 29 is supported. @@ -2067,8 +2032,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 30 || RegNo %2) @@ -2079,8 +2043,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 4) @@ -2091,8 +2054,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 4) @@ -2103,8 +2065,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 4) @@ -2115,8 +2076,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -2127,8 +2087,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -2139,8 +2098,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -2151,8 +2109,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -2163,8 +2120,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) @@ -2175,8 +2131,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -2187,8 +2142,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -2478,12 +2432,12 @@ (fieldFromInstruction(Insn, 3, 1) << 2); else RegRs = fieldFromInstruction(Insn, 1, 3); - if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == + if (decodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; unsigned RegRt = fieldFromInstruction(Insn, 4, 3); - if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == + if (decodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1173,7 +1173,7 @@ def PtrRC : Operand { let MIOperandInfo = (ops ptr_rc); - let DecoderMethod = "DecodePtrRegisterClass"; + let DecoderMethod = "decodePtrRegisterClass"; let ParserMatchClass = GPR32AsmOperand; } diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -88,113 +88,113 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, CRRegs); } -static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { return decodeRegisterClass(Inst, RegNo, CRBITRegs); } -static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, FRegs); } -static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, FRegs); } -static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VFRegs); } -static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VRegs); } -static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VSRegs); } -static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VSFRegs); } -static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VSSRegs); } -static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, RRegs); } -static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { return decodeRegisterClass(Inst, RegNo, RRegsNoR0); } -static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, XRegs); } -static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, XRegs); } -static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { return decodeRegisterClass(Inst, RegNo, XRegsNoX0); } -#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass -#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass +#define decodePointerLikeRegClass0 decodeGPRCRegisterClass +#define decodePointerLikeRegClass1 decodeGPRC_NOR0RegisterClass -static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SPERegs); } -static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, ACCRegs); } -static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VSRpRegs); } -#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass -#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass +#define decodeQSRCRegisterClass decodeQFRCRegisterClass +#define decodeQBRCRegisterClass decodeQFRCRegisterClass template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -58,7 +58,7 @@ createRISCVDisassembler); } -static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { const FeatureBitset &FeatureBits = @@ -75,7 +75,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) @@ -86,7 +86,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) @@ -97,7 +97,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 8) { @@ -108,7 +108,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) @@ -119,7 +119,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 8) { @@ -130,27 +130,27 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo == 0) { return MCDisassembler::Fail; } - return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); + return decodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo == 2) { return MCDisassembler::Fail; } - return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); + return decodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 8) @@ -161,7 +161,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) @@ -172,7 +172,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) @@ -192,7 +192,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) @@ -212,7 +212,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) @@ -258,11 +258,11 @@ Inst.getOpcode() == RISCV::C_FLDSP || Inst.getOpcode() == RISCV::C_FSDSP || Inst.getOpcode() == RISCV::C_ADDI4SPN) { - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + decodeGPRRegisterClass(Inst, 2, Address, Decoder); } if (Inst.getOpcode() == RISCV::C_ADDI16SP) { - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + decodeGPRRegisterClass(Inst, 2, Address, Decoder); + decodeGPRRegisterClass(Inst, 2, Address, Decoder); } } @@ -369,7 +369,7 @@ static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + decodeGPRRegisterClass(Inst, 0, Address, Decoder); uint64_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); @@ -381,7 +381,7 @@ static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + decodeGPRRegisterClass(Inst, 0, Address, Decoder); Inst.addOperand(Inst.getOperand(0)); uint64_t UImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); @@ -395,8 +395,8 @@ uint64_t Address, const void *Decoder) { unsigned Rd = fieldFromInstruction(Insn, 7, 5); unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); - DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); - DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); + decodeGPRRegisterClass(Inst, Rd, Address, Decoder); + decodeGPRRegisterClass(Inst, Rs2, Address, Decoder); return MCDisassembler::Success; } @@ -405,9 +405,9 @@ const void *Decoder) { unsigned Rd = fieldFromInstruction(Insn, 7, 5); unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); - DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); + decodeGPRRegisterClass(Inst, Rd, Address, Decoder); Inst.addOperand(Inst.getOperand(0)); - DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); + decodeGPRRegisterClass(Inst, Rs2, Address, Decoder); return MCDisassembler::Success; } diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp --- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -142,8 +142,7 @@ SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31 }; -static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -153,8 +152,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -164,9 +162,7 @@ return MCDisassembler::Success; } - -static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -176,9 +172,7 @@ return MCDisassembler::Success; } - -static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -188,9 +182,7 @@ return MCDisassembler::Success; } - -static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -203,10 +195,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodeCPRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = CPRegDecoderTable[RegNo]; @@ -214,7 +205,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 3) @@ -223,7 +214,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) @@ -232,17 +223,18 @@ return MCDisassembler::Success; } -static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus decodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo >= array_lengthof(PRRegDecoderTable)) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); return MCDisassembler::Success; } -static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo > 31) @@ -256,8 +248,9 @@ return S; } -static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus decodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -390,7 +383,7 @@ } // Decode rs1. - status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler::Success) return status; @@ -398,7 +391,7 @@ if (isImm) MI.addOperand(MCOperand::createImm(simm13)); else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) return status; } @@ -417,85 +410,85 @@ static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeIntRegsRegisterClass); + decodeIntRegsRegisterClass); } static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeIntPairRegisterClass); + decodeIntPairRegisterClass); } static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeFPRegsRegisterClass); + decodeFPRegsRegisterClass); } static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeDFPRegsRegisterClass); + decodeDFPRegsRegisterClass); } static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeQFPRegsRegisterClass); + decodeQFPRegsRegisterClass); } static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeCPRegsRegisterClass); + decodeCPRegsRegisterClass); } static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeCPPairRegisterClass); + decodeCPPairRegisterClass); } static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeIntRegsRegisterClass); + decodeIntRegsRegisterClass); } static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeIntPairRegisterClass); + decodeIntPairRegisterClass); } static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeFPRegsRegisterClass); + decodeFPRegsRegisterClass); } static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeDFPRegsRegisterClass); + decodeDFPRegsRegisterClass); } static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeQFPRegsRegisterClass); + decodeQFPRegsRegisterClass); } static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeCPRegsRegisterClass); + decodeCPRegsRegisterClass); } static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeCPPairRegisterClass); + decodeCPPairRegisterClass); } static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, @@ -538,12 +531,12 @@ rs2 = fieldFromInstruction(insn, 0, 5); // Decode RD. - DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + DecodeStatus status = decodeIntRegsRegisterClass(MI, rd, Address, Decoder); if (status != MCDisassembler::Success) return status; // Decode RS1. - status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler::Success) return status; @@ -551,7 +544,7 @@ if (isImm) MI.addOperand(MCOperand::createImm(simm13)); else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) return status; } @@ -571,7 +564,7 @@ rs2 = fieldFromInstruction(insn, 0, 5); // Decode RS1. - DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + DecodeStatus status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler::Success) return status; @@ -579,7 +572,7 @@ if (isImm) MI.addOperand(MCOperand::createImm(simm13)); else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) return status; } @@ -602,12 +595,12 @@ rs2 = fieldFromInstruction(insn, 0, 5); // Decode RD. - DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + DecodeStatus status = decodeIntRegsRegisterClass(MI, rd, Address, Decoder); if (status != MCDisassembler::Success) return status; // Decode RS1. - status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler::Success) return status; @@ -615,7 +608,7 @@ if (isImm) MI.addOperand(MCOperand::createImm(simm13)); else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) return status; } @@ -640,7 +633,7 @@ rs2 = fieldFromInstruction(insn, 0, 5); // Decode RS1. - DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + DecodeStatus status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler::Success) return status; @@ -648,7 +641,7 @@ if (isImm) MI.addOperand(MCOperand::createImm(imm7)); else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) return status; } diff --git a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp --- a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -89,79 +89,79 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); } -static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); } -static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); } -static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16); } -static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); } -static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16); } -static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16); } -static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16); } -static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32); } -static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32); } -static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32); } -static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16); } -static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16); diff --git a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp --- a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp +++ b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp @@ -124,7 +124,7 @@ VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, VE::PMC12, VE::PMC13, VE::PMC14}; -static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeI32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 63) @@ -134,7 +134,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeI64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 63) @@ -144,7 +144,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeF32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 63) @@ -154,7 +154,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeF128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo % 2 || RegNo > 63) @@ -164,7 +164,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeV64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg = VE::NoRegister; @@ -178,7 +178,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeVMRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) @@ -188,7 +188,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeVM512RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo % 2 || RegNo > 15) @@ -198,7 +198,7 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus decodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 30) @@ -315,7 +315,7 @@ // Decode sz. if (cz) { - status = DecodeI64RegisterClass(MI, sz, Address, Decoder); + status = decodeI64RegisterClass(MI, sz, Address, Decoder); if (status != MCDisassembler::Success) return status; } else { @@ -324,7 +324,7 @@ // Decode sy. if (cy) { - status = DecodeI64RegisterClass(MI, sy, Address, Decoder); + status = decodeI64RegisterClass(MI, sy, Address, Decoder); if (status != MCDisassembler::Success) return status; } else { @@ -346,7 +346,7 @@ // Decode sz. if (cz) { - status = DecodeI64RegisterClass(MI, sz, Address, Decoder); + status = decodeI64RegisterClass(MI, sz, Address, Decoder); if (status != MCDisassembler::Success) return status; } else { @@ -409,44 +409,44 @@ static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { - return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); + return DecodeMem(Inst, insn, Address, Decoder, true, decodeI32RegisterClass); } static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { - return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); + return DecodeMem(Inst, insn, Address, Decoder, false, decodeI32RegisterClass); } static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { - return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); + return DecodeMem(Inst, insn, Address, Decoder, true, decodeI64RegisterClass); } static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { - return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); + return DecodeMem(Inst, insn, Address, Decoder, false, decodeI64RegisterClass); } static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { - return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); + return DecodeMem(Inst, insn, Address, Decoder, true, decodeF32RegisterClass); } static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { - return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); + return DecodeMem(Inst, insn, Address, Decoder, false, decodeF32RegisterClass); } static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { return DecodeMemAS(Inst, insn, Address, Decoder, true, - DecodeI64RegisterClass); + decodeI64RegisterClass); } static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { return DecodeMemAS(Inst, insn, Address, Decoder, false, - DecodeI64RegisterClass); + decodeI64RegisterClass); } static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address, @@ -490,30 +490,30 @@ static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address, const void *Decoder) { return DecodeCAS(MI, insn, Address, Decoder, false, true, - DecodeI64RegisterClass); + decodeI64RegisterClass); } static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address, const void *Decoder) { return DecodeCAS(MI, insn, Address, Decoder, false, true, - DecodeI32RegisterClass); + decodeI32RegisterClass); } static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address, const void *Decoder) { return DecodeCAS(MI, insn, Address, Decoder, false, false, - DecodeI64RegisterClass); + decodeI64RegisterClass); } static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address, const void *Decoder) { return DecodeCAS(MI, insn, Address, Decoder, false, false, - DecodeI32RegisterClass); + decodeI32RegisterClass); } static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, const void *Decoder) { - return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); + return DecodeMem(Inst, insn, Address, Decoder, true, decodeI64RegisterClass); } static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, @@ -594,7 +594,7 @@ // Decode sy. DecodeStatus status; if (cy) { - status = DecodeI64RegisterClass(MI, sy, Address, Decoder); + status = decodeI64RegisterClass(MI, sy, Address, Decoder); if (status != MCDisassembler::Success) return status; } else { diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp --- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -72,13 +72,11 @@ return *(RegInfo->getRegClass(RC).begin() + RegNo); } -static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -195,11 +193,9 @@ #include "XCoreGenDisassemblerTables.inc" -static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) -{ + const void *Decoder) { if (RegNo > 11) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); @@ -207,11 +203,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus decodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) -{ + const void *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); @@ -348,8 +342,8 @@ if (S != MCDisassembler::Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } @@ -362,7 +356,7 @@ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); Inst.addOperand(MCOperand::createImm(Op1)); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } @@ -374,8 +368,8 @@ if (S != MCDisassembler::Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } @@ -387,9 +381,9 @@ if (S != MCDisassembler::Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } @@ -401,7 +395,7 @@ if (S != MCDisassembler::Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); Inst.addOperand(MCOperand::createImm(Op2)); return S; } @@ -414,7 +408,7 @@ if (S != MCDisassembler::Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeBitpOperand(Inst, Op2, Address, Decoder); return S; } @@ -427,8 +421,8 @@ if (S != MCDisassembler::Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeBitpOperand(Inst, Op2, Address, Decoder); return S; } @@ -513,8 +507,8 @@ if (S != MCDisassembler::Success) return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } @@ -527,8 +521,8 @@ if (S != MCDisassembler::Success) return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return S; } @@ -538,9 +532,9 @@ unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } @@ -552,8 +546,8 @@ DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); if (S == MCDisassembler::Success) { Inst.addOperand(MCOperand::createImm(Op1)); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } @@ -564,8 +558,8 @@ unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); Inst.addOperand(MCOperand::createImm(Op3)); } return S; @@ -577,8 +571,8 @@ unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeBitpOperand(Inst, Op3, Address, Decoder); } return S; @@ -591,9 +585,9 @@ DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } @@ -605,10 +599,10 @@ DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } @@ -620,8 +614,8 @@ DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); Inst.addOperand(MCOperand::createImm(Op3)); } return S; @@ -634,8 +628,8 @@ DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeBitpOperand(Inst, Op3, Address, Decoder); } return S; @@ -652,12 +646,12 @@ S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); if (S != MCDisassembler::Success) return S; - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); return S; } @@ -687,11 +681,11 @@ if (S != MCDisassembler::Success) return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); return S; } @@ -703,13 +697,13 @@ DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); } if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } @@ -722,14 +716,14 @@ DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); } if (S == MCDisassembler::Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp --- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -1803,10 +1803,10 @@ Record = Record->getValueAsDef("RegClass"); if (Record->isSubClassOf("RegisterClass")) { - Decoder = "Decode" + Record->getName().str() + "RegisterClass"; + Decoder = "decode" + Record->getName().str() + "RegisterClass"; } else if (Record->isSubClassOf("PointerLikeRegClass")) { - Decoder = "DecodePointerLikeRegClass" + - utostr(Record->getValueAsInt("RegClassKind")); + Decoder = "decodePointerLikeRegClass" + + utostr(Record->getValueAsInt("RegClassKind")); } return Decoder; @@ -1976,10 +1976,10 @@ if (TypeRecord->isSubClassOf("RegisterOperand")) TypeRecord = TypeRecord->getValueAsDef("RegClass"); if (TypeRecord->isSubClassOf("RegisterClass")) { - Decoder = "Decode" + TypeRecord->getName().str() + "RegisterClass"; + Decoder = "decode" + TypeRecord->getName().str() + "RegisterClass"; isReg = true; } else if (TypeRecord->isSubClassOf("PointerLikeRegClass")) { - Decoder = "DecodePointerLikeRegClass" + + Decoder = "decodePointerLikeRegClass" + utostr(TypeRecord->getValueAsInt("RegClassKind")); isReg = true; }