diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10786,7 +10786,7 @@
         return LHS.getOperand(0);
     }
 
-    uint64_t CRHSVal = CRHS->getZExtValue();
+    const APInt &CRHSVal = CRHS->getAPIntValue();
     if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
         LHS.getOpcode() == ISD::SELECT &&
         isa<ConstantSDNode>(LHS.getOperand(1)) &&
@@ -10798,8 +10798,8 @@
       // setcc (select cc, CT, CF), CF, ne => cc
       // setcc (select cc, CT, CF), CT, ne => xor cc, -1
       // setcc (select cc, CT, CF), CT, eq => cc
-      uint64_t CT = LHS.getConstantOperandVal(1);
-      uint64_t CF = LHS.getConstantOperandVal(2);
+      const APInt &CT = LHS.getConstantOperandAPInt(1);
+      const APInt &CF = LHS.getConstantOperandAPInt(2);
 
       if ((CF == CRHSVal && CC == ISD::SETEQ) ||
           (CT == CRHSVal && CC == ISD::SETNE))
diff --git a/llvm/test/CodeGen/AMDGPU/setcc64.ll b/llvm/test/CodeGen/AMDGPU/setcc64.ll
--- a/llvm/test/CodeGen/AMDGPU/setcc64.ll
+++ b/llvm/test/CodeGen/AMDGPU/setcc64.ll
@@ -260,4 +260,28 @@
   ret void
 }
 
+; GCN-LABEL: {{^}}i128_sle:
+; GCN: v_cmp_le_u64
+; GCN: v_cmp_le_i64
+; SI: v_cmp_eq_u64
+; VI: s_cmp_eq_u64
+define amdgpu_kernel void @i128_sle(i32 addrspace(1)* %out, i128 %a, i128 %b) #0 {
+entry:
+  %tmp0 = icmp sle i128 %a, %b
+  %tmp1 = sext i1 %tmp0 to i32
+  store i32 %tmp1, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}i128_eq_const:
+; SI: v_cmp_eq_u64
+; VI: s_cmp_eq_u64
+define amdgpu_kernel void @i128_eq_const(i32 addrspace(1)* %out, i128 %a) #0 {
+entry:
+  %tmp0 = icmp eq i128 %a, 85070591730234615865843651857942052992
+  %tmp1 = sext i1 %tmp0 to i32
+  store i32 %tmp1, i32 addrspace(1)* %out
+  ret void
+}
+
 attributes #0 = { nounwind }