diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -126,6 +126,8 @@ StringRef CodeModel = getTargetOpts().CodeModel; unsigned FLen = ISAInfo->getFLen(); unsigned MinVLen = ISAInfo->getMinVLen(); + unsigned MaxELen = ISAInfo->getMaxELen(); + unsigned MaxELenFp = ISAInfo->getMaxELenFp(); if (CodeModel == "default") CodeModel = "small"; @@ -177,13 +179,16 @@ Builder.defineMacro("__riscv_fsqrt"); } - if (MinVLen) + if (MinVLen) { Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen)); + Builder.defineMacro("__riscv_v_elen", Twine(MaxELen)); + Builder.defineMacro("__riscv_v_elen_fp", Twine(MaxELenFp)); + } if (ISAInfo->hasExtension("c")) Builder.defineMacro("__riscv_compressed"); - if (ISAInfo->hasExtension("v")) + if (ISAInfo->hasExtension("zve32x")) Builder.defineMacro("__riscv_vector"); } diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -416,35 +416,35 @@ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v" -// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -### %s -c 2>&1 | \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s -// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izvlsseg' +// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32iv0p10_zvlsseg' // RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires '-menable-experimental-extensions' -// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -menable-experimental-extensions -### %s -c 2>&1 | \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s -// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32izvlsseg' +// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32iv0p10_zvlsseg' // RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit version number -// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s -// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32izvlsseg0p1' +// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32iv0p10_zvlsseg0p1' // RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension 'zvlsseg' -// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s // RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg" -// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -### %s -c 2>&1 | \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s -// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32izvl32b0p10' +// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32iv0p10_zvl32b0p10' // RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions' -// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s -// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32izvl32b0p1' +// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32iv0p10_zvl32b0p1' // RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension -// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s // RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -218,12 +218,6 @@ // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ // RUN: -march=rv64iv0p10 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s -// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izvlsseg0p10 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s -// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izvlsseg0p10 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s // CHECK-V-EXT: __riscv_v 10000 // CHECK-V-EXT: __riscv_vector 1 // CHECK-V-EXT: __riscv_zvlsseg 10000 @@ -247,6 +241,8 @@ // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ // RUN: -march=rv64iv0p10 -x c -E -dM %s -o - \ // RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s +// CHECK-V-MINVLEN: __riscv_v_elen 64 +// CHECK-V-MINVLEN: __riscv_v_elen_fp 64 // CHECK-V-MINVLEN: __riscv_v_min_vlen 128 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ @@ -293,3 +289,57 @@ // RUN: -march=rv64iv0p10_zvl65536b0p10 -x c -E -dM %s -o - \ // RUN: | FileCheck --check-prefix=CHECK-ZVL65536b %s // CHECK-ZVL65536b: __riscv_v_min_vlen 65536 + +// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64ifdzve64d0p10 -x c -E -dM %s -o - \ +// RUN: | FileCheck --check-prefix=CHECK-ZVE64D-EXT %s +// CHECK-ZVE64D-EXT: __riscv_v_elen 64 +// CHECK-ZVE64D-EXT: __riscv_v_elen_fp 64 +// CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64 +// CHECK-ZVE64D-EXT: __riscv_vector 1 +// CHECK-ZVE64D-EXT: __riscv_zve32f 10000 +// CHECK-ZVE64D-EXT: __riscv_zve32x 10000 +// CHECK-ZVE64D-EXT: __riscv_zve64d 10000 +// CHECK-ZVE64D-EXT: __riscv_zve64f 10000 +// CHECK-ZVE64D-EXT: __riscv_zve64x 10000 + +// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64ifzve64f0p10 -x c -E -dM %s -o - \ +// RUN: | FileCheck --check-prefix=CHECK-ZVE64F-EXT %s +// CHECK-ZVE64F-EXT: __riscv_v_elen 64 +// CHECK-ZVE64F-EXT: __riscv_v_elen_fp 32 +// CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64 +// CHECK-ZVE64F-EXT: __riscv_vector 1 +// CHECK-ZVE64F-EXT: __riscv_zve32f 10000 +// CHECK-ZVE64F-EXT: __riscv_zve32x 10000 +// CHECK-ZVE64F-EXT: __riscv_zve64f 10000 +// CHECK-ZVE64F-EXT: __riscv_zve64x 10000 + +// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64izve64x0p10 -x c -E -dM %s -o - \ +// RUN: | FileCheck --check-prefix=CHECK-ZVE64X-EXT %s +// CHECK-ZVE64X-EXT: __riscv_v_elen 64 +// CHECK-ZVE64X-EXT: __riscv_v_elen_fp 0 +// CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64 +// CHECK-ZVE64X-EXT: __riscv_vector 1 +// CHECK-ZVE64X-EXT: __riscv_zve32x 10000 +// CHECK-ZVE64X-EXT: __riscv_zve64x 10000 + +// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64ifzve32f0p10 -x c -E -dM %s -o - \ +// RUN: | FileCheck --check-prefix=CHECK-ZVE32F-EXT %s +// CHECK-ZVE32F-EXT: __riscv_v_elen 32 +// CHECK-ZVE32F-EXT: __riscv_v_elen_fp 32 +// CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32 +// CHECK-ZVE32F-EXT: __riscv_vector 1 +// CHECK-ZVE32F-EXT: __riscv_zve32f 10000 +// CHECK-ZVE32F-EXT: __riscv_zve32x 10000 + +// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64izve32x0p10 -x c -E -dM %s -o - \ +// RUN: | FileCheck --check-prefix=CHECK-ZVE32X-EXT %s +// CHECK-ZVE32X-EXT: __riscv_v_elen 32 +// CHECK-ZVE32X-EXT: __riscv_v_elen_fp 0 +// CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32 +// CHECK-ZVE32X-EXT: __riscv_vector 1 +// CHECK-ZVE32X-EXT: __riscv_zve32x 10000 diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h --- a/llvm/include/llvm/Support/RISCVISAInfo.h +++ b/llvm/include/llvm/Support/RISCVISAInfo.h @@ -62,6 +62,8 @@ unsigned getXLen() const { return XLen; }; unsigned getFLen() const { return FLen; }; unsigned getMinVLen() const { return MinVLen; } + unsigned getMaxELen() const { return MaxELen; } + unsigned getMaxELenFp() const { return MaxELenFp; } bool hasExtension(StringRef Ext) const; std::string toString() const; @@ -72,11 +74,13 @@ unsigned MinorVersion); private: - RISCVISAInfo(unsigned XLen) : XLen(XLen), FLen(0), MinVLen(0) {} + RISCVISAInfo(unsigned XLen) + : XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0) {} unsigned XLen; unsigned FLen; unsigned MinVLen; + unsigned MaxELen, MaxELenFp; OrderedExtensionMap Exts; @@ -88,6 +92,7 @@ void updateImplication(); void updateFLen(); void updateMinVLen(); + void updateMaxELen(); }; } // namespace llvm diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -79,6 +79,11 @@ {"zvl16384b", RISCVExtensionVersion{0, 10}}, {"zvl32768b", RISCVExtensionVersion{0, 10}}, {"zvl65536b", RISCVExtensionVersion{0, 10}}, + {"zve32x", RISCVExtensionVersion{0, 10}}, + {"zve32f", RISCVExtensionVersion{0, 10}}, + {"zve64x", RISCVExtensionVersion{0, 10}}, + {"zve64f", RISCVExtensionVersion{0, 10}}, + {"zve64d", RISCVExtensionVersion{0, 10}}, }; static bool stripExperimentalPrefix(StringRef &Ext) { @@ -297,7 +302,6 @@ continue; if (ExtName == "zvlsseg") { - Features.push_back("+experimental-v"); Features.push_back("+experimental-zvlsseg"); } else if (isExperimentalExtension(ExtName)) { Features.push_back(StrAlloc("+experimental-" + ExtName)); @@ -449,6 +453,7 @@ ISAInfo->updateImplication(); ISAInfo->updateFLen(); ISAInfo->updateMinVLen(); + ISAInfo->updateMaxELen(); if (Error Result = ISAInfo->checkDependency()) return std::move(Result); @@ -673,6 +678,7 @@ ISAInfo->updateImplication(); ISAInfo->updateFLen(); ISAInfo->updateMinVLen(); + ISAInfo->updateMaxELen(); if (Error Result = ISAInfo->checkDependency()) return std::move(Result); @@ -685,6 +691,11 @@ bool HasE = Exts.count("e") == 1; bool HasD = Exts.count("d") == 1; bool HasF = Exts.count("f") == 1; + bool HasZvlsseg = Exts.count("zvlsseg") == 1; + bool HasVector = Exts.count("zve32x") == 1; + bool HasZve32f = Exts.count("zve32f") == 1; + bool HasZve64d = Exts.count("zve64d") == 1; + bool HasZvl = MinVLen != 0; if (HasE && !IsRv32) return createStringError( @@ -699,6 +710,28 @@ return createStringError(errc::invalid_argument, "d requires f extension to also be specified"); + if (HasZvlsseg && !HasVector) + return createStringError( + errc::invalid_argument, + "zvlsseg requires v or zve* extension to also be specified"); + + // FIXME: Consider Zfinx in the future + if (HasZve32f && !HasF) + return createStringError( + errc::invalid_argument, + "zve32f requires f extension to also be specified"); + + // FIXME: Consider Zdinx in the future + if (HasZve64d && !HasD) + return createStringError( + errc::invalid_argument, + "zve64d requires d extension to also be specified"); + + if (HasZvl && !HasVector) + return createStringError( + errc::invalid_argument, + "zvl*b requires v or zve* extension to also be specified"); + // Additional dependency checks. // TODO: The 'q' extension requires rv64. // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. @@ -706,8 +739,13 @@ return Error::success(); } -static const char *ImpliedExtsV[] = {"zvlsseg", "zvl128b"}; +static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"}; static const char *ImpliedExtsZfh[] = {"zfhmin"}; +static const char *ImpliedExtsZve64d[] = {"zve64f"}; +static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; +static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"}; +static const char *ImpliedExtsZve32f[] = {"zve32x"}; +static const char *ImpliedExtsZve32x[] = {"zvlsseg", "zvl32b"}; static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"}; static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"}; static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"}; @@ -734,6 +772,11 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"v"}, {ImpliedExtsV}}, {{"zfh"}, {ImpliedExtsZfh}}, + {{"zve32f"}, {ImpliedExtsZve32f}}, + {{"zve32x"}, {ImpliedExtsZve32x}}, + {{"zve64d"}, {ImpliedExtsZve64d}}, + {{"zve64f"}, {ImpliedExtsZve64f}}, + {{"zve64x"}, {ImpliedExtsZve64x}}, {{"zvl1024b"}, {ImpliedExtsZvl1024b}}, {{"zvl128b"}, {ImpliedExtsZvl128b}}, {{"zvl16384b"}, {ImpliedExtsZvl16384b}}, @@ -804,6 +847,24 @@ } } +void RISCVISAInfo::updateMaxELen() { + // handles EEW restriction by sub-extension zve + for (auto Ext : Exts) { + StringRef ExtName = Ext.first; + bool IsZveExt = ExtName.consume_front("zve"); + if (IsZveExt) { + if (ExtName.back() == 'f') + MaxELenFp = std::max(MaxELenFp, 32u); + if (ExtName.back() == 'd') + MaxELenFp = std::max(MaxELenFp, 64u); + ExtName = ExtName.drop_back(); + unsigned ZveELen; + ExtName.getAsInteger(10, ZveELen); + MaxELen = std::max(MaxELen, ZveELen); + } + } +} + std::string RISCVISAInfo::toString() const { std::string Buffer; raw_string_ostream Arch(Buffer); diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -161,25 +161,73 @@ [!cast("FeatureStdExtZvl"#!srl(I, 1)#"b")]>; } -def FeatureStdExtV - : SubtargetFeature<"experimental-v", "HasStdExtV", "true", - "'V' (Vector Instructions)", - [FeatureStdExtZvl128b]>; -def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, - AssemblerPredicate<(all_of FeatureStdExtV), - "'V' (Vector Instructions)">; - -def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">; -def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">; - def FeatureStdExtZvlsseg : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true", "'Zvlsseg' (Vector segment load/store instructions)", - [FeatureStdExtV]>; + []>; def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">, AssemblerPredicate<(all_of FeatureStdExtZvlsseg), "'Zvlsseg' (Vector segment load/store instructions)">; +def FeatureStdExtZve32x + : SubtargetFeature<"experimental-zve32x", "HasStdExtZve32x", "true", + "'Zve32x' (Vector Extensions for Embedded Processors " + "with maximal 32 EEW)", + [FeatureStdExtZvlsseg, FeatureStdExtZvl32b]>; +def HasStdExtZve32x : Predicate<"SubTarget->hasStdExtZve32x()">, + AssemblerPredicate<(all_of FeatureStdExtZve32x), + "'Zve32x' (Vector Extensions for Embedded Processors " + "with maximal 32 EEW)">; + +def FeatureStdExtZve32f + : SubtargetFeature<"experimental-zve32f", "HasStdExtZve32f", "true", + "'Zve32f' (Vector Extensions for Embedded Processors " + "with maximal 32 EEW and F extension)", + [FeatureStdExtZve32x]>; +def HasStdExtZve32f : Predicate<"SubTarget->hasStdExtZve32f()">; + +def FeatureStdExtZve64x + : SubtargetFeature<"experimental-zve64x", "HasStdExtZve64x", "true", + "'Zve64x' (Vector Extensions for Embedded Processors " + "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>; +def HasStdExtZve64x : Predicate<"SubTarget->hasStdExtZve64x()">; + +def FeatureStdExtZve64f + : SubtargetFeature<"experimental-zve64f", "HasStdExtZve64f", "true", + "'Zve64f' (Vector Extensions for Embedded Processors " + "with maximal 64 EEW and F extension)", + [FeatureStdExtZve32f, FeatureStdExtZve64x]>; +def HasStdExtZve64f : Predicate<"SubTarget->hasStdExtZve64f()">; + +def FeatureStdExtZve64d + : SubtargetFeature<"experimental-zve64d", "HasStdExtZve64d", "true", + "'Zve64d' (Vector Extensions for Embedded Processors " + "with maximal 64 EEW, F and D extension)", + [FeatureStdExtZve64f]>; +def HasStdExtZve64d : Predicate<"SubTarget->hasStdExtZve64d()">; + +def FeatureStdExtV + : SubtargetFeature<"experimental-v", "HasStdExtV", "true", + "'V' (Vector Extension for Application Processors)", + [FeatureStdExtZvl128b, FeatureStdExtZve64d, FeatureStdExtF, FeatureStdExtD]>; +def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">; + +def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, + AssemblerPredicate< + (any_of FeatureStdExtZve32x), + "'V' (Vector Extension for Application Processors), 'Zve32x' or " + "'Zve64x' (Vector Extensions for Embedded Processors)">; +def HasVInstructionsI64 : Predicate<"Subtarget->hasStdExtZve64x()">, + AssemblerPredicate< + (any_of FeatureStdExtZve64x), + "'V' (Vector Extension for Application Processors) or 'Zve64x' " + "(Vector Extensions for Embedded Processors)">; +def HasVInstructionsAnyF : Predicate<"Subtarget->hasStdExtZve32f()">, + AssemblerPredicate< + (any_of FeatureStdExtZve32f), + "'V' (Vector Extension for Application Processors), 'Zve32f', " + "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">; + def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -349,6 +349,27 @@ // Combination of instruction classes. // Use these multiclasses to define instructions more easily. //===----------------------------------------------------------------------===// + +multiclass VIndexLoadStore EEWList> { + foreach n = EEWList in { + defvar w = !cast("LSWidth" # n); + + def VLUXEI # n # _V : + VIndexedLoad, + VLXSched; + def VLOXEI # n # _V : + VIndexedLoad, + VLXSched; + + def VSUXEI # n # _V : + VIndexedStore, + VSXSched; + def VSOXEI # n # _V : + VIndexedStore, + VSXSched; + } +} + multiclass VALU_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { def V : VALUVV, Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>; @@ -764,7 +785,7 @@ } multiclass VWholeLoadN nf, string opcodestr, RegisterClass VRC> { - foreach l = [8, 16, 32, 64] in { + foreach l = [8, 16, 32] in { defvar w = !cast("LSWidth" # l); defvar s = !cast("WriteVLD" # !add(nf, 1) # "R" # l); @@ -772,12 +793,16 @@ Sched<[s, ReadVLDX]>; } } +multiclass VWholeLoadEEW64 nf, string opcodestr, RegisterClass VRC, SchedReadWrite schedrw> { + def E64_V : VWholeLoad, + Sched<[schedrw, ReadVLDX]>; +} //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtV] in { +let Predicates = [HasVInstructions] in { let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp11:$vtypei), "vsetvli", "$rd, $rs1, $vtypei">; @@ -788,7 +813,7 @@ def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), "vsetvl", "$rd, $rs1, $rs2">; } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 -foreach eew = [8, 16, 32, 64] in { +foreach eew = [8, 16, 32] in { defvar w = !cast("LSWidth" # eew); // Vector Unit-Stride Instructions @@ -803,34 +828,10 @@ def VSSE#eew#_V : VStridedStore, VSSSched; } -foreach eew = [8, 16, 32] in { - defvar w = !cast("LSWidth" # eew); +defm "" : VIndexLoadStore<[8, 16, 32]>; +} // Predicates = [HasVInstructions] - // Vector Indexed Instructions - def VLUXEI#eew#_V : - VIndexedLoad, VLXSched; - def VLOXEI#eew#_V : - VIndexedLoad, VLXSched; - def VSUXEI#eew#_V : - VIndexedStore, VSXSched; - def VSOXEI#eew#_V : - VIndexedStore, VSXSched; -} -} // Predicates = [HasStdExtV] - -let Predicates = [HasStdExtV, IsRV64] in { - // Vector Indexed Instructions - def VLUXEI64_V : VIndexedLoad, - VLXSched<64, "U">; - def VLOXEI64_V : VIndexedLoad, - VLXSched<64, "O">; - def VSUXEI64_V : VIndexedStore, - VSXSched<64, "U">; - def VSOXEI64_V : VIndexedStore, - VSXSched<64, "O">; -} // Predicates = [HasStdExtV, IsRV64] - -let Predicates = [HasStdExtV] in { +let Predicates = [HasVInstructions] in { def VLM_V : VUnitStrideLoadMask<"vlm.v">, Sched<[WriteVLDM, ReadVLDX]>; def VSM_V : VUnitStrideStoreMask<"vsm.v">, @@ -845,11 +846,6 @@ defm VL4R : VWholeLoadN<3, "vl4r", VRM4>; defm VL8R : VWholeLoadN<7, "vl8r", VRM8>; -def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; -def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>; -def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>; -def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>; - def VS1R_V : VWholeStore<0, "vs1r.v", VR>, Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>; def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>, @@ -859,6 +855,40 @@ def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>, Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>; +def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; +def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>; +def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>; +def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>; +} // Predicates = [HasVInstructions] + +let Predicates = [HasVInstructionsI64] in { +// Vector Unit-Stride Instructions +def VLE64_V : VUnitStrideLoad, + VLESched<64>; + +def VLE64FF_V : VUnitStrideLoadFF, + VLFSched<64>; + +def VSE64_V : VUnitStrideStore, + VSESched<64>; +// Vector Strided Instructions +def VLSE64_V : VStridedLoad, + VLSSched<32>; + +def VSSE64_V : VStridedStore, + VSSSched<64>; + +defm VL1R: VWholeLoadEEW64<0, "vl1r", VR, WriteVLD1R64>; +defm VL2R: VWholeLoadEEW64<1, "vl2r", VRM2, WriteVLD2R64>; +defm VL4R: VWholeLoadEEW64<3, "vl4r", VRM4, WriteVLD4R64>; +defm VL8R: VWholeLoadEEW64<7, "vl8r", VRM8, WriteVLD8R64>; +} // Predicates = [HasVInstructionsI64] +let Predicates = [IsRV64, HasVInstructionsI64] in { + // Vector Indexed Instructions + defm "" : VIndexLoadStore<[64]>; +} // [IsRV64, HasVInstructionsI64] + +let Predicates = [HasVInstructions] in { // Vector Single-Width Integer Add and Subtract defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>; @@ -1090,9 +1120,9 @@ defm VNCLIPU_W : VNCLP_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">; defm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">; } // Constraints = "@earlyclobber $vd" -} // Predicates = [HasStdExtV] +} // Predicates = [HasVInstructions] -let Predicates = [HasStdExtV, HasStdExtF] in { +let Predicates = [HasVInstructionsAnyF] in { // Vector Single-Width Floating-Point Add/Subtract Instructions defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>; defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>; @@ -1227,9 +1257,9 @@ defm VFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>; defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>; } // Constraints = "@earlyclobber $vd" -} // Predicates = [HasStdExtV, HasStdExtF] +} // Predicates = HasVInstructionsAnyF] -let Predicates = [HasStdExtV] in { +let Predicates = [HasVInstructions] in { // Vector Single-Width Integer Reduction Instructions let RVVConstraint = NoConstraint in { @@ -1253,9 +1283,9 @@ defm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>; } // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint -} // Predicates = [HasStdExtV] +} // Predicates = [HasVInstructions] -let Predicates = [HasStdExtV, HasStdExtF] in { +let Predicates = [HasVInstructionsAnyF] in { // Vector Single-Width Floating-Point Reduction Instructions let RVVConstraint = NoConstraint in { defm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>; @@ -1279,9 +1309,9 @@ def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm", (VFWREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>; -} // Predicates = [HasStdExtV, HasStdExtF] +} // Predicates = [HasVInstructionsAnyF] -let Predicates = [HasStdExtV] in { +let Predicates = [HasVInstructions] in { // Vector Mask-Register Logical Instructions let RVVConstraint = NoConstraint in { defm VMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">; @@ -1362,9 +1392,9 @@ } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 -} // Predicates = [HasStdExtV] +} // Predicates = [HasVInstructions] -let Predicates = [HasStdExtV, HasStdExtF] in { +let Predicates = [HasVInstructionsAnyF] in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1, RVVConstraint = NoConstraint in { @@ -1379,9 +1409,9 @@ } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 -} // Predicates = [HasStdExtV, HasStdExtF] +} // Predicates = [HasVInstructionsAnyF] -let Predicates = [HasStdExtV] in { +let Predicates = [HasVInstructions] in { // Vector Slide Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, uimm5>; @@ -1389,16 +1419,16 @@ } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, uimm5>; defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>; -} // Predicates = [HasStdExtV] +} // Predicates = [HasVInstructions] -let Predicates = [HasStdExtV, HasStdExtF] in { +let Predicates = [HasVInstructionsAnyF] in { let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>; } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>; -} // Predicates = [HasStdExtV, HasStdExtF] +} // Predicates = [HasVInstructionsAnyF] -let Predicates = [HasStdExtV] in { +let Predicates = [HasVInstructions] in { // Vector Register Gather Instruction let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in { defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100, uimm5>; @@ -1429,11 +1459,11 @@ } } } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 -} // Predicates = [HasStdExtV] +} // Predicates = [HasVInstructions] let Predicates = [HasStdExtZvlsseg] in { foreach nf=2-8 in { - foreach eew = [8, 16, 32, 64] in { + foreach eew = [8, 16, 32] in { defvar w = !cast("LSWidth"#eew); def VLSEG#nf#E#eew#_V : @@ -1448,10 +1478,6 @@ VStridedSegmentLoad; def VSSSEG#nf#E#eew#_V : VStridedSegmentStore; - } - - foreach eew = [8, 16, 32] in { - defvar w = !cast("LSWidth"#eew); // Vector Indexed Instructions def VLUXSEG#nf#EI#eew#_V : @@ -1470,9 +1496,26 @@ } } // Predicates = [HasStdExtZvlsseg] -let Predicates = [HasStdExtZvlsseg, IsRV64] in { +let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] in { + foreach nf=2-8 in { + // Vector Unit-strided Segment Instructions + def VLSEG#nf#E64_V : + VUnitStrideSegmentLoad; + def VLSEG#nf#E64FF_V : + VUnitStrideSegmentLoadFF; + def VSSEG#nf#E64_V : + VUnitStrideSegmentStore; + + // Vector Strided Segment Instructions + def VLSSEG#nf#E64_V : + VStridedSegmentLoad; + def VSSSEG#nf#E64_V : + VStridedSegmentStore; + } +} // Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] +let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] in { foreach nf=2-8 in { - // Vector Indexed Instructions + // Vector Indexed Segment Instructions def VLUXSEG#nf#EI64_V : VIndexedSegmentLoad; @@ -1486,6 +1529,6 @@ VIndexedSegmentStore; } -} // Predicates = [HasStdExtZvlsseg, IsRV64] +} // Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] include "RISCVInstrInfoVPseudos.td" diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -17,7 +17,7 @@ let LoadLatency = 3; let MispredictPenalty = 3; let CompleteModel = false; - let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg]; + let UnsupportedFeatures = [HasStdExtV, HasVInstructions, HasVInstructionsI64, HasStdExtZvlsseg]; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -76,6 +76,11 @@ bool HasStdExtZbs = false; bool HasStdExtZbt = false; bool HasStdExtV = false; + bool HasStdExtZve32x = false; + bool HasStdExtZve32f = false; + bool HasStdExtZve64x = false; + bool HasStdExtZve64f = false; + bool HasStdExtZve64d = false; bool HasStdExtZvlsseg = false; bool HasStdExtZfhmin = false; bool HasStdExtZfh = false; @@ -150,6 +155,11 @@ bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZbt() const { return HasStdExtZbt; } bool hasStdExtV() const { return HasStdExtV; } + bool hasStdExtZve32x() const { return HasStdExtZve32x; } + bool hasStdExtZve32f() const { return HasStdExtZve32f; } + bool hasStdExtZve64x() const { return HasStdExtZve64x; } + bool hasStdExtZve64f() const { return HasStdExtZve64f; } + bool hasStdExtZve64d() const { return HasStdExtZve64d; } bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; } bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } @@ -177,11 +187,13 @@ } // Vector codegen related methods. - bool hasVInstructions() const { return HasStdExtV; } - bool hasVInstructionsI64() const { return HasStdExtV; } - bool hasVInstructionsF16() const { return HasStdExtV && hasStdExtZfh(); } - bool hasVInstructionsF32() const { return HasStdExtV && hasStdExtF(); } - bool hasVInstructionsF64() const { return HasStdExtV && hasStdExtD(); } + bool hasVInstructions() const { return HasStdExtZve32x; } + bool hasVInstructionsI64() const { return HasStdExtZve64x; } + bool hasVInstructionsF16() const { return HasStdExtZve32f && HasStdExtZfh; } + // FIXME: Consider Zfinx in the future + bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; } + // FIXME: Consider Zdinx in the future + bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; } // F16 and F64 both require F32. bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } unsigned getMaxInterleaveFactor() const { diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -57,8 +57,8 @@ ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" -; RV32V: .attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" -; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64A: .attribute 5, "rv64i2p0_a2p0" @@ -77,8 +77,8 @@ ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" -; RV64V: .attribute 5, "rv64i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" -; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32I -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64I -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zve64x -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32I +; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zve64x -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64I +; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zve64x -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zve64x -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32D ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64D ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32I -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64I -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zve64x -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32I +; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zve64x -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64I +; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zve64x -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zve64x -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV64 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV32,LMULMAX2-RV32D ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX2-RV64,LMULMAX2-RV64D ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX1-RV32 diff --git a/llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll b/llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll --- a/llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll +++ b/llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh,+m \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+zfh,+m \ ; RUN: -regalloc=fast -verify-machineinstrs < %s | FileCheck %s ; This test previously crashed with an error "ran out of registers during register allocation" diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vlseg2.nxv16i16(i16* , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vlseg2.nxv16i16(i16* , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vlsseg2.nxv16i16(i16*, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vlsseg2.nxv16i16(i16*, i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(,, i16*, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(,, i16*, , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsseg2.nxv16i16(,, i16* , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsseg2.nxv16i16(,, i16* , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vssseg2.nxv16i16(,, i16*, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vssseg2.nxv16i16(,, i16*, i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(,, i16*, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(,, i16*, , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll --- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve32x \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -36,7 +36,7 @@ ## Experimental extensions require version string to be explicitly specified .attribute arch, "rv32iv0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32izba1p0" # CHECK: attribute 5, "rv32i2p0_zba1p0" @@ -74,41 +74,56 @@ .attribute arch, "rv32ifzfh1p0" # CHECK: attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0" -.attribute arch, "rv32iv0p10_zvlsseg0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +.attribute arch, "rv32iv0p10zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl32b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl64b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl128b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl256b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl512b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl1024b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl2048b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl4096b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl8192b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl16384b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl32768b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" .attribute arch, "rv32iv0p10zvl65536b0p10" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10" + +.attribute arch, "rv32i_zve32x0p10" +# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10_zvlsseg0p10" + +.attribute arch, "rv32if_zve32f0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10_zvlsseg0p10" + +.attribute arch, "rv32i_zve64x0p10" +# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32if_zve64f0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32ifd_zve64d0p10" +# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" diff --git a/llvm/test/MC/RISCV/rvv/add.s b/llvm/test/MC/RISCV/rvv/add.s --- a/llvm/test/MC/RISCV/rvv/add.s +++ b/llvm/test/MC/RISCV/rvv/add.s @@ -11,353 +11,353 @@ vadd.vv v8, v4, v20, v0.t # CHECK-INST: vadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 00 vadd.vv v8, v4, v20 # CHECK-INST: vadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 02 vadd.vx v8, v4, a0, v0.t # CHECK-INST: vadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 00 vadd.vx v8, v4, a0 # CHECK-INST: vadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 02 vadd.vi v8, v4, 15, v0.t # CHECK-INST: vadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 00 vadd.vi v8, v4, 15 # CHECK-INST: vadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 02 vwaddu.vv v8, v4, v20, v0.t # CHECK-INST: vwaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a c0 vwaddu.vv v8, v4, v20 # CHECK-INST: vwaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a c2 vwaddu.vx v8, v4, a0, v0.t # CHECK-INST: vwaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 c0 vwaddu.vx v8, v4, a0 # CHECK-INST: vwaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 c2 vwadd.vv v8, v4, v20, v0.t # CHECK-INST: vwadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a c4 vwadd.vv v8, v4, v20 # CHECK-INST: vwadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a c6 vwadd.vx v8, v4, a0, v0.t # CHECK-INST: vwadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 c4 vwadd.vx v8, v4, a0 # CHECK-INST: vwadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 c6 vwaddu.wv v8, v4, v20, v0.t # CHECK-INST: vwaddu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a d0 vwaddu.wv v8, v4, v20 # CHECK-INST: vwaddu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xd2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a d2 vwaddu.wx v8, v4, a0, v0.t # CHECK-INST: vwaddu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 d0 vwaddu.wx v8, v4, a0 # CHECK-INST: vwaddu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xd2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 d2 vwadd.wv v8, v4, v20, v0.t # CHECK-INST: vwadd.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a d4 vwadd.wv v8, v4, v20 # CHECK-INST: vwadd.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xd6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a d6 vwadd.wx v8, v4, a0, v0.t # CHECK-INST: vwadd.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 d4 vwadd.wx v8, v4, a0 # CHECK-INST: vwadd.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xd6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 d6 vadc.vvm v8, v4, v20, v0 # CHECK-INST: vadc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 40 vadc.vvm v4, v4, v20, v0 # CHECK-INST: vadc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 02 4a 40 vadc.vvm v8, v4, v8, v0 # CHECK-INST: vadc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 44 40 vadc.vxm v8, v4, a0, v0 # CHECK-INST: vadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 40 vadc.vim v8, v4, 15, v0 # CHECK-INST: vadc.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 40 vmadc.vvm v8, v4, v20, v0 # CHECK-INST: vmadc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 44 vmadc.vvm v4, v4, v20, v0 # CHECK-INST: vmadc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 02 4a 44 vmadc.vvm v8, v4, v8, v0 # CHECK-INST: vmadc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 44 44 vmadc.vxm v8, v4, a0, v0 # CHECK-INST: vmadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 44 vmadc.vim v8, v4, 15, v0 # CHECK-INST: vmadc.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 44 vmadc.vv v8, v4, v20 # CHECK-INST: vmadc.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 46 vmadc.vx v8, v4, a0 # CHECK-INST: vmadc.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 46 vmadc.vi v8, v4, 15 # CHECK-INST: vmadc.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 46 vsaddu.vv v8, v4, v20, v0.t # CHECK-INST: vsaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 80 vsaddu.vv v8, v4, v20 # CHECK-INST: vsaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 82 vsaddu.vx v8, v4, a0, v0.t # CHECK-INST: vsaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 80 vsaddu.vx v8, v4, a0 # CHECK-INST: vsaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 82 vsaddu.vi v8, v4, 15, v0.t # CHECK-INST: vsaddu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 80 vsaddu.vi v8, v4, 15 # CHECK-INST: vsaddu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 82 vsadd.vv v8, v4, v20, v0.t # CHECK-INST: vsadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 84 vsadd.vv v8, v4, v20 # CHECK-INST: vsadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 86 vsadd.vx v8, v4, a0, v0.t # CHECK-INST: vsadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 84 vsadd.vx v8, v4, a0 # CHECK-INST: vsadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 86 vsadd.vi v8, v4, 15, v0.t # CHECK-INST: vsadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 84 vsadd.vi v8, v4, 15 # CHECK-INST: vsadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 86 vaadd.vv v8, v4, v20, v0.t # CHECK-INST: vaadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 24 vaadd.vv v8, v4, v20 # CHECK-INST: vaadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 26 vaadd.vx v8, v4, a0, v0.t # CHECK-INST: vaadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 24 vaadd.vx v8, v4, a0 # CHECK-INST: vaadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 26 vaaddu.vv v8, v4, v20, v0.t # CHECK-INST: vaaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x20] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 20 vaaddu.vv v8, v4, v20 # CHECK-INST: vaaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 22 vaaddu.vx v8, v4, a0, v0.t # CHECK-INST: vaaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x20] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 20 vaaddu.vx v8, v4, a0 # CHECK-INST: vaaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 22 vwcvt.x.x.v v8, v4, v0.t # CHECK-INST: vwcvt.x.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x40,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 40 c4 vwcvt.x.x.v v8, v4 # CHECK-INST: vwadd.vx v8, v4, zero # CHECK-ENCODING: [0x57,0x64,0x40,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 40 c6 vwcvtu.x.x.v v8, v4, v0.t # CHECK-INST: vwcvtu.x.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x40,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 40 c0 vwcvtu.x.x.v v8, v4 # CHECK-INST: vwaddu.vx v8, v4, zero # CHECK-ENCODING: [0x57,0x64,0x40,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 40 c2 diff --git a/llvm/test/MC/RISCV/rvv/and.s b/llvm/test/MC/RISCV/rvv/and.s --- a/llvm/test/MC/RISCV/rvv/and.s +++ b/llvm/test/MC/RISCV/rvv/and.s @@ -11,35 +11,35 @@ vand.vv v8, v4, v20, v0.t # CHECK-INST: vand.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 24 vand.vv v8, v4, v20 # CHECK-INST: vand.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 26 vand.vx v8, v4, a0, v0.t # CHECK-INST: vand.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 24 vand.vx v8, v4, a0 # CHECK-INST: vand.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 26 vand.vi v8, v4, 15, v0.t # CHECK-INST: vand.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 24 vand.vi v8, v4, 15 # CHECK-INST: vand.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 26 diff --git a/llvm/test/MC/RISCV/rvv/clip.s b/llvm/test/MC/RISCV/rvv/clip.s --- a/llvm/test/MC/RISCV/rvv/clip.s +++ b/llvm/test/MC/RISCV/rvv/clip.s @@ -11,71 +11,71 @@ vnclipu.wv v8, v4, v20, v0.t # CHECK-INST: vnclipu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a b8 vnclipu.wv v8, v4, v20 # CHECK-INST: vnclipu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xba] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a ba vnclipu.wx v8, v4, a0, v0.t # CHECK-INST: vnclipu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 b8 vnclipu.wx v8, v4, a0 # CHECK-INST: vnclipu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xba] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 ba vnclipu.wi v8, v4, 31, v0.t # CHECK-INST: vnclipu.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f b8 vnclipu.wi v8, v4, 31 # CHECK-INST: vnclipu.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xba] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f ba vnclip.wv v8, v4, v20, v0.t # CHECK-INST: vnclip.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a bc vnclip.wv v8, v4, v20 # CHECK-INST: vnclip.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a be vnclip.wx v8, v4, a0, v0.t # CHECK-INST: vnclip.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 bc vnclip.wx v8, v4, a0 # CHECK-INST: vnclip.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 be vnclip.wi v8, v4, 31, v0.t # CHECK-INST: vnclip.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f bc vnclip.wi v8, v4, 31 # CHECK-INST: vnclip.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f be diff --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s --- a/llvm/test/MC/RISCV/rvv/compare.s +++ b/llvm/test/MC/RISCV/rvv/compare.s @@ -11,367 +11,367 @@ vmslt.vv v0, v4, v20, v0.t # CHECK-INST: vmslt.vv v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x00,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 00 4a 6c vmseq.vv v8, v4, v20, v0.t # CHECK-INST: vmseq.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 60 vmseq.vv v8, v4, v20 # CHECK-INST: vmseq.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 62 vmseq.vx v8, v4, a0, v0.t # CHECK-INST: vmseq.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 60 vmseq.vx v8, v4, a0 # CHECK-INST: vmseq.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 62 vmseq.vi v8, v4, 15, v0.t # CHECK-INST: vmseq.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 60 vmseq.vi v8, v4, 15 # CHECK-INST: vmseq.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 62 vmsne.vv v8, v4, v20, v0.t # CHECK-INST: vmsne.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 64 vmsne.vv v8, v4, v20 # CHECK-INST: vmsne.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 66 vmsne.vx v8, v4, a0, v0.t # CHECK-INST: vmsne.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 64 vmsne.vx v8, v4, a0 # CHECK-INST: vmsne.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 66 vmsne.vi v8, v4, 15, v0.t # CHECK-INST: vmsne.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 64 vmsne.vi v8, v4, 15 # CHECK-INST: vmsne.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 66 vmsltu.vv v8, v4, v20, v0.t # CHECK-INST: vmsltu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x68] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 68 vmsltu.vv v8, v4, v20 # CHECK-INST: vmsltu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 6a vmsltu.vx v8, v4, a0, v0.t # CHECK-INST: vmsltu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x68] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 68 vmsltu.vx v8, v4, a0 # CHECK-INST: vmsltu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 6a vmslt.vv v8, v4, v20, v0.t # CHECK-INST: vmslt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 6c vmslt.vv v8, v4, v20 # CHECK-INST: vmslt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 6e vmslt.vx v8, v4, a0, v0.t # CHECK-INST: vmslt.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 6c vmslt.vx v8, v4, a0 # CHECK-INST: vmslt.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 6e vmsleu.vv v8, v4, v20, v0.t # CHECK-INST: vmsleu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 70 vmsleu.vv v8, v4, v20 # CHECK-INST: vmsleu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 72 vmsleu.vx v8, v4, a0, v0.t # CHECK-INST: vmsleu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 70 vmsleu.vx v8, v4, a0 # CHECK-INST: vmsleu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 72 vmsleu.vi v8, v4, 15, v0.t # CHECK-INST: vmsleu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 70 vmsleu.vi v8, v4, 15 # CHECK-INST: vmsleu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 72 vmsle.vv v8, v4, v20, v0.t # CHECK-INST: vmsle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 74 vmsle.vv v8, v4, v20 # CHECK-INST: vmsle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 76 vmsle.vx v8, v4, a0, v0.t # CHECK-INST: vmsle.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 74 vmsle.vx v8, v4, a0 # CHECK-INST: vmsle.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 76 vmsle.vi v8, v4, 15, v0.t # CHECK-INST: vmsle.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 74 vmsle.vi v8, v4, 15 # CHECK-INST: vmsle.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 76 vmsgtu.vx v8, v4, a0, v0.t # CHECK-INST: vmsgtu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x78] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 78 vmsgtu.vx v8, v4, a0 # CHECK-INST: vmsgtu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 7a vmsgtu.vi v8, v4, 15, v0.t # CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x78] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 78 vmsgtu.vi v8, v4, 15 # CHECK-INST: vmsgtu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 7a vmsgt.vx v8, v4, a0, v0.t # CHECK-INST: vmsgt.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x7c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 7c vmsgt.vx v8, v4, a0 # CHECK-INST: vmsgt.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 7e vmsgt.vi v8, v4, 15, v0.t # CHECK-INST: vmsgt.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 7c vmsgt.vi v8, v4, 15 # CHECK-INST: vmsgt.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 7e vmsgtu.vv v8, v20, v4, v0.t # CHECK-INST: vmsltu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x68] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 68 vmsgtu.vv v8, v20, v4 # CHECK-INST: vmsltu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 6a vmsgt.vv v8, v20, v4, v0.t # CHECK-INST: vmslt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 6c vmsgt.vv v8, v20, v4 # CHECK-INST: vmslt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 6e vmsgeu.vv v8, v20, v4, v0.t # CHECK-INST: vmsleu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 70 vmsgeu.vv v8, v20, v4 # CHECK-INST: vmsleu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 72 vmsge.vv v8, v20, v4, v0.t # CHECK-INST: vmsle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 74 vmsge.vv v8, v20, v4 # CHECK-INST: vmsle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 76 vmsltu.vi v8, v4, 16, v0.t # CHECK-INST: vmsleu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 70 vmsltu.vi v8, v4, 16 # CHECK-INST: vmsleu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 72 vmsltu.vi v8, v4, 0, v0.t # CHECK-INST: vmsne.vv v8, v4, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x42,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 42 64 vmsltu.vi v8, v4, 0 # CHECK-INST: vmsne.vv v8, v4, v4 # CHECK-ENCODING: [0x57,0x04,0x42,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 42 66 vmslt.vi v8, v4, 16, v0.t # CHECK-INST: vmsle.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 74 vmslt.vi v8, v4, 16 # CHECK-INST: vmsle.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 76 vmsgeu.vi v8, v4, 16, v0.t # CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x78] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 78 vmsgeu.vi v8, v4, 16 # CHECK-INST: vmsgtu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 7a vmsgeu.vi v8, v4, 0, v0.t # CHECK-INST: vmseq.vv v8, v4, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x42,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 42 60 vmsgeu.vi v8, v4, 0 # CHECK-INST: vmseq.vv v8, v4, v4 # CHECK-ENCODING: [0x57,0x04,0x42,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 42 62 vmsge.vi v8, v4, 16, v0.t # CHECK-INST: vmsgt.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 7c vmsge.vi v8, v4, 16 # CHECK-INST: vmsgt.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 7e vmsgeu.vx v8, v4, a0 @@ -379,7 +379,7 @@ # CHECK-INST: vmnot.m v8, v8 # CHECK-ENCODING: [0x57,0x44,0x45,0x6a] # CHECK-ENCODING: [0x57,0x24,0x84,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 6a # CHECK-UNKNOWN: 57 24 84 76 @@ -388,7 +388,7 @@ # CHECK-INST: vmnot.m v0, v0 # CHECK-ENCODING: [0x57,0x40,0x45,0x6e] # CHECK-ENCODING: [0x57,0x20,0x00,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 40 45 6e # CHECK-UNKNOWN: 57 20 00 76 @@ -397,7 +397,7 @@ # CHECK-INST: vmnot.m v8, v8 # CHECK-ENCODING: [0x57,0x44,0x45,0x6e] # CHECK-ENCODING: [0x57,0x24,0x84,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 6e # CHECK-UNKNOWN: 57 24 84 76 @@ -406,7 +406,7 @@ # CHECK-INST: vmxor.mm v8, v8, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x68] # CHECK-ENCODING: [0x57,0x24,0x80,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 68 # CHECK-UNKNOWN: 57 24 80 6e @@ -415,7 +415,7 @@ # CHECK-INST: vmxor.mm v8, v8, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6c] # CHECK-ENCODING: [0x57,0x24,0x80,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 6c # CHECK-UNKNOWN: 57 24 80 6e @@ -424,7 +424,7 @@ # CHECK-INST: vmandn.mm v0, v0, v2 # CHECK-ENCODING: [0x57,0x41,0x45,0x68] # CHECK-ENCODING: [0x57,0x20,0x01,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 41 45 68 # CHECK-UNKNOWN: 57 20 01 62 @@ -433,7 +433,7 @@ # CHECK-INST: vmandn.mm v0, v0, v2 # CHECK-ENCODING: [0x57,0x41,0x45,0x6c] # CHECK-ENCODING: [0x57,0x20,0x01,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 41 45 6c # CHECK-UNKNOWN: 57 20 01 62 @@ -446,7 +446,7 @@ # CHECK-ENCODING: [0x57,0x21,0x01,0x62] # CHECK-ENCODING: [0xd7,0x24,0x90,0x62] # CHECK-ENCODING: [0xd7,0xa4,0x24,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 41 45 6a # CHECK-UNKNOWN: 57 21 01 62 # CHECK-UNKNOWN: d7 24 90 62 @@ -461,8 +461,8 @@ # CHECK-ENCODING: [0x57,0x21,0x01,0x62] # CHECK-ENCODING: [0x57,0x24,0x80,0x62] # CHECK-ENCODING: [0x57,0x24,0x24,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 41 45 6e # CHECK-UNKNOWN: 57 21 01 62 # CHECK-UNKNOWN: 57 24 80 62 -# CHECK-UNKNOWN: 57 24 24 6a \ No newline at end of file +# CHECK-UNKNOWN: 57 24 24 6a diff --git a/llvm/test/MC/RISCV/rvv/convert.s b/llvm/test/MC/RISCV/rvv/convert.s --- a/llvm/test/MC/RISCV/rvv/convert.s +++ b/llvm/test/MC/RISCV/rvv/convert.s @@ -14,257 +14,257 @@ vfcvt.xu.f.v v8, v4, v0.t # CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x40,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 40 48 vfcvt.xu.f.v v8, v4 # CHECK-INST: vfcvt.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x40,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 40 4a vfcvt.x.f.v v8, v4, v0.t # CHECK-INST: vfcvt.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x40,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 40 48 vfcvt.x.f.v v8, v4 # CHECK-INST: vfcvt.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x40,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 40 4a vfcvt.f.xu.v v8, v4, v0.t # CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x41,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 41 48 vfcvt.f.xu.v v8, v4 # CHECK-INST: vfcvt.f.xu.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x41,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 41 4a vfcvt.f.x.v v8, v4, v0.t # CHECK-INST: vfcvt.f.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x41,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 41 48 vfcvt.f.x.v v8, v4 # CHECK-INST: vfcvt.f.x.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x41,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 41 4a vfcvt.rtz.xu.f.v v8, v4, v0.t # CHECK-INST: vfcvt.rtz.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x43,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 43 48 vfcvt.rtz.xu.f.v v8, v4 # CHECK-INST: vfcvt.rtz.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x43,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 43 4a vfcvt.rtz.x.f.v v8, v4, v0.t # CHECK-INST: vfcvt.rtz.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x43,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 43 48 vfcvt.rtz.x.f.v v8, v4 # CHECK-INST: vfcvt.rtz.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x43,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 43 4a vfwcvt.xu.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x44,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 44 48 vfwcvt.xu.f.v v8, v4 # CHECK-INST: vfwcvt.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x44,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 44 4a vfwcvt.x.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x44,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 44 48 vfwcvt.x.f.v v8, v4 # CHECK-INST: vfwcvt.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x44,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 44 4a vfwcvt.f.xu.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x45,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 45 48 vfwcvt.f.xu.v v8, v4 # CHECK-INST: vfwcvt.f.xu.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x45,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 45 4a vfwcvt.f.x.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x45,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 45 48 vfwcvt.f.x.v v8, v4 # CHECK-INST: vfwcvt.f.x.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x45,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 45 4a vfwcvt.f.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x46,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 46 48 vfwcvt.f.f.v v8, v4 # CHECK-INST: vfwcvt.f.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x46,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 46 4a vfwcvt.rtz.xu.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x47,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 47 48 vfwcvt.rtz.xu.f.v v8, v4 # CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x47,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 47 4a vfwcvt.rtz.x.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.rtz.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x47,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 47 48 vfwcvt.rtz.x.f.v v8, v4 # CHECK-INST: vfwcvt.rtz.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x47,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 47 4a vfncvt.xu.f.w v8, v4, v0.t # CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x48,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 48 48 vfncvt.xu.f.w v4, v4, v0.t # CHECK-INST: vfncvt.xu.f.w v4, v4, v0.t # CHECK-ENCODING: [0x57,0x12,0x48,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 12 48 48 vfncvt.xu.f.w v8, v4 # CHECK-INST: vfncvt.xu.f.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x48,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 48 4a vfncvt.x.f.w v8, v4, v0.t # CHECK-INST: vfncvt.x.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x48,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 48 48 vfncvt.x.f.w v8, v4 # CHECK-INST: vfncvt.x.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x48,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 48 4a vfncvt.f.xu.w v8, v4, v0.t # CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x49,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 49 48 vfncvt.f.xu.w v8, v4 # CHECK-INST: vfncvt.f.xu.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x49,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 49 4a vfncvt.f.x.w v8, v4, v0.t # CHECK-INST: vfncvt.f.x.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x49,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 49 48 vfncvt.f.x.w v8, v4 # CHECK-INST: vfncvt.f.x.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x49,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 49 4a vfncvt.f.f.w v8, v4, v0.t # CHECK-INST: vfncvt.f.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 48 vfncvt.f.f.w v8, v4 # CHECK-INST: vfncvt.f.f.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 4a vfncvt.rod.f.f.w v8, v4, v0.t # CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x4a,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 4a 48 vfncvt.rod.f.f.w v8, v4 # CHECK-INST: vfncvt.rod.f.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x4a,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 4a 4a vfncvt.rtz.xu.f.w v8, v4, v0.t # CHECK-INST: vfncvt.rtz.xu.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4b,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4b 48 vfncvt.rtz.xu.f.w v8, v4 # CHECK-INST: vfncvt.rtz.xu.f.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x4b,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4b 4a vfncvt.rtz.x.f.w v8, v4, v0.t # CHECK-INST: vfncvt.rtz.x.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x4b,0x48] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 4b 48 vfncvt.rtz.x.f.w v8, v4 # CHECK-INST: vfncvt.rtz.x.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x4b,0x4a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 4b 4a diff --git a/llvm/test/MC/RISCV/rvv/div.s b/llvm/test/MC/RISCV/rvv/div.s --- a/llvm/test/MC/RISCV/rvv/div.s +++ b/llvm/test/MC/RISCV/rvv/div.s @@ -11,95 +11,95 @@ vdivu.vv v8, v4, v20, v0.t # CHECK-INST: vdivu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 80 vdivu.vv v8, v4, v20 # CHECK-INST: vdivu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 82 vdivu.vx v8, v4, a0, v0.t # CHECK-INST: vdivu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 80 vdivu.vx v8, v4, a0 # CHECK-INST: vdivu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 82 vdiv.vv v8, v4, v20, v0.t # CHECK-INST: vdiv.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 84 vdiv.vv v8, v4, v20 # CHECK-INST: vdiv.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 86 vdiv.vx v8, v4, a0, v0.t # CHECK-INST: vdiv.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 84 vdiv.vx v8, v4, a0 # CHECK-INST: vdiv.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 86 vremu.vv v8, v4, v20, v0.t # CHECK-INST: vremu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 88 vremu.vv v8, v4, v20 # CHECK-INST: vremu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 8a vremu.vx v8, v4, a0, v0.t # CHECK-INST: vremu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 88 vremu.vx v8, v4, a0 # CHECK-INST: vremu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 8a vrem.vv v8, v4, v20, v0.t # CHECK-INST: vrem.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 8c vrem.vv v8, v4, v20 # CHECK-INST: vrem.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 8e vrem.vx v8, v4, a0, v0.t # CHECK-INST: vrem.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 8c vrem.vx v8, v4, a0 # CHECK-INST: vrem.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 8e diff --git a/llvm/test/MC/RISCV/rvv/ext.s b/llvm/test/MC/RISCV/rvv/ext.s --- a/llvm/test/MC/RISCV/rvv/ext.s +++ b/llvm/test/MC/RISCV/rvv/ext.s @@ -11,71 +11,71 @@ vzext.vf2 v8, v4, v0.t # CHECK-INST: vzext.vf2 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x43,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 43 48 vzext.vf2 v8, v4 # CHECK-INST: vzext.vf2 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x43,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 43 4a vsext.vf2 v8, v4, v0.t # CHECK-INST: vsext.vf2 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x43,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 43 48 vsext.vf2 v8, v4 # CHECK-INST: vsext.vf2 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x43,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 43 4a vzext.vf4 v8, v4, v0.t # CHECK-INST: vzext.vf4 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x42,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 42 48 vzext.vf4 v8, v4 # CHECK-INST: vzext.vf4 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 42 4a vsext.vf4 v8, v4, v0.t # CHECK-INST: vsext.vf4 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x42,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 42 48 vsext.vf4 v8, v4 # CHECK-INST: vsext.vf4 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x42,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 42 4a vzext.vf8 v8, v4, v0.t # CHECK-INST: vzext.vf8 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x41,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 41 48 vzext.vf8 v8, v4 # CHECK-INST: vzext.vf8 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x41,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 41 4a vsext.vf8 v8, v4, v0.t # CHECK-INST: vsext.vf8 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x41,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 41 48 vsext.vf8 v8, v4 # CHECK-INST: vsext.vf8 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x41,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 41 4a diff --git a/llvm/test/MC/RISCV/rvv/fadd.s b/llvm/test/MC/RISCV/rvv/fadd.s --- a/llvm/test/MC/RISCV/rvv/fadd.s +++ b/llvm/test/MC/RISCV/rvv/fadd.s @@ -14,71 +14,71 @@ vfadd.vv v8, v4, v20, v0.t # CHECK-INST: vfadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 00 vfadd.vv v8, v4, v20 # CHECK-INST: vfadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x02] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 02 vfadd.vf v8, v4, fa0, v0.t # CHECK-INST: vfadd.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x00] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 00 vfadd.vf v8, v4, fa0 # CHECK-INST: vfadd.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x02] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 02 vfwadd.vv v8, v4, v20, v0.t # CHECK-INST: vfwadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a c0 vfwadd.vv v8, v4, v20 # CHECK-INST: vfwadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xc2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a c2 vfwadd.vf v8, v4, fa0, v0.t # CHECK-INST: vfwadd.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xc0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 c0 vfwadd.vf v8, v4, fa0 # CHECK-INST: vfwadd.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xc2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 c2 vfwadd.wv v8, v4, v20, v0.t # CHECK-INST: vfwadd.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xd0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a d0 vfwadd.wv v8, v4, v20 # CHECK-INST: vfwadd.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xd2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a d2 vfwadd.wf v8, v4, fa0, v0.t # CHECK-INST: vfwadd.wf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xd0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 d0 vfwadd.wf v8, v4, fa0 # CHECK-INST: vfwadd.wf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xd2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 d2 diff --git a/llvm/test/MC/RISCV/rvv/fcompare.s b/llvm/test/MC/RISCV/rvv/fcompare.s --- a/llvm/test/MC/RISCV/rvv/fcompare.s +++ b/llvm/test/MC/RISCV/rvv/fcompare.s @@ -14,149 +14,149 @@ vmfeq.vv v8, v4, v20, v0.t # CHECK-INST: vmfeq.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x60] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 60 vmfeq.vv v8, v4, v20 # CHECK-INST: vmfeq.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x62] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 62 vmfeq.vf v8, v4, fa0, v0.t # CHECK-INST: vmfeq.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x60] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 60 vmfeq.vf v8, v4, fa0 # CHECK-INST: vmfeq.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x62] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 62 vmfne.vv v8, v4, v20, v0.t # CHECK-INST: vmfne.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x70] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 70 vmfne.vv v8, v4, v20 # CHECK-INST: vmfne.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 72 vmfne.vf v8, v4, fa0, v0.t # CHECK-INST: vmfne.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x70] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 70 vmfne.vf v8, v4, fa0 # CHECK-INST: vmfne.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x72] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 72 vmflt.vv v8, v4, v20, v0.t # CHECK-INST: vmflt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 6c vmflt.vv v8, v4, v20 # CHECK-INST: vmflt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 6e vmflt.vf v8, v4, fa0, v0.t # CHECK-INST: vmflt.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 6c vmflt.vf v8, v4, fa0 # CHECK-INST: vmflt.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 6e vmfle.vv v8, v4, v20, v0.t # CHECK-INST: vmfle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x64] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 64 vmfle.vv v8, v4, v20 # CHECK-INST: vmfle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 66 vmfle.vf v8, v4, fa0, v0.t # CHECK-INST: vmfle.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 64 vmfle.vf v8, v4, fa0 # CHECK-INST: vmfle.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 66 vmfgt.vf v8, v4, fa0, v0.t # CHECK-INST: vmfgt.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x74] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 74 vmfgt.vf v8, v4, fa0 # CHECK-INST: vmfgt.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x76] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 76 vmfge.vf v8, v4, fa0, v0.t # CHECK-INST: vmfge.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x7c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 7c vmfge.vf v8, v4, fa0 # CHECK-INST: vmfge.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x7e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 7e vmfgt.vv v8, v20, v4, v0.t # CHECK-INST: vmflt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 6c vmfgt.vv v8, v20, v4 # CHECK-INST: vmflt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 6e vmfge.vv v8, v20, v4, v0.t # CHECK-INST: vmfle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x64] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 64 vmfge.vv v8, v20, v4 # CHECK-INST: vmfle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 66 vmfeq.vv v0, v4, v20, v0.t # CHECK-INST: vmfeq.vv v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x10,0x4a,0x60] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 10 4a 60 diff --git a/llvm/test/MC/RISCV/rvv/fdiv.s b/llvm/test/MC/RISCV/rvv/fdiv.s --- a/llvm/test/MC/RISCV/rvv/fdiv.s +++ b/llvm/test/MC/RISCV/rvv/fdiv.s @@ -14,35 +14,35 @@ vfdiv.vv v8, v4, v20, v0.t # CHECK-INST: vfdiv.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x80] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 80 vfdiv.vv v8, v4, v20 # CHECK-INST: vfdiv.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x82] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 82 vfdiv.vf v8, v4, fa0, v0.t # CHECK-INST: vfdiv.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x80] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 80 vfdiv.vf v8, v4, fa0 # CHECK-INST: vfdiv.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x82] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 82 vfrdiv.vf v8, v4, fa0, v0.t # CHECK-INST: vfrdiv.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 84 vfrdiv.vf v8, v4, fa0 # CHECK-INST: vfrdiv.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 86 diff --git a/llvm/test/MC/RISCV/rvv/fmacc.s b/llvm/test/MC/RISCV/rvv/fmacc.s --- a/llvm/test/MC/RISCV/rvv/fmacc.s +++ b/llvm/test/MC/RISCV/rvv/fmacc.s @@ -14,287 +14,287 @@ vfmacc.vv v8, v20, v4, v0.t # CHECK-INST: vfmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a b0 vfmacc.vv v8, v20, v4 # CHECK-INST: vfmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xb2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a b2 vfmacc.vf v8, fa0, v4, v0.t # CHECK-INST: vfmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 b0 vfmacc.vf v8, fa0, v4 # CHECK-INST: vfmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xb2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 b2 vfnmacc.vv v8, v20, v4, v0.t # CHECK-INST: vfnmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb4] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a b4 vfnmacc.vv v8, v20, v4 # CHECK-INST: vfnmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xb6] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a b6 vfnmacc.vf v8, fa0, v4, v0.t # CHECK-INST: vfnmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb4] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 b4 vfnmacc.vf v8, fa0, v4 # CHECK-INST: vfnmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xb6] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 b6 vfmsac.vv v8, v20, v4, v0.t # CHECK-INST: vfmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a b8 vfmsac.vv v8, v20, v4 # CHECK-INST: vfmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xba] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a ba vfmsac.vf v8, fa0, v4, v0.t # CHECK-INST: vfmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 b8 vfmsac.vf v8, fa0, v4 # CHECK-INST: vfmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xba] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 ba vfnmsac.vv v8, v20, v4, v0.t # CHECK-INST: vfnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xbc] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a bc vfnmsac.vv v8, v20, v4 # CHECK-INST: vfnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xbe] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a be vfnmsac.vf v8, fa0, v4, v0.t # CHECK-INST: vfnmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xbc] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 bc vfnmsac.vf v8, fa0, v4 # CHECK-INST: vfnmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xbe] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 be vfmadd.vv v8, v20, v4, v0.t # CHECK-INST: vfmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a a0 vfmadd.vv v8, v20, v4 # CHECK-INST: vfmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xa2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a a2 vfmadd.vf v8, fa0, v4, v0.t # CHECK-INST: vfmadd.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 a0 vfmadd.vf v8, fa0, v4 # CHECK-INST: vfmadd.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xa2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 a2 vfnmadd.vv v8, v20, v4, v0.t # CHECK-INST: vfnmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa4] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a a4 vfnmadd.vv v8, v20, v4 # CHECK-INST: vfnmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xa6] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a a6 vfnmadd.vf v8, fa0, v4, v0.t # CHECK-INST: vfnmadd.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 a4 vfnmadd.vf v8, fa0, v4 # CHECK-INST: vfnmadd.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 a6 vfmsub.vv v8, v20, v4, v0.t # CHECK-INST: vfmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a a8 vfmsub.vv v8, v20, v4 # CHECK-INST: vfmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xaa] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a aa vfmsub.vf v8, fa0, v4, v0.t # CHECK-INST: vfmsub.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 a8 vfmsub.vf v8, fa0, v4 # CHECK-INST: vfmsub.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xaa] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 aa vfnmsub.vv v8, v20, v4, v0.t # CHECK-INST: vfnmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xac] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a ac vfnmsub.vv v8, v20, v4 # CHECK-INST: vfnmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xae] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a ae vfnmsub.vf v8, fa0, v4, v0.t # CHECK-INST: vfnmsub.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 ac vfnmsub.vf v8, fa0, v4 # CHECK-INST: vfnmsub.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 ae vfwmacc.vv v8, v20, v4, v0.t # CHECK-INST: vfwmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a f0 vfwmacc.vv v8, v20, v4 # CHECK-INST: vfwmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xf2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a f2 vfwmacc.vf v8, fa0, v4, v0.t # CHECK-INST: vfwmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 f0 vfwmacc.vf v8, fa0, v4 # CHECK-INST: vfwmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xf2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 f2 vfwnmacc.vv v8, v20, v4, v0.t # CHECK-INST: vfwnmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf4] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a f4 vfwnmacc.vv v8, v20, v4 # CHECK-INST: vfwnmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xf6] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a f6 vfwnmacc.vf v8, fa0, v4, v0.t # CHECK-INST: vfwnmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf4] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 f4 vfwnmacc.vf v8, fa0, v4 # CHECK-INST: vfwnmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xf6] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 f6 vfwmsac.vv v8, v20, v4, v0.t # CHECK-INST: vfwmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a f8 vfwmsac.vv v8, v20, v4 # CHECK-INST: vfwmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xfa] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a fa vfwmsac.vf v8, fa0, v4, v0.t # CHECK-INST: vfwmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 f8 vfwmsac.vf v8, fa0, v4 # CHECK-INST: vfwmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xfa] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 fa vfwnmsac.vv v8, v20, v4, v0.t # CHECK-INST: vfwnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xfc] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a fc vfwnmsac.vv v8, v20, v4 # CHECK-INST: vfwnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xfe] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a fe vfwnmsac.vf v8, fa0, v4, v0.t # CHECK-INST: vfwnmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xfc] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 fc vfwnmsac.vf v8, fa0, v4 # CHECK-INST: vfwnmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xfe] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 fe diff --git a/llvm/test/MC/RISCV/rvv/fminmax.s b/llvm/test/MC/RISCV/rvv/fminmax.s --- a/llvm/test/MC/RISCV/rvv/fminmax.s +++ b/llvm/test/MC/RISCV/rvv/fminmax.s @@ -14,47 +14,47 @@ vfmin.vv v8, v4, v20, v0.t # CHECK-INST: vfmin.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x10] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 10 vfmin.vv v8, v4, v20 # CHECK-INST: vfmin.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x12] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 12 vfmin.vf v8, v4, fa0, v0.t # CHECK-INST: vfmin.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x10] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 10 vfmin.vf v8, v4, fa0 # CHECK-INST: vfmin.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x12] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 12 vfmax.vv v8, v4, v20, v0.t # CHECK-INST: vfmax.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x18] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 18 vfmax.vv v8, v4, v20 # CHECK-INST: vfmax.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x1a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 1a vfmax.vf v8, v4, fa0, v0.t # CHECK-INST: vfmax.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x18] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 18 vfmax.vf v8, v4, fa0 # CHECK-INST: vfmax.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x1a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 1a diff --git a/llvm/test/MC/RISCV/rvv/fmul.s b/llvm/test/MC/RISCV/rvv/fmul.s --- a/llvm/test/MC/RISCV/rvv/fmul.s +++ b/llvm/test/MC/RISCV/rvv/fmul.s @@ -14,47 +14,47 @@ vfmul.vv v8, v4, v20, v0.t # CHECK-INST: vfmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x90] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 90 vfmul.vv v8, v4, v20 # CHECK-INST: vfmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x92] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 92 vfmul.vf v8, v4, fa0, v0.t # CHECK-INST: vfmul.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x90] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 90 vfmul.vf v8, v4, fa0 # CHECK-INST: vfmul.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x92] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 92 vfwmul.vv v8, v4, v20, v0.t # CHECK-INST: vfwmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xe0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a e0 vfwmul.vv v8, v4, v20 # CHECK-INST: vfwmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xe2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a e2 vfwmul.vf v8, v4, fa0, v0.t # CHECK-INST: vfwmul.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xe0] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 e0 vfwmul.vf v8, v4, fa0 # CHECK-INST: vfwmul.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xe2] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 e2 diff --git a/llvm/test/MC/RISCV/rvv/fmv.s b/llvm/test/MC/RISCV/rvv/fmv.s --- a/llvm/test/MC/RISCV/rvv/fmv.s +++ b/llvm/test/MC/RISCV/rvv/fmv.s @@ -14,17 +14,17 @@ vfmv.v.f v8, fa0 # CHECK-INST: vfmv.v.f v8, fa0 # CHECK-ENCODING: [0x57,0x54,0x05,0x5e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 05 5e vfmv.f.s fa0, v4 # CHECK-INST: vfmv.f.s fa0, v4 # CHECK-ENCODING: [0x57,0x15,0x40,0x42] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 15 40 42 vfmv.s.f v8, fa0 # CHECK-INST: vfmv.s.f v8, fa0 # CHECK-ENCODING: [0x57,0x54,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 05 42 diff --git a/llvm/test/MC/RISCV/rvv/fothers.s b/llvm/test/MC/RISCV/rvv/fothers.s --- a/llvm/test/MC/RISCV/rvv/fothers.s +++ b/llvm/test/MC/RISCV/rvv/fothers.s @@ -12,77 +12,77 @@ vfsqrt.v v8, v4, v0.t # CHECK-INST: vfsqrt.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x40,0x4c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 40 4c vfsqrt.v v8, v4 # CHECK-INST: vfsqrt.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x40,0x4e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 40 4e vfrsqrt7.v v8, v4, v0.t # CHECK-INST: vfrsqrt7.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x42,0x4c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 42 4c vfrsqrt7.v v8, v4 # CHECK-INST: vfrsqrt7.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x42,0x4e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 42 4e vfrec7.v v8, v4, v0.t # CHECK-INST: vfrec7.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x42,0x4c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 42 4c vfrec7.v v8, v4 # CHECK-INST: vfrec7.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x42,0x4e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 94 42 4e vfclass.v v8, v4, v0.t # CHECK-INST: vfclass.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x48,0x4c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 48 4c vfclass.v v8, v4 # CHECK-INST: vfclass.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x48,0x4e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 48 4e vfmerge.vfm v8, v4, fa0, v0 # CHECK-INST: vfmerge.vfm v8, v4, fa0, v0 # CHECK-ENCODING: [0x57,0x54,0x45,0x5c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 5c vfslide1up.vf v8, v4, fa0, v0.t # CHECK-INST: vfslide1up.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x38] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 38 vfslide1up.vf v8, v4, fa0 # CHECK-INST: vfslide1up.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x3a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 3a vfslide1down.vf v8, v4, fa0, v0.t # CHECK-INST: vfslide1down.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x3c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 3c vfslide1down.vf v8, v4, fa0 # CHECK-INST: vfslide1down.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x3e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 3e diff --git a/llvm/test/MC/RISCV/rvv/freduction.s b/llvm/test/MC/RISCV/rvv/freduction.s --- a/llvm/test/MC/RISCV/rvv/freduction.s +++ b/llvm/test/MC/RISCV/rvv/freduction.s @@ -14,77 +14,77 @@ vfredosum.vs v8, v4, v20, v0.t # CHECK-INST: vfredosum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x0c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 0c vfredosum.vs v8, v4, v20 # CHECK-INST: vfredosum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x0e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 0e vfredusum.vs v8, v4, v20, v0.t # CHECK-INST: vfredusum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x04] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 04 vfredusum.vs v8, v4, v20 # CHECK-INST: vfredusum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x06] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 06 vfredmax.vs v8, v4, v20, v0.t # CHECK-INST: vfredmax.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x1c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 1c vfredmax.vs v8, v4, v20 # CHECK-INST: vfredmax.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x1e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 1e vfredmin.vs v8, v4, v20, v0.t # CHECK-INST: vfredmin.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x14] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 14 vfredmin.vs v8, v4, v20 # CHECK-INST: vfredmin.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x16] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 16 vfwredosum.vs v8, v4, v20, v0.t # CHECK-INST: vfwredosum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xcc] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a cc vfwredosum.vs v8, v4, v20 # CHECK-INST: vfwredosum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xce] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a ce vfwredusum.vs v8, v4, v20, v0.t # CHECK-INST: vfwredusum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc4] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a c4 vfwredusum.vs v8, v4, v20 # CHECK-INST: vfwredusum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xc6] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a c6 vfredosum.vs v0, v4, v20, v0.t # CHECK-INST: vfredosum.vs v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x10,0x4a,0x0c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 10 4a 0c diff --git a/llvm/test/MC/RISCV/rvv/fsub.s b/llvm/test/MC/RISCV/rvv/fsub.s --- a/llvm/test/MC/RISCV/rvv/fsub.s +++ b/llvm/test/MC/RISCV/rvv/fsub.s @@ -14,83 +14,83 @@ vfsub.vv v8, v4, v20, v0.t # CHECK-INST: vfsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x08] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 08 vfsub.vv v8, v4, v20 # CHECK-INST: vfsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x0a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 0a vfsub.vf v8, v4, fa0, v0.t # CHECK-INST: vfsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x08] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 08 vfsub.vf v8, v4, fa0 # CHECK-INST: vfsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x0a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 0a vfrsub.vf v8, v4, fa0, v0.t # CHECK-INST: vfrsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 9c vfrsub.vf v8, v4, fa0 # CHECK-INST: vfrsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 9e vfwsub.vv v8, v4, v20, v0.t # CHECK-INST: vfwsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a c8 vfwsub.vv v8, v4, v20 # CHECK-INST: vfwsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xca] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a ca vfwsub.vf v8, v4, fa0, v0.t # CHECK-INST: vfwsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xc8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 c8 vfwsub.vf v8, v4, fa0 # CHECK-INST: vfwsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xca] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 ca vfwsub.wv v8, v4, v20, v0.t # CHECK-INST: vfwsub.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xd8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a d8 vfwsub.wv v8, v4, v20 # CHECK-INST: vfwsub.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xda] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a da vfwsub.wf v8, v4, fa0, v0.t # CHECK-INST: vfwsub.wf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xd8] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 d8 vfwsub.wf v8, v4, fa0 # CHECK-INST: vfwsub.wf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xda] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 da diff --git a/llvm/test/MC/RISCV/rvv/invalid-eew.s b/llvm/test/MC/RISCV/rvv/invalid-eew.s --- a/llvm/test/MC/RISCV/rvv/invalid-eew.s +++ b/llvm/test/MC/RISCV/rvv/invalid-eew.s @@ -1,195 +1,194 @@ -# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-v \ -# RUN: --mattr=+experimental-zvlsseg %s 2>&1 \ +# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-zve32x %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR vluxei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxei64.v v24, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxei64.v v24, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxei64.v v24, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxei64.v v24, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg2ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg2ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg3ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg3ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg4ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg4ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg5ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg5ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg6ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg6ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg7ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg7ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg8ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vluxseg8ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg2ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg2ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg3ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg3ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg4ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg4ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg5ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg5ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg6ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg6ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg7ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg7ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg8ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vloxseg8ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg2ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg2ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg3ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg3ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg4ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg4ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg5ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg5ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg6ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg6ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg7ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg7ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg8ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsuxseg8ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg2ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg2ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg3ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg3ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg4ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg4ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg5ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg5ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg6ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg6ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg7ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg7ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg8ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set vsoxseg8ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s --- a/llvm/test/MC/RISCV/rvv/load.s +++ b/llvm/test/MC/RISCV/rvv/load.s @@ -11,347 +11,347 @@ vlm.v v0, (a0) # CHECK-INST: vlm.v v0, (a0) # CHECK-ENCODING: [0x07,0x00,0xb5,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 00 b5 02 vlm.v v8, (a0) # CHECK-INST: vlm.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0xb5,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 b5 02 vle8.v v8, (a0), v0.t # CHECK-INST: vle8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 05 00 vle8.v v8, (a0) # CHECK-INST: vle8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 05 02 vle16.v v8, (a0), v0.t # CHECK-INST: vle16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 05 00 vle16.v v8, (a0) # CHECK-INST: vle16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 05 02 vle32.v v8, (a0), v0.t # CHECK-INST: vle32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 05 00 vle32.v v8, (a0) # CHECK-INST: vle32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 05 02 vle64.v v8, (a0), v0.t # CHECK-INST: vle64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 05 00 vle64.v v8, (a0) # CHECK-INST: vle64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 05 02 vle8ff.v v8, (a0), v0.t # CHECK-INST: vle8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 05 01 vle8ff.v v8, (a0) # CHECK-INST: vle8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x03] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 05 03 vle16ff.v v8, (a0), v0.t # CHECK-INST: vle16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 05 01 vle16ff.v v8, (a0) # CHECK-INST: vle16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x03] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 05 03 vle32ff.v v8, (a0), v0.t # CHECK-INST: vle32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 05 01 vle32ff.v v8, (a0) # CHECK-INST: vle32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x03] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 05 03 vle64ff.v v8, (a0), v0.t # CHECK-INST: vle64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 05 01 vle64ff.v v8, (a0) # CHECK-INST: vle64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x03] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 05 03 vlse8.v v8, (a0), a1, v0.t # CHECK-INST: vlse8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 b5 08 vlse8.v v8, (a0), a1 # CHECK-INST: vlse8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 b5 0a vlse16.v v8, (a0), a1, v0.t # CHECK-INST: vlse16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 b5 08 vlse16.v v8, (a0), a1 # CHECK-INST: vlse16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 b5 0a vlse32.v v8, (a0), a1, v0.t # CHECK-INST: vlse32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 b5 08 vlse32.v v8, (a0), a1 # CHECK-INST: vlse32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 b5 0a vlse64.v v8, (a0), a1, v0.t # CHECK-INST: vlse64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 b5 08 vlse64.v v8, (a0), a1 # CHECK-INST: vlse64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 b5 0a vluxei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 45 04 vluxei8.v v8, (a0), v4 # CHECK-INST: vluxei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 45 06 vluxei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 45 04 vluxei16.v v8, (a0), v4 # CHECK-INST: vluxei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 45 06 vluxei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 45 04 vluxei32.v v8, (a0), v4 # CHECK-INST: vluxei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 45 06 vluxei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 45 04 vluxei64.v v8, (a0), v4 # CHECK-INST: vluxei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 45 06 vloxei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 45 0c vloxei8.v v8, (a0), v4 # CHECK-INST: vloxei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 45 0e vloxei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 45 0c vloxei16.v v8, (a0), v4 # CHECK-INST: vloxei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 45 0e vloxei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 45 0c vloxei32.v v8, (a0), v4 # CHECK-INST: vloxei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 45 0e vloxei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 45 0c vloxei64.v v8, (a0), v4 # CHECK-INST: vloxei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 45 0e vl1re8.v v8, (a0) # CHECK-INST: vl1re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 85 02 vl1re16.v v8, (a0) # CHECK-INST: vl1re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 85 02 vl1re32.v v8, (a0) # CHECK-INST: vl1re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 85 02 vl1re64.v v8, (a0) # CHECK-INST: vl1re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 85 02 vl2re8.v v8, (a0) # CHECK-INST: vl2re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 85 22 vl2re16.v v8, (a0) # CHECK-INST: vl2re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 85 22 vl2re32.v v8, (a0) # CHECK-INST: vl2re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 85 22 vl2re64.v v8, (a0) # CHECK-INST: vl2re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 85 22 vl4re8.v v8, (a0) # CHECK-INST: vl4re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 85 62 vl4re16.v v8, (a0) # CHECK-INST: vl4re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 85 62 vl4re32.v v8, (a0) # CHECK-INST: vl4re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 85 62 vl4re64.v v8, (a0) # CHECK-INST: vl4re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 85 62 vl8re8.v v8, (a0) # CHECK-INST: vl8re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 04 85 e2 vl8re16.v v8, (a0) # CHECK-INST: vl8re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 54 85 e2 vl8re32.v v8, (a0) # CHECK-INST: vl8re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 64 85 e2 vl8re64.v v8, (a0) # CHECK-INST: vl8re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 07 74 85 e2 diff --git a/llvm/test/MC/RISCV/rvv/macc.s b/llvm/test/MC/RISCV/rvv/macc.s --- a/llvm/test/MC/RISCV/rvv/macc.s +++ b/llvm/test/MC/RISCV/rvv/macc.s @@ -11,179 +11,179 @@ vmacc.vv v8, v20, v4, v0.t # CHECK-INST: vmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a b4 vmacc.vv v8, v20, v4 # CHECK-INST: vmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a b6 vmacc.vx v8, a0, v4, v0.t # CHECK-INST: vmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 b4 vmacc.vx v8, a0, v4 # CHECK-INST: vmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 b6 vnmsac.vv v8, v20, v4, v0.t # CHECK-INST: vnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a bc vnmsac.vv v8, v20, v4 # CHECK-INST: vnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a be vnmsac.vx v8, a0, v4, v0.t # CHECK-INST: vnmsac.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 bc vnmsac.vx v8, a0, v4 # CHECK-INST: vnmsac.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 be vmadd.vv v8, v20, v4, v0.t # CHECK-INST: vmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a a4 vmadd.vv v8, v20, v4 # CHECK-INST: vmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a a6 vmadd.vx v8, a0, v4, v0.t # CHECK-INST: vmadd.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 a4 vmadd.vx v8, a0, v4 # CHECK-INST: vmadd.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 a6 vnmsub.vv v8, v20, v4, v0.t # CHECK-INST: vnmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a ac vnmsub.vv v8, v20, v4 # CHECK-INST: vnmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a ae vnmsub.vx v8, a0, v4, v0.t # CHECK-INST: vnmsub.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 ac vnmsub.vx v8, a0, v4 # CHECK-INST: vnmsub.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 ae vwmaccu.vv v8, v20, v4, v0.t # CHECK-INST: vwmaccu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a f0 vwmaccu.vv v8, v20, v4 # CHECK-INST: vwmaccu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xf2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a f2 vwmaccu.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 f0 vwmaccu.vx v8, a0, v4 # CHECK-INST: vwmaccu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xf2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 f2 vwmacc.vv v8, v20, v4, v0.t # CHECK-INST: vwmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a f4 vwmacc.vv v8, v20, v4 # CHECK-INST: vwmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xf6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a f6 vwmacc.vx v8, a0, v4, v0.t # CHECK-INST: vwmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 f4 vwmacc.vx v8, a0, v4 # CHECK-INST: vwmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xf6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 f6 vwmaccsu.vv v8, v20, v4, v0.t # CHECK-INST: vwmaccsu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xfc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a fc vwmaccsu.vv v8, v20, v4 # CHECK-INST: vwmaccsu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xfe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a fe vwmaccsu.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccsu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xfc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 fc vwmaccsu.vx v8, a0, v4 # CHECK-INST: vwmaccsu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xfe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 fe vwmaccus.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccus.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 f8 vwmaccus.vx v8, a0, v4 # CHECK-INST: vwmaccus.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xfa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 fa diff --git a/llvm/test/MC/RISCV/rvv/mask.s b/llvm/test/MC/RISCV/rvv/mask.s --- a/llvm/test/MC/RISCV/rvv/mask.s +++ b/llvm/test/MC/RISCV/rvv/mask.s @@ -11,155 +11,155 @@ vmand.mm v8, v4, v20 # CHECK-INST: vmand.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 66 vmnand.mm v8, v4, v20 # CHECK-INST: vmnand.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 76 vmandn.mm v8, v4, v20 # CHECK-INST: vmandn.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 62 vmxor.mm v8, v4, v20 # CHECK-INST: vmxor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 6e vmor.mm v8, v4, v20 # CHECK-INST: vmor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 6a vmnor.mm v8, v4, v20 # CHECK-INST: vmnor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 7a vmorn.mm v8, v4, v20 # CHECK-INST: vmorn.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 72 vmxnor.mm v8, v4, v20 # CHECK-INST: vmxnor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 7e vcpop.m a2, v4, v0.t # CHECK-INST: vcpop.m a2, v4, v0.t # CHECK-ENCODING: [0x57,0x26,0x48,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 26 48 40 vcpop.m a2, v4 # CHECK-INST: vcpop.m a2, v4 # CHECK-ENCODING: [0x57,0x26,0x48,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 26 48 42 vfirst.m a2, v4, v0.t # CHECK-INST: vfirst.m a2, v4, v0.t # CHECK-ENCODING: [0x57,0xa6,0x48,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a6 48 40 vfirst.m a2, v4 # CHECK-INST: vfirst.m a2, v4 # CHECK-ENCODING: [0x57,0xa6,0x48,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a6 48 42 vmsbf.m v8, v4, v0.t # CHECK-INST: vmsbf.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x40,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 40 50 vmsbf.m v8, v4 # CHECK-INST: vmsbf.m v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x40,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 40 52 vmsif.m v8, v4, v0.t # CHECK-INST: vmsif.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x41,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 41 50 vmsif.m v8, v4 # CHECK-INST: vmsif.m v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x41,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 41 52 vmsof.m v8, v4, v0.t # CHECK-INST: vmsof.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x41,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 41 50 vmsof.m v8, v4 # CHECK-INST: vmsof.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x41,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 41 52 viota.m v8, v4, v0.t # CHECK-INST: viota.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x48,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 48 50 viota.m v8, v4 # CHECK-INST: viota.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x48,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 48 52 vid.v v8, v0.t # CHECK-INST: vid.v v8, v0.t # CHECK-ENCODING: [0x57,0xa4,0x08,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 08 50 vid.v v8 # CHECK-INST: vid.v v8 # CHECK-ENCODING: [0x57,0xa4,0x08,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 a4 08 52 vmmv.m v8, v4 # CHECK-INST: vmmv.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 42 66 vmclr.m v8 # CHECK-INST: vmclr.m v8 # CHECK-ENCODING: [0x57,0x24,0x84,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 84 6e vmset.m v8 # CHECK-INST: vmset.m v8 # CHECK-ENCODING: [0x57,0x24,0x84,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 84 7e vmnot.m v8, v4 # CHECK-INST: vmnot.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 42 76 diff --git a/llvm/test/MC/RISCV/rvv/minmax.s b/llvm/test/MC/RISCV/rvv/minmax.s --- a/llvm/test/MC/RISCV/rvv/minmax.s +++ b/llvm/test/MC/RISCV/rvv/minmax.s @@ -11,95 +11,95 @@ vminu.vv v8, v4, v20, v0.t # CHECK-INST: vminu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 10 vminu.vv v8, v4, v20 # CHECK-INST: vminu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 12 vminu.vx v8, v4, a0, v0.t # CHECK-INST: vminu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 10 vminu.vx v8, v4, a0 # CHECK-INST: vminu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 12 vmin.vv v8, v4, v20, v0.t # CHECK-INST: vmin.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 14 vmin.vv v8, v4, v20 # CHECK-INST: vmin.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 16 vmin.vx v8, v4, a0, v0.t # CHECK-INST: vmin.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 14 vmin.vx v8, v4, a0 # CHECK-INST: vmin.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 16 vmaxu.vv v8, v4, v20, v0.t # CHECK-INST: vmaxu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 18 vmaxu.vv v8, v4, v20 # CHECK-INST: vmaxu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 1a vmaxu.vx v8, v4, a0, v0.t # CHECK-INST: vmaxu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 18 vmaxu.vx v8, v4, a0 # CHECK-INST: vmaxu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 1a vmax.vv v8, v4, v20, v0.t # CHECK-INST: vmax.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 1c vmax.vv v8, v4, v20 # CHECK-INST: vmax.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 1e vmax.vx v8, v4, a0, v0.t # CHECK-INST: vmax.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 1c vmax.vx v8, v4, a0 # CHECK-INST: vmax.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 1e diff --git a/llvm/test/MC/RISCV/rvv/mul.s b/llvm/test/MC/RISCV/rvv/mul.s --- a/llvm/test/MC/RISCV/rvv/mul.s +++ b/llvm/test/MC/RISCV/rvv/mul.s @@ -11,191 +11,191 @@ vmul.vv v8, v4, v20, v0.t # CHECK-INST: vmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 94 vmul.vv v8, v4, v20 # CHECK-INST: vmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 96 vmul.vx v8, v4, a0, v0.t # CHECK-INST: vmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 94 vmul.vx v8, v4, a0 # CHECK-INST: vmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 96 vmulh.vv v8, v4, v20, v0.t # CHECK-INST: vmulh.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 9c vmulh.vv v8, v4, v20 # CHECK-INST: vmulh.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 9e vmulh.vx v8, v4, a0, v0.t # CHECK-INST: vmulh.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 9c vmulh.vx v8, v4, a0 # CHECK-INST: vmulh.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 9e vmulhu.vv v8, v4, v20, v0.t # CHECK-INST: vmulhu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 90 vmulhu.vv v8, v4, v20 # CHECK-INST: vmulhu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 92 vmulhu.vx v8, v4, a0, v0.t # CHECK-INST: vmulhu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 90 vmulhu.vx v8, v4, a0 # CHECK-INST: vmulhu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 92 vmulhsu.vv v8, v4, v20, v0.t # CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 98 vmulhsu.vv v8, v4, v20 # CHECK-INST: vmulhsu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 9a vmulhsu.vx v8, v4, a0, v0.t # CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 98 vmulhsu.vx v8, v4, a0 # CHECK-INST: vmulhsu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 9a vwmul.vv v8, v4, v20, v0.t # CHECK-INST: vwmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xec] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a ec vwmul.vv v8, v4, v20 # CHECK-INST: vwmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xee] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a ee vwmul.vx v8, v4, a0, v0.t # CHECK-INST: vwmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 ec vwmul.vx v8, v4, a0 # CHECK-INST: vwmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 ee vwmulu.vv v8, v4, v20, v0.t # CHECK-INST: vwmulu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xe0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a e0 vwmulu.vv v8, v4, v20 # CHECK-INST: vwmulu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a e2 vwmulu.vx v8, v4, a0, v0.t # CHECK-INST: vwmulu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xe0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 e0 vwmulu.vx v8, v4, a0 # CHECK-INST: vwmulu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 e2 vwmulsu.vv v8, v4, v20, v0.t # CHECK-INST: vwmulsu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xe8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a e8 vwmulsu.vv v8, v4, v20 # CHECK-INST: vwmulsu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xea] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a ea vwmulsu.vx v8, v4, a0, v0.t # CHECK-INST: vwmulsu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xe8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 e8 vwmulsu.vx v8, v4, a0 # CHECK-INST: vwmulsu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xea] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 ea vsmul.vv v8, v4, v20, v0.t # CHECK-INST: vsmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 9c vsmul.vv v8, v4, v20 # CHECK-INST: vsmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 9e vsmul.vx v8, v4, a0, v0.t # CHECK-INST: vsmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 9c vsmul.vx v8, v4, a0 # CHECK-INST: vsmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 9e diff --git a/llvm/test/MC/RISCV/rvv/mv.s b/llvm/test/MC/RISCV/rvv/mv.s --- a/llvm/test/MC/RISCV/rvv/mv.s +++ b/llvm/test/MC/RISCV/rvv/mv.s @@ -11,53 +11,53 @@ vmv.v.v v8, v20 # CHECK-INST: vmv.v.v v8, v20 # CHECK-ENCODING: [0x57,0x04,0x0a,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 0a 5e vmv.v.x v8, a0 # CHECK-INST: vmv.v.x v8, a0 # CHECK-ENCODING: [0x57,0x44,0x05,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 05 5e vmv.v.i v8, 15 # CHECK-INST: vmv.v.i v8, 15 # CHECK-ENCODING: [0x57,0xb4,0x07,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 07 5e vmv.x.s a2, v4 # CHECK-INST: vmv.x.s a2, v4 # CHECK-ENCODING: [0x57,0x26,0x40,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 26 40 42 vmv.s.x v8, a0 # CHECK-INST: vmv.s.x v8, a0 # CHECK-ENCODING: [0x57,0x64,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 05 42 vmv1r.v v8, v4 # CHECK-INST: vmv1r.v v8, v4 # CHECK-ENCODING: [0x57,0x34,0x40,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 34 40 9e vmv2r.v v8, v4 # CHECK-INST: vmv2r.v v8, v4 # CHECK-ENCODING: [0x57,0xb4,0x40,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 40 9e vmv4r.v v8, v4 # CHECK-INST: vmv4r.v v8, v4 # CHECK-ENCODING: [0x57,0xb4,0x41,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 41 9e vmv8r.v v8, v24 # CHECK-INST: vmv8r.v v8, v24 # CHECK-ENCODING: [0x57,0xb4,0x83,0x9f] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 83 9f diff --git a/llvm/test/MC/RISCV/rvv/or.s b/llvm/test/MC/RISCV/rvv/or.s --- a/llvm/test/MC/RISCV/rvv/or.s +++ b/llvm/test/MC/RISCV/rvv/or.s @@ -11,35 +11,35 @@ vor.vv v8, v4, v20, v0.t # CHECK-INST: vor.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 28 vor.vv v8, v4, v20 # CHECK-INST: vor.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 2a vor.vx v8, v4, a0, v0.t # CHECK-INST: vor.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 28 vor.vx v8, v4, a0 # CHECK-INST: vor.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 2a vor.vi v8, v4, 15, v0.t # CHECK-INST: vor.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 28 vor.vi v8, v4, 15 # CHECK-INST: vor.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 2a diff --git a/llvm/test/MC/RISCV/rvv/others.s b/llvm/test/MC/RISCV/rvv/others.s --- a/llvm/test/MC/RISCV/rvv/others.s +++ b/llvm/test/MC/RISCV/rvv/others.s @@ -11,143 +11,143 @@ vmerge.vvm v8, v4, v20, v0 # CHECK-INST: vmerge.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 5c vmerge.vxm v8, v4, a0, v0 # CHECK-INST: vmerge.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 5c vmerge.vim v8, v4, 15, v0 # CHECK-INST: vmerge.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 5c vslideup.vx v8, v4, a0, v0.t # CHECK-INST: vslideup.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 38 vslideup.vx v8, v4, a0 # CHECK-INST: vslideup.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 3a vslideup.vi v8, v4, 31, v0.t # CHECK-INST: vslideup.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 38 vslideup.vi v8, v4, 31 # CHECK-INST: vslideup.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 3a vslidedown.vx v8, v4, a0, v0.t # CHECK-INST: vslidedown.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 3c vslidedown.vx v8, v4, a0 # CHECK-INST: vslidedown.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 3e vslidedown.vi v8, v4, 31, v0.t # CHECK-INST: vslidedown.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 3c vslidedown.vi v8, v4, 31 # CHECK-INST: vslidedown.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 3e vslide1up.vx v8, v4, a0, v0.t # CHECK-INST: vslide1up.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 38 vslide1up.vx v8, v4, a0 # CHECK-INST: vslide1up.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 3a vslide1down.vx v8, v4, a0, v0.t # CHECK-INST: vslide1down.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 3c vslide1down.vx v8, v4, a0 # CHECK-INST: vslide1down.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 3e vrgather.vv v8, v4, v20, v0.t # CHECK-INST: vrgather.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 30 vrgather.vv v8, v4, v20 # CHECK-INST: vrgather.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 32 vrgather.vx v8, v4, a0, v0.t # CHECK-INST: vrgather.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 30 vrgather.vx v8, v4, a0 # CHECK-INST: vrgather.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 32 vrgather.vi v8, v4, 31, v0.t # CHECK-INST: vrgather.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 30 vrgather.vi v8, v4, 31 # CHECK-INST: vrgather.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 32 vrgatherei16.vv v8, v4, v20, v0.t # CHECK-INST: vrgatherei16.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 38 vrgatherei16.vv v8, v4, v20 # CHECK-INST: vrgatherei16.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 3a vcompress.vm v8, v4, v20 # CHECK-INST: vcompress.vm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 5e diff --git a/llvm/test/MC/RISCV/rvv/reduction.s b/llvm/test/MC/RISCV/rvv/reduction.s --- a/llvm/test/MC/RISCV/rvv/reduction.s +++ b/llvm/test/MC/RISCV/rvv/reduction.s @@ -11,125 +11,125 @@ vredsum.vs v8, v4, v20, v0.t # CHECK-INST: vredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 00 vredsum.vs v8, v4, v20 # CHECK-INST: vredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 02 vredmaxu.vs v8, v4, v20, v0.t # CHECK-INST: vredmaxu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 18 vredmaxu.vs v8, v4, v20 # CHECK-INST: vredmaxu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 1a vredmax.vs v8, v4, v20, v0.t # CHECK-INST: vredmax.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 1c vredmax.vs v8, v4, v20 # CHECK-INST: vredmax.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 1e vredminu.vs v8, v4, v20, v0.t # CHECK-INST: vredminu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 10 vredminu.vs v8, v4, v20 # CHECK-INST: vredminu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 12 vredmin.vs v8, v4, v20, v0.t # CHECK-INST: vredmin.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 14 vredmin.vs v8, v4, v20 # CHECK-INST: vredmin.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 16 vredand.vs v8, v4, v20, v0.t # CHECK-INST: vredand.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 04 vredand.vs v8, v4, v20 # CHECK-INST: vredand.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 06 vredor.vs v8, v4, v20, v0.t # CHECK-INST: vredor.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 08 vredor.vs v8, v4, v20 # CHECK-INST: vredor.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 0a vredxor.vs v8, v4, v20, v0.t # CHECK-INST: vredxor.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 0c vredxor.vs v8, v4, v20 # CHECK-INST: vredxor.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 0e vwredsumu.vs v8, v4, v20, v0.t # CHECK-INST: vwredsumu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a c0 vwredsumu.vs v8, v4, v20 # CHECK-INST: vwredsumu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a c2 vwredsum.vs v8, v4, v20, v0.t # CHECK-INST: vwredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a c4 vwredsum.vs v8, v4, v20 # CHECK-INST: vwredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a c6 vredsum.vs v0, v4, v20, v0.t # CHECK-INST: vredsum.vs v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x20,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 20 4a 00 diff --git a/llvm/test/MC/RISCV/rvv/shift.s b/llvm/test/MC/RISCV/rvv/shift.s --- a/llvm/test/MC/RISCV/rvv/shift.s +++ b/llvm/test/MC/RISCV/rvv/shift.s @@ -11,257 +11,257 @@ vsll.vv v8, v4, v20, v0.t # CHECK-INST: vsll.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 94 vsll.vv v8, v4, v20 # CHECK-INST: vsll.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 96 vsll.vx v8, v4, a0, v0.t # CHECK-INST: vsll.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 94 vsll.vx v8, v4, a0 # CHECK-INST: vsll.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 96 vsll.vi v8, v4, 31, v0.t # CHECK-INST: vsll.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 94 vsll.vi v8, v4, 31 # CHECK-INST: vsll.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 96 vsrl.vv v8, v4, v20, v0.t # CHECK-INST: vsrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a a0 vsrl.vv v8, v4, v20 # CHECK-INST: vsrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a a2 vsrl.vx v8, v4, a0, v0.t # CHECK-INST: vsrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 a0 vsrl.vx v8, v4, a0 # CHECK-INST: vsrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 a2 vsrl.vi v8, v4, 31, v0.t # CHECK-INST: vsrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f a0 vsrl.vi v8, v4, 31 # CHECK-INST: vsrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f a2 vsra.vv v8, v4, v20, v0.t # CHECK-INST: vsra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a a4 vsra.vv v8, v4, v20 # CHECK-INST: vsra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a a6 vsra.vx v8, v4, a0, v0.t # CHECK-INST: vsra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 a4 vsra.vx v8, v4, a0 # CHECK-INST: vsra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 a6 vsra.vi v8, v4, 31, v0.t # CHECK-INST: vsra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f a4 vsra.vi v8, v4, 31 # CHECK-INST: vsra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f a6 vnsrl.wv v8, v4, v20, v0.t # CHECK-INST: vnsrl.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a b0 vnsrl.wv v4, v4, v20, v0.t # CHECK-INST: vnsrl.wv v4, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x02,0x4a,0xb0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 02 4a b0 vnsrl.wv v8, v4, v20 # CHECK-INST: vnsrl.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a b2 vnsrl.wx v8, v4, a0, v0.t # CHECK-INST: vnsrl.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 b0 vnsrl.wx v8, v4, a0 # CHECK-INST: vnsrl.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xb2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 b2 vnsrl.wi v8, v4, 31, v0.t # CHECK-INST: vnsrl.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f b0 vnsrl.wi v8, v4, 31 # CHECK-INST: vnsrl.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f b2 vnsra.wv v8, v4, v20, v0.t # CHECK-INST: vnsra.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a b4 vnsra.wv v8, v4, v20 # CHECK-INST: vnsra.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a b6 vnsra.wx v8, v4, a0, v0.t # CHECK-INST: vnsra.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 b4 vnsra.wx v8, v4, a0 # CHECK-INST: vnsra.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 b6 vnsra.wi v8, v4, 31, v0.t # CHECK-INST: vnsra.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f b4 vnsra.wi v8, v4, 31 # CHECK-INST: vnsra.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f b6 vssrl.vv v8, v4, v20, v0.t # CHECK-INST: vssrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a a8 vssrl.vv v8, v4, v20 # CHECK-INST: vssrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a aa vssrl.vx v8, v4, a0, v0.t # CHECK-INST: vssrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 a8 vssrl.vx v8, v4, a0 # CHECK-INST: vssrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 aa vssrl.vi v8, v4, 31, v0.t # CHECK-INST: vssrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f a8 vssrl.vi v8, v4, 31 # CHECK-INST: vssrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f aa vssra.vv v8, v4, v20, v0.t # CHECK-INST: vssra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a ac vssra.vv v8, v4, v20 # CHECK-INST: vssra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a ae vssra.vx v8, v4, a0, v0.t # CHECK-INST: vssra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 ac vssra.vx v8, v4, a0 # CHECK-INST: vssra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 ae vssra.vi v8, v4, 31, v0.t # CHECK-INST: vssra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f ac vssra.vi v8, v4, 31 # CHECK-INST: vssra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f ae diff --git a/llvm/test/MC/RISCV/rvv/sign-injection.s b/llvm/test/MC/RISCV/rvv/sign-injection.s --- a/llvm/test/MC/RISCV/rvv/sign-injection.s +++ b/llvm/test/MC/RISCV/rvv/sign-injection.s @@ -14,71 +14,71 @@ vfsgnj.vv v8, v4, v20, v0.t # CHECK-INST: vfsgnj.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x20] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 20 vfsgnj.vv v8, v4, v20 # CHECK-INST: vfsgnj.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x22] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 22 vfsgnj.vf v8, v4, fa0, v0.t # CHECK-INST: vfsgnj.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x20] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 20 vfsgnj.vf v8, v4, fa0 # CHECK-INST: vfsgnj.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x22] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 22 vfsgnjn.vv v8, v4, v20, v0.t # CHECK-INST: vfsgnjn.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x24] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 24 vfsgnjn.vv v8, v4, v20 # CHECK-INST: vfsgnjn.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x26] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 26 vfsgnjn.vf v8, v4, fa0, v0.t # CHECK-INST: vfsgnjn.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 24 vfsgnjn.vf v8, v4, fa0 # CHECK-INST: vfsgnjn.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 26 vfsgnjx.vv v8, v4, v20, v0.t # CHECK-INST: vfsgnjx.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x28] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 28 vfsgnjx.vv v8, v4, v20 # CHECK-INST: vfsgnjx.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x2a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 14 4a 2a vfsgnjx.vf v8, v4, fa0, v0.t # CHECK-INST: vfsgnjx.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x28] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 28 vfsgnjx.vf v8, v4, fa0 # CHECK-INST: vfsgnjx.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x2a] -# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f', 'Zve64f' or 'Zve64d' # CHECK-UNKNOWN: 57 54 45 2a diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s --- a/llvm/test/MC/RISCV/rvv/store.s +++ b/llvm/test/MC/RISCV/rvv/store.s @@ -11,221 +11,221 @@ vsm.v v24, (a0) # CHECK-INST: vsm.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0xb5,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c b5 02 vse8.v v24, (a0), v0.t # CHECK-INST: vse8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 05 00 vse8.v v24, (a0) # CHECK-INST: vse8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 05 02 vse16.v v24, (a0), v0.t # CHECK-INST: vse16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 5c 05 00 vse16.v v24, (a0) # CHECK-INST: vse16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 5c 05 02 vse32.v v24, (a0), v0.t # CHECK-INST: vse32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 6c 05 00 vse32.v v24, (a0) # CHECK-INST: vse32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 6c 05 02 vse64.v v24, (a0), v0.t # CHECK-INST: vse64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 7c 05 00 vse64.v v24, (a0) # CHECK-INST: vse64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 7c 05 02 vsse8.v v24, (a0), a1, v0.t # CHECK-INST: vsse8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c b5 08 vsse8.v v24, (a0), a1 # CHECK-INST: vsse8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c b5 0a vsse16.v v24, (a0), a1, v0.t # CHECK-INST: vsse16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 5c b5 08 vsse16.v v24, (a0), a1 # CHECK-INST: vsse16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 5c b5 0a vsse32.v v24, (a0), a1, v0.t # CHECK-INST: vsse32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 6c b5 08 vsse32.v v24, (a0), a1 # CHECK-INST: vsse32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 6c b5 0a vsse64.v v24, (a0), a1, v0.t # CHECK-INST: vsse64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 7c b5 08 vsse64.v v24, (a0), a1 # CHECK-INST: vsse64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 7c b5 0a vsuxei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 45 04 vsuxei8.v v24, (a0), v4 # CHECK-INST: vsuxei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 45 06 vsuxei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 5c 45 04 vsuxei16.v v24, (a0), v4 # CHECK-INST: vsuxei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 5c 45 06 vsuxei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 6c 45 04 vsuxei32.v v24, (a0), v4 # CHECK-INST: vsuxei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 6c 45 06 vsuxei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 7c 45 04 vsuxei64.v v24, (a0), v4 # CHECK-INST: vsuxei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 7c 45 06 vsoxei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 45 0c vsoxei8.v v24, (a0), v4 # CHECK-INST: vsoxei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 45 0e vsoxei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 5c 45 0c vsoxei16.v v24, (a0), v4 # CHECK-INST: vsoxei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 5c 45 0e vsoxei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 6c 45 0c vsoxei32.v v24, (a0), v4 # CHECK-INST: vsoxei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 6c 45 0e vsoxei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 7c 45 0c vsoxei64.v v24, (a0), v4 # CHECK-INST: vsoxei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 7c 45 0e vs1r.v v24, (a0) # CHECK-INST: vs1r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 85 02 vs2r.v v24, (a0) # CHECK-INST: vs2r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 85 22 vs4r.v v24, (a0) # CHECK-INST: vs4r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 85 62 vs8r.v v24, (a0) # CHECK-INST: vs8r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 27 0c 85 e2 diff --git a/llvm/test/MC/RISCV/rvv/sub.s b/llvm/test/MC/RISCV/rvv/sub.s --- a/llvm/test/MC/RISCV/rvv/sub.s +++ b/llvm/test/MC/RISCV/rvv/sub.s @@ -11,299 +11,299 @@ vsub.vv v8, v4, v20, v0.t # CHECK-INST: vsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 08 vsub.vv v8, v4, v20 # CHECK-INST: vsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 0a vsub.vx v8, v4, a0, v0.t # CHECK-INST: vsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 08 vsub.vx v8, v4, a0 # CHECK-INST: vsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 0a vrsub.vx v8, v4, a0, v0.t # CHECK-INST: vrsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 0c vrsub.vx v8, v4, a0 # CHECK-INST: vrsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 0e vrsub.vi v8, v4, 15, v0.t # CHECK-INST: vrsub.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 0c vrsub.vi v8, v4, 15 # CHECK-INST: vrsub.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 0e vwsubu.vv v8, v4, v20, v0.t # CHECK-INST: vwsubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a c8 vwsubu.vv v8, v4, v20 # CHECK-INST: vwsubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xca] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a ca vwsubu.vx v8, v4, a0, v0.t # CHECK-INST: vwsubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 c8 vwsubu.vx v8, v4, a0 # CHECK-INST: vwsubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xca] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 ca vwsub.vv v8, v4, v20, v0.t # CHECK-INST: vwsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xcc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a cc vwsub.vv v8, v4, v20 # CHECK-INST: vwsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xce] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a ce vwsub.vx v8, v4, a0, v0.t # CHECK-INST: vwsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 cc vwsub.vx v8, v4, a0 # CHECK-INST: vwsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 ce vwsubu.wv v8, v4, v20, v0.t # CHECK-INST: vwsubu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a d8 vwsubu.wv v8, v4, v20 # CHECK-INST: vwsubu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xda] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a da vwsubu.wx v8, v4, a0, v0.t # CHECK-INST: vwsubu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 d8 vwsubu.wx v8, v4, a0 # CHECK-INST: vwsubu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xda] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 da vwsub.wv v8, v4, v20, v0.t # CHECK-INST: vwsub.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xdc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a dc vwsub.wv v8, v4, v20 # CHECK-INST: vwsub.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xde] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a de vwsub.wx v8, v4, a0, v0.t # CHECK-INST: vwsub.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xdc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 dc vwsub.wx v8, v4, a0 # CHECK-INST: vwsub.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xde] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 de vsbc.vvm v8, v4, v20, v0 # CHECK-INST: vsbc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 48 vsbc.vvm v4, v4, v20, v0 # CHECK-INST: vsbc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 02 4a 48 vsbc.vvm v8, v4, v8, v0 # CHECK-INST: vsbc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 44 48 vsbc.vxm v8, v4, a0, v0 # CHECK-INST: vsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 48 vmsbc.vvm v8, v4, v20, v0 # CHECK-INST: vmsbc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x4c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 4c vmsbc.vvm v4, v4, v20, v0 # CHECK-INST: vmsbc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x4c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 02 4a 4c vmsbc.vvm v8, v4, v8, v0 # CHECK-INST: vmsbc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x4c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 44 4c vmsbc.vxm v8, v4, a0, v0 # CHECK-INST: vmsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 4c vmsbc.vv v8, v4, v20 # CHECK-INST: vmsbc.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x4e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 4e vmsbc.vx v8, v4, a0 # CHECK-INST: vmsbc.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 4e vssubu.vv v8, v4, v20, v0.t # CHECK-INST: vssubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 88 vssubu.vv v8, v4, v20 # CHECK-INST: vssubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 8a vssubu.vx v8, v4, a0, v0.t # CHECK-INST: vssubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 88 vssubu.vx v8, v4, a0 # CHECK-INST: vssubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 8a vssub.vv v8, v4, v20, v0.t # CHECK-INST: vssub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 8c vssub.vv v8, v4, v20 # CHECK-INST: vssub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 8e vssub.vx v8, v4, a0, v0.t # CHECK-INST: vssub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 8c vssub.vx v8, v4, a0 # CHECK-INST: vssub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 8e vasub.vv v8, v4, v20, v0.t # CHECK-INST: vasub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 2c vasub.vv v8, v4, v20 # CHECK-INST: vasub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 2e vasub.vx v8, v4, a0, v0.t # CHECK-INST: vasub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 2c vasub.vx v8, v4, a0 # CHECK-INST: vasub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 2e vasubu.vv v8, v4, v20, v0.t # CHECK-INST: vasubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 28 vasubu.vv v8, v4, v20 # CHECK-INST: vasubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 24 4a 2a vasubu.vx v8, v4, a0, v0.t # CHECK-INST: vasubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 28 vasubu.vx v8, v4, a0 # CHECK-INST: vasubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 2a diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s --- a/llvm/test/MC/RISCV/rvv/vsetvl.s +++ b/llvm/test/MC/RISCV/rvv/vsetvl.s @@ -12,150 +12,150 @@ vsetvli a2, a0, 0x224 # CHECK-INST: vsetvli a2, a0, 548 # CHECK-ENCODING: [0x57,0x76,0x45,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 45 22 vsetvli a2, a0, 0xd0 # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 0d vsetvli a2, a0, 0xd1 # CHECK-INST: vsetvli a2, a0, e32, m2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x15,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 15 0d vsetvli a2, a0, 0x50 # CHECK-INST: vsetvli a2, a0, e32, m1, ta, mu # CHECK-ENCODING: [0x57,0x76,0x05,0x05] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 05 vsetvli a2, a0, 0x90 # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 09 vsetvli a2, a0, 144 # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 09 vsetvli a2, a0, e32, m1, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 0d vsetvli a2, a0, e32, m2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x15,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 15 0d vsetvli a2, a0, e32, m4, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m4, ta, ma # CHECK-ENCODING: [0x57,0x76,0x25,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 25 0d vsetvli a2, a0, e32, m8, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m8, ta, ma # CHECK-ENCODING: [0x57,0x76,0x35,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 35 0d vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x75,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 75 0d vsetvli a2, a0, e32, mf4, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma # CHECK-ENCODING: [0x57,0x76,0x65,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 65 0d vsetvli a2, a0, e32, mf8, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf8, ta, ma # CHECK-ENCODING: [0x57,0x76,0x55,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 55 0d vsetvli a2, a0, e32, m1, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 0d vsetvli a2, a0, e32, m1, tu, ma # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 09 vsetvli a2, a0, e32, m1, ta, mu # CHECK-INST: vsetvli a2, a0, e32, m1, ta, mu # CHECK-ENCODING: [0x57,0x76,0x05,0x05] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 05 vsetvli a2, a0, e32, m1, tu, mu # CHECK-INST: vsetvli a2, a0, e32, m1 # CHECK-ENCODING: [0x57,0x76,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 05 01 vsetvl a2, a0, a1 # CHECK-INST: vsetvl a2, a0, a1 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 b5 80 # reserved filed: vlmul[2:0]=4, vsew[2:0]=0b1xx, non-zero bits 8/9/10. vsetivli a2, 0, 0x224 # CHECK-INST: vsetivli a2, 0, 548 # CHECK-ENCODING: [0x57,0x76,0x40,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 40 e2 vsetivli a2, 0, 0xd0 # CHECK-INST: vsetivli a2, 0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x00,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 00 cd vsetivli a2, 15, 0xd0 # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 f6 07 cd vsetivli a2, 15, 208 # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 f6 07 cd vsetivli a2, 0, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x00,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 76 00 cd vsetivli a2, 15, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 f6 07 cd vsetivli a2, 31, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 31, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x0f,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 f6 0f cd diff --git a/llvm/test/MC/RISCV/rvv/xor.s b/llvm/test/MC/RISCV/rvv/xor.s --- a/llvm/test/MC/RISCV/rvv/xor.s +++ b/llvm/test/MC/RISCV/rvv/xor.s @@ -11,47 +11,47 @@ vxor.vv v8, v4, v20, v0.t # CHECK-INST: vxor.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 2c vxor.vv v8, v4, v20 # CHECK-INST: vxor.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 04 4a 2e vxor.vx v8, v4, a0, v0.t # CHECK-INST: vxor.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 2c vxor.vx v8, v4, a0 # CHECK-INST: vxor.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 44 45 2e vxor.vi v8, v4, 15, v0.t # CHECK-INST: vxor.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 2c vxor.vi v8, v4, 15 # CHECK-INST: vxor.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 47 2e vnot.v v8, v4, v0.t # CHECK-INST: vnot.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 2c vnot.v v8, v4 # CHECK-INST: vxor.vi v8, v4, -1 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 b4 4f 2e