Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1105,7 +1105,12 @@
     return true;
   default:;
   }
-  return isSEHInstruction(MI);
+  const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
+  return isSEHInstruction(MI) ||
+         ((MI.getFlag(MachineInstr::FrameSetup) ||
+           MI.getFlag(MachineInstr::FrameDestroy)) &&
+          TFI.hasFP(MF) && MI.modifiesRegister(AArch64::FP) &&
+          MF.getFunction().needsUnwindTableEntry());
 }
 
 /// analyzeCompare - For a comparison instruction, return the source registers
Index: llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
@@ -27,8 +27,8 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #288
 ; CHECK-NEXT:    stp x29, x30, [sp, #256] // 16-byte Folded Spill
-; CHECK-NEXT:    add x29, sp, #256
 ; CHECK-NEXT:    str x28, [sp, #272] // 8-byte Folded Spill
+; CHECK-NEXT:    add x29, sp, #256
 ; CHECK-NEXT:    .cfi_def_cfa w29, 32
 ; CHECK-NEXT:    .cfi_offset w28, -16
 ; CHECK-NEXT:    .cfi_offset w30, -24
@@ -66,8 +66,8 @@
 ; CHECK-NEXT:    ldr q0, [x0, #240]
 ; CHECK-NEXT:    str q0, [sp, #240]
 ; CHECK-NEXT:    bl byval_a64i32
-; CHECK-NEXT:    ldp x29, x30, [sp, #256] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldr x28, [sp, #272] // 8-byte Folded Reload
+; CHECK-NEXT:    ldp x29, x30, [sp, #256] // 16-byte Folded Reload
 ; CHECK-NEXT:    add sp, sp, #288
 ; CHECK-NEXT:    ret
   call void @byval_a64i32([64 x i32]* byval([64 x i32]) %incoming)
Index: llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
@@ -453,9 +453,9 @@
 ; CHECK:  mov      x5, x25
 ; CHECK:  mov      x6, x26
 ; CHECK:  mov      x7, x27
-; CHECK:  ldp     x29, x30, [sp
 ; CHECK:  mov      x21, x28
 ; Restore callee save registers.
+; CHECK:  ldp     x29, x30, [sp
 ; CHECK:  ldp     x20, x19, [sp
 ; CHECK:  ldp     x23, x22, [sp
 ; CHECK:  ldp     x25, x24, [sp
Index: llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
+++ llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
@@ -33,12 +33,12 @@
 ; CHECK-NEXT:    bl __Z3goof
 ; CHECK-NEXT:    fadd s0, s10, s0
 ; CHECK-NEXT:    scvtf s1, w19
-; CHECK-NEXT:    ldp x29, x30, [sp, #48]
-; CHECK-NEXT:    ldp x20, x19, [sp, #32]
 ; CHECK-NEXT:    fmul s0, s8, s0
 ; CHECK-NEXT:    fadd s0, s9, s0
-; CHECK-NEXT:    ldp d9, d8, [sp, #16]
 ; CHECK-NEXT:    fsub s0, s0, s1
+; CHECK-NEXT:    ldp x29, x30, [sp, #48]
+; CHECK-NEXT:    ldp x20, x19, [sp, #32]
+; CHECK-NEXT:    ldp d9, d8, [sp, #16]
 ; CHECK-NEXT:    ldp d11, d10, [sp], #64
 ; CHECK-NEXT:    ret
 ;
@@ -47,8 +47,8 @@
 ; CHECK-LINUX-NEXT:    stp d11, d10, [sp, #-64]!
 ; CHECK-LINUX-NEXT:    stp d9, d8, [sp, #16]
 ; CHECK-LINUX-NEXT:    stp x29, x30, [sp, #32]
-; CHECK-LINUX-NEXT:    add x29, sp, #32
 ; CHECK-LINUX-NEXT:    stp x20, x19, [sp, #48]
+; CHECK-LINUX-NEXT:    add x29, sp, #32
 ; CHECK-LINUX-NEXT:    .cfi_def_cfa w29, 32
 ; CHECK-LINUX-NEXT:    .cfi_offset w19, -8
 ; CHECK-LINUX-NEXT:    .cfi_offset w20, -16
@@ -73,11 +73,11 @@
 ; CHECK-LINUX-NEXT:    fadd s0, s10, s0
 ; CHECK-LINUX-NEXT:    scvtf s1, w19
 ; CHECK-LINUX-NEXT:    ldp x20, x19, [sp, #48]
-; CHECK-LINUX-NEXT:    ldp x29, x30, [sp, #32]
 ; CHECK-LINUX-NEXT:    fmul s0, s8, s0
 ; CHECK-LINUX-NEXT:    fadd s0, s9, s0
-; CHECK-LINUX-NEXT:    ldp d9, d8, [sp, #16]
 ; CHECK-LINUX-NEXT:    fsub s0, s0, s1
+; CHECK-LINUX-NEXT:    ldp x29, x30, [sp, #32]
+; CHECK-LINUX-NEXT:    ldp d9, d8, [sp, #16]
 ; CHECK-LINUX-NEXT:    ldp d11, d10, [sp], #64
 ; CHECK-LINUX-NEXT:    ret
 entry:
Index: llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
+++ llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
@@ -16,8 +16,8 @@
 
 # CHECK: stp d9, d8, [sp, #-48]!
 # CHECK: stp x29, x30, [sp, #16]
-# CHECK: add x29, sp, #16
 # CHECK: str x19, [sp, #32]
+# CHECK: add x29, sp, #16
 
 # CHECK: .cfi_def_cfa w29, 32
 # CHECK: .cfi_offset w19, -16
Index: llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
+++ llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
@@ -28,12 +28,12 @@
 ; CHECK-LABEL: b:
 ; CHECK:       str     d8, [sp, #-32]!
 ; CHECK-NEXT:  stp     x29, x30, [sp, #8]
-; CHECK-NEXT:  add     x29, sp, #8
 ; CHECK-NEXT:  str     x19, [sp, #24]
+; CHECK-NEXT:  add     x29, sp, #8
 
 ; CHECK:       sub     sp, x29, #8
-; CHECK-NEXT:  ldp     x29, x30, [sp, #8]
 ; CHECK-NEXT:  ldr     x19, [sp, #24]
+; CHECK-NEXT:  ldp     x29, x30, [sp, #8]
 ; CHECK-NEXT:  ldr     d8, [sp], #32
 ; CHECK-NEXT:  ret
 
Index: llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
===================================================================
--- llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
+++ llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
@@ -39,8 +39,8 @@
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    b.ne LBB0_2
 ; CHECK-NEXT:  ; %bb.1: ; %entry
-; CHECK-NEXT:    ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
 ; CHECK-NEXT:    mov w0, #-1
+; CHECK-NEXT:    ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
 ; CHECK-NEXT:    add sp, sp, #64
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  LBB0_2: ; %entry
Index: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
@@ -49,8 +49,8 @@
 ; CHECK-LABEL: select_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
@@ -112,8 +112,8 @@
 ; VBITS_GE_512-LABEL: select_v32f16:
 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
+; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
@@ -207,8 +207,8 @@
 ; VBITS_GE_1024-LABEL: select_v64f16:
 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
+; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
@@ -366,8 +366,8 @@
 ; VBITS_GE_2048-LABEL: select_v128f16:
 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
+; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
@@ -679,8 +679,8 @@
 ; CHECK-LABEL: select_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
@@ -722,8 +722,8 @@
 ; VBITS_GE_512-LABEL: select_v16f32:
 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
+; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
@@ -777,8 +777,8 @@
 ; VBITS_GE_1024-LABEL: select_v32f32:
 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
+; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
@@ -856,8 +856,8 @@
 ; VBITS_GE_2048-LABEL: select_v64f32:
 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
+; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
@@ -1009,8 +1009,8 @@
 ; CHECK-LABEL: select_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
@@ -1049,8 +1049,8 @@
 ; VBITS_GE_512-LABEL: select_v8f64:
 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
+; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
@@ -1099,8 +1099,8 @@
 ; VBITS_GE_1024-LABEL: select_v16f64:
 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
+; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
@@ -1169,8 +1169,8 @@
 ; VBITS_GE_2048-LABEL: select_v32f64:
 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
+; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
Index: llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
@@ -48,8 +48,8 @@
 ; CHECK-LABEL: select_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
@@ -143,8 +143,8 @@
 ; VBITS_GE_512-LABEL: select_v64i8:
 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
+; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
@@ -302,8 +302,8 @@
 ; VBITS_GE_1024-LABEL: select_v128i8:
 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
+; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
@@ -590,8 +590,8 @@
 ; VBITS_GE_2048-LABEL: select_v256i8:
 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
+; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
@@ -1161,8 +1161,8 @@
 ; CHECK-LABEL: select_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
@@ -1224,8 +1224,8 @@
 ; VBITS_GE_512-LABEL: select_v32i16:
 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
+; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
@@ -1319,8 +1319,8 @@
 ; VBITS_GE_1024-LABEL: select_v64i16:
 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
+; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
@@ -1478,8 +1478,8 @@
 ; VBITS_GE_2048-LABEL: select_v128i16:
 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
+; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
@@ -1791,8 +1791,8 @@
 ; CHECK-LABEL: select_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
@@ -1834,8 +1834,8 @@
 ; VBITS_GE_512-LABEL: select_v16i32:
 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
+; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
@@ -1889,8 +1889,8 @@
 ; VBITS_GE_1024-LABEL: select_v32i32:
 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
+; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
@@ -1968,8 +1968,8 @@
 ; VBITS_GE_2048-LABEL: select_v64i32:
 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
+; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
@@ -2121,8 +2121,8 @@
 ; CHECK-LABEL: select_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
@@ -2161,8 +2161,8 @@
 ; VBITS_GE_512-LABEL: select_v8i64:
 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
+; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
@@ -2211,8 +2211,8 @@
 ; VBITS_GE_1024-LABEL: select_v16i64:
 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
+; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
@@ -2281,8 +2281,8 @@
 ; VBITS_GE_2048-LABEL: select_v32i64:
 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
+; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
Index: llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
@@ -932,8 +932,8 @@
 ; CHECK-LABEL: shuffle_ext_invalid:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
===================================================================
--- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
+++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
@@ -89,8 +89,8 @@
 ; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    bl OUTLINED_FUNCTION_0
 ; CHECK-NEXT:  .LBB0_5:
-; CHECK-NEXT:    ldp x29, x30, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    ldp x29, x30, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    add sp, sp, #48
 ; CHECK-NEXT:    ret
 ;
@@ -115,8 +115,8 @@
 ; CHECK-NEXT:    //APP
 ; CHECK-NEXT:    //NO_APP
 ; CHECK-NEXT:    stp w10, w8, [x29, #-12]
-; CHECK-NEXT:    ldp x29, x30, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    stp w9, w11, [sp, #12]
+; CHECK-NEXT:    ldp x29, x30, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    add sp, sp, #48
 ; CHECK-NEXT:    ret
 ;
Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
===================================================================
--- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
+++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
@@ -30,8 +30,8 @@
 ; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    bl OUTLINED_FUNCTION_0
 ; CHECK-NEXT:  .LBB0_5:
-; CHECK-NEXT:    ldp x29, x30, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    ldp x29, x30, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    add sp, sp, #48
 ; CHECK-NEXT:    ret
   %1 = alloca i32, align 4
@@ -92,8 +92,8 @@
 ; CHECK-NEXT:    //APP
 ; CHECK-NEXT:    //NO_APP
 ; CHECK-NEXT:    stp w10, w8, [x29, #-12]
-; CHECK-NEXT:    ldp x29, x30, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    stp w9, w11, [sp, #12]
+; CHECK-NEXT:    ldp x29, x30, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    add sp, sp, #48
 ; CHECK-NEXT:    ret
   %1 = alloca i32, align 4