diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -4997,6 +4997,57 @@
     }
     break;
 
+  case ISD::INTRINSIC_VOID: {
+    auto IntrinsicID = N->getConstantOperandVal(1);
+    if (IntrinsicID == Intrinsic::ppc_tdw || IntrinsicID == Intrinsic::ppc_tw) {
+      unsigned Opcode = 0;
+      SDValue Ops[] = {N->getOperand(4), N->getOperand(2), N->getOperand(3)};
+      int16_t SImmOperand2;
+      int16_t SImmOperand3;
+      int16_t SImmOperand4;
+      bool isOperand2IntS16Immediate =
+          isIntS16Immediate(N->getOperand(2), SImmOperand2);
+      bool isOperand3IntS16Immediate =
+          isIntS16Immediate(N->getOperand(3), SImmOperand3);
+      // We will emit PPC::TD or PPC::TW if the 2nd and 3rd operands are reg +
+      // reg or imm + imm. The imm + imm form will be optimized to either an
+      // unconditional trap or a nop in a later pass.
+      if (isOperand2IntS16Immediate == isOperand3IntS16Immediate) {
+        Opcode = IntrinsicID == Intrinsic::ppc_tdw ? PPC::TD : PPC::TW;
+      }
+      // We will emit PPC::TDI or PPC::TWI if the 2nd and 3rd operands are reg +
+      // imm or imm + reg.
+      else {
+        Opcode = IntrinsicID == Intrinsic::ppc_tdw ? PPC::TDI : PPC::TWI;
+        // The 2nd and 3rd operands are reg + imm.
+        if (isOperand3IntS16Immediate) {
+          Ops[2] = getI32Imm(int(SImmOperand3) & 0xFFFF, dl);
+        }
+        // The 2nd and 3rd operands are imm + reg.
+        else {
+          bool isOperand4IntS16Immediate =
+              isIntS16Immediate(N->getOperand(4), SImmOperand4);
+          assert(isOperand4IntS16Immediate &&
+                 "The 4th operand is not an Immediate");
+          // We need to flip the condition immediate TO.
+          int16_t TO = int(SImmOperand4) & 0x1F;
+          // We swap the first and second bit of TO if they are not same.
+          if ((TO & 0x1) != ((TO & 0x2) >> 1))
+            TO = (TO & 0x1) ? TO + 1 : TO - 1;
+          // We swap the fourth and fifthy bit of TO if they are not same.
+          if ((TO & 0x8) != ((TO & 0x10) >> 1))
+            TO = (TO & 0x8) ? TO + 8 : TO - 8;
+          Ops[0] = getI32Imm(TO, dl);
+          Ops[1] = N->getOperand(3);
+          Ops[2] = getI32Imm(int(SImmOperand2) & 0xFFFF, dl);
+        }
+      }
+      CurDAG->SelectNodeTo(N, Opcode, MVT::Other, Ops);
+      return;
+    }
+    break;
+  }
+
   case ISD::INTRINSIC_WO_CHAIN: {
     // We emit the PPC::FSELS instruction here because of type conflicts with
     // the comparison operand. The FSELS instruction is defined to use an 8-byte
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1877,8 +1877,6 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
           (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
-          (TD $IMM, $A, $B)>;
 
 // trapd
 def : Pat<(int_ppc_trapd g8rc:$A),
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5477,8 +5477,6 @@
           (STWCX gprc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
           (STBCX gprc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
-          (TW $IMM, $A, $B)>;
 def : Pat<(int_ppc_trap gprc:$A),
           (TWI 24, $A, 0)>;
 
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
@@ -124,6 +124,213 @@
   ret void
 }
 
+; tdw -> tdi
+define dso_local void @test__tdi_reg_imm_boundary(i64 %a) {
+; CHECK-LABEL: test__tdi_reg_imm_boundary:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdi 3, r3, 32767
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 32767, i32 3)
+  ret void
+}
+
+define dso_local void @test__tdi_imm_reg_boundary(i64 %a) {
+; CHECK-LABEL: test__tdi_imm_reg_boundary:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdi 3, r3, 32767
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 32767, i64 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tdi_reg_imm_boundary1(i64 %a) {
+; CHECK-LABEL: test__tdi_reg_imm_boundary1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdi 3, r3, -32768
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 -32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__tdi_imm_reg_boundary1(i64 %a) {
+; CHECK-LABEL: test__tdi_imm_reg_boundary1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdi 3, r3, -32768
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 -32768, i64 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__td_reg_imm_boundary2(i64 %a) {
+; CHECK-LABEL: test__td_reg_imm_boundary2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    ori r4, r4, 32768
+; CHECK-NEXT:    td 3, r4, r3
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 32768, i64 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__td_imm_reg_boundary2(i64 %a) {
+; CHECK-LABEL: test__td_imm_reg_boundary2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    ori r4, r4, 32768
+; CHECK-NEXT:    td 3, r3, r4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__td_reg_imm_boundary3(i64 %a) {
+; CHECK-LABEL: test__td_reg_imm_boundary3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis r4, -1
+; CHECK-NEXT:    ori r4, r4, 32767
+; CHECK-NEXT:    td 3, r3, r4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 -32769, i32 3)
+  ret void
+}
+
+define dso_local void @test__td_imm_reg_boundary3(i64 %a) {
+; CHECK-LABEL: test__td_imm_reg_boundary3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis r4, -1
+; CHECK-NEXT:    ori r4, r4, 32767
+; CHECK-NEXT:    td 3, r3, r4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 -32769, i32 3)
+  ret void
+}
+
+define dso_local void @test__tdlgti_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdlgti_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdlgti r3, 0
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 0, i32 1)
+  ret void
+}
+
+define dso_local void @test__tdllti_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdllti_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdllti r3, 0
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 0, i64 %a, i32 1)
+  ret void
+}
+
+define dso_local void @test__tdllti_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdllti_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdllti r3, 1
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 1, i32 2)
+  ret void
+}
+
+define dso_local void @test__tdlgti_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdlgti_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdlgti r3, 1
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 1, i64 %a, i32 2)
+  ret void
+}
+
+define dso_local void @test__tdeqi_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdeqi_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdeqi r3, 2
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 2, i32 4)
+  ret void
+}
+
+define dso_local void @test__tdeqi_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdeqi_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdeqi r3, 2
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 2, i64 %a, i32 4)
+  ret void
+}
+
+define dso_local void @test__tdgti_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdgti_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdgti r3, 16
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 16, i32 8)
+  ret void
+}
+
+define dso_local void @test__tdlti_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdlti_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdlti r3, 16
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 16, i64 %a, i32 8)
+  ret void
+}
+
+define dso_local void @test__tdlti_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdlti_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdlti r3, 64
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 64, i32 16)
+  ret void
+}
+
+define dso_local void @test__tdgti_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdgti_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdgti r3, 64
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 64, i64 %a, i32 16)
+  ret void
+}
+
+define dso_local void @test__tdnei_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdnei_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdnei r3, 256
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 256, i32 24)
+  ret void
+}
+
+define dso_local void @test__tdnei_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdnei_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdnei r3, 256
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 256, i64 %a, i32 24)
+  ret void
+}
+
+define dso_local void @test__tdui_reg_imm(i64 %a) {
+; CHECK-LABEL: test__tdui_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdui r3, 512
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 512, i32 31)
+  ret void
+}
+
+define dso_local void @test__tdui_imm_reg(i64 %a) {
+; CHECK-LABEL: test__tdui_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdui r3, 512
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 512, i64 %a, i32 31)
+  ret void
+}
+
 ; trapd
 declare void @llvm.ppc.trapd(i64 %a)
 define dso_local void @test__trapd(i64 %a) {
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -127,6 +127,213 @@
   ret void
 }
 
+; tw -> twi
+define dso_local void @test__twi_boundary_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twi 3, r3, 32767
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 32767, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twi 3, r3, 32767
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 32767, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twi 3, r3, -32768
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__twi_boundary1_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twi_boundary1_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twi 3, r3, -32768
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 -32768, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis r4, 0
+; CHECK-NEXT:    ori r4, r4, 32768
+; CHECK-NEXT:    tw 3, r3, r4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 32768, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary2_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary2_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis r4, 0
+; CHECK-NEXT:    ori r4, r4, 32768
+; CHECK-NEXT:    tw 3, r4, r3
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 32768, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis r4, -1
+; CHECK-NEXT:    ori r4, r4, 32767
+; CHECK-NEXT:    tw 3, r3, r4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 -32769, i32 3)
+  ret void
+}
+
+define dso_local void @test__tw_boundary3_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tw_boundary3_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis r4, -1
+; CHECK-NEXT:    ori r4, r4, 32767
+; CHECK-NEXT:    tw 3, r4, r3
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 -32769, i32 %a, i32 3)
+  ret void
+}
+
+define dso_local void @test__twlgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twlgti_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twlgti r3, 0
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 0, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twllti_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twllti r3, 0
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 0, i32 %a, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twllti_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twllti r3, 1
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 1, i32 2)
+  ret void
+}
+
+define dso_local void @test__twlgti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlgti_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twlgti r3, 1
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 1, i32 %a, i32 2)
+  ret void
+}
+
+define dso_local void @test__tweqi_reg_imm(i32 %a) {
+; CHECK-LABEL: test__tweqi_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tweqi r3, 2
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 2, i32 4)
+  ret void
+}
+
+define dso_local void @test__tweqi_imm_reg(i32 %a) {
+; CHECK-LABEL: test__tweqi_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tweqi r3, 2
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 2, i32 %a, i32 4)
+  ret void
+}
+
+define dso_local void @test__twgti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twgti_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twgti r3, 16
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 16, i32 8)
+  ret void
+}
+
+define dso_local void @test__twlti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twlti_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twlti r3, 16
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 16, i32 %a, i32 8)
+  ret void
+}
+
+define dso_local void @test__twlti_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twlti_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twlti r3, 64
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 64, i32 16)
+  ret void
+}
+
+define dso_local void @test__twgti_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twgti_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twgti r3, 64
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 64, i32 %a, i32 16)
+  ret void
+}
+
+define dso_local void @test__twnei_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twnei_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twnei r3, 256
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 256, i32 24)
+  ret void
+}
+
+define dso_local void @test__twnei_imm_reg(i32 %a) {
+; CHECK-LABEL: test__twnei_imm_reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twnei r3, 256
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 256, i32 %a, i32 24)
+  ret void
+}
+
+define dso_local void @test__twui_reg_imm(i32 %a) {
+; CHECK-LABEL: test__twui_reg_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twui r3, 512
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 512, i32 31)
+  ret void
+}
+
+define dso_local void @test__twui_imm_imm(i32 %a) {
+; CHECK-LABEL: test__twui_imm_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twui r3, 512
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 512, i32 %a, i32 31)
+  ret void
+}
+
 ; trap
 declare void @llvm.ppc.trap(i32 %a)
 define dso_local void @test__trap(i32 %a) {