diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp --- a/llvm/lib/IR/Instruction.cpp +++ b/llvm/lib/IR/Instruction.cpp @@ -142,27 +142,23 @@ } void Instruction::dropPoisonGeneratingFlags() { - switch (getOpcode()) { - case Instruction::Add: - case Instruction::Sub: - case Instruction::Mul: - case Instruction::Shl: - cast(this)->setHasNoUnsignedWrap(false); - cast(this)->setHasNoSignedWrap(false); - break; - - case Instruction::UDiv: - case Instruction::SDiv: - case Instruction::AShr: - case Instruction::LShr: - cast(this)->setIsExact(false); - break; - - case Instruction::GetElementPtr: - cast(this)->setIsInBounds(false); - break; + if (auto *OverflowingOp = dyn_cast(this)) { + OverflowingOp->setHasNoUnsignedWrap(false); + OverflowingOp->setHasNoSignedWrap(false); + return; + } + if (auto *ExactOp = dyn_cast(this)) { + ExactOp->setIsExact(false); + return; + } + if (auto *Gep = dyn_cast(this)) { + Gep->setIsInBounds(false); + return; + } + if (auto *FPMOp = dyn_cast(this)) { + FPMOp->setHasNoNaNs(false); + FPMOp->setHasNoInfs(false); } - // TODO: FastMathFlags! } void Instruction::dropUndefImplyingAttrsAndUnknownMetadata( diff --git a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll --- a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll +++ b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll @@ -89,9 +89,9 @@ ; CHECK-LABEL: @fadd_f32( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[VEC:%.*]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[VEC]], [[RDX_SHUF]] +; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd reassoc nsz arcp contract afn <4 x float> [[VEC]], [[RDX_SHUF]] ; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX2:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF1]] +; CHECK-NEXT: [[BIN_RDX2:%.*]] = fadd reassoc nsz arcp contract afn <4 x float> [[BIN_RDX]], [[RDX_SHUF1]] ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[BIN_RDX2]], i32 0 ; CHECK-NEXT: [[BIN_RDX3:%.*]] = fadd fast float 0.000000e+00, [[TMP0]] ; CHECK-NEXT: ret float [[BIN_RDX3]] @@ -105,9 +105,9 @@ ; CHECK-LABEL: @fadd_f32_accum( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[VEC:%.*]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[VEC]], [[RDX_SHUF]] +; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd reassoc nsz arcp contract afn <4 x float> [[VEC]], [[RDX_SHUF]] ; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX2:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF1]] +; CHECK-NEXT: [[BIN_RDX2:%.*]] = fadd reassoc nsz arcp contract afn <4 x float> [[BIN_RDX]], [[RDX_SHUF1]] ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[BIN_RDX2]], i32 0 ; CHECK-NEXT: [[BIN_RDX3:%.*]] = fadd fast float [[ACCUM:%.*]], [[TMP0]] ; CHECK-NEXT: ret float [[BIN_RDX3]] @@ -157,9 +157,9 @@ ; CHECK-LABEL: @fmul_f32( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[VEC:%.*]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul fast <4 x float> [[VEC]], [[RDX_SHUF]] +; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul reassoc nsz arcp contract afn <4 x float> [[VEC]], [[RDX_SHUF]] ; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX2:%.*]] = fmul fast <4 x float> [[BIN_RDX]], [[RDX_SHUF1]] +; CHECK-NEXT: [[BIN_RDX2:%.*]] = fmul reassoc nsz arcp contract afn <4 x float> [[BIN_RDX]], [[RDX_SHUF1]] ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[BIN_RDX2]], i32 0 ; CHECK-NEXT: [[BIN_RDX3:%.*]] = fmul fast float 1.000000e+00, [[TMP0]] ; CHECK-NEXT: ret float [[BIN_RDX3]] @@ -173,9 +173,9 @@ ; CHECK-LABEL: @fmul_f32_accum( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[VEC:%.*]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul fast <4 x float> [[VEC]], [[RDX_SHUF]] +; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul reassoc nsz arcp contract afn <4 x float> [[VEC]], [[RDX_SHUF]] ; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX2:%.*]] = fmul fast <4 x float> [[BIN_RDX]], [[RDX_SHUF1]] +; CHECK-NEXT: [[BIN_RDX2:%.*]] = fmul reassoc nsz arcp contract afn <4 x float> [[BIN_RDX]], [[RDX_SHUF1]] ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[BIN_RDX2]], i32 0 ; CHECK-NEXT: [[BIN_RDX3:%.*]] = fmul fast float [[ACCUM:%.*]], [[TMP0]] ; CHECK-NEXT: ret float [[BIN_RDX3]] diff --git a/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll b/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll --- a/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll @@ -211,7 +211,7 @@ define float @extelt_binop_insertelt(<4 x float> %A, <4 x float> %B, float %f) { ; CHECK-LABEL: @extelt_binop_insertelt( ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[B:%.*]], i32 0 -; CHECK-NEXT: [[E:%.*]] = fmul nnan float [[TMP1]], [[F:%.*]] +; CHECK-NEXT: [[E:%.*]] = fmul float [[TMP1]], [[F:%.*]] ; CHECK-NEXT: ret float [[E]] ; %C = insertelement <4 x float> %A, float %f, i32 0 diff --git a/llvm/test/Transforms/InstCombine/scalarization.ll b/llvm/test/Transforms/InstCombine/scalarization.ll --- a/llvm/test/Transforms/InstCombine/scalarization.ll +++ b/llvm/test/Transforms/InstCombine/scalarization.ll @@ -211,7 +211,7 @@ define float @extelt_binop_insertelt(<4 x float> %A, <4 x float> %B, float %f) { ; CHECK-LABEL: @extelt_binop_insertelt( ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[B:%.*]], i32 0 -; CHECK-NEXT: [[E:%.*]] = fmul nnan float [[TMP1]], [[F:%.*]] +; CHECK-NEXT: [[E:%.*]] = fmul float [[TMP1]], [[F:%.*]] ; CHECK-NEXT: ret float [[E]] ; %C = insertelement <4 x float> %A, float %f, i32 0 diff --git a/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll --- a/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll @@ -371,7 +371,7 @@ define <4 x double> @fdiv_constant_op0(<4 x double> %v) { ; CHECK-LABEL: @fdiv_constant_op0( -; CHECK-NEXT: [[B:%.*]] = fdiv fast <4 x double> , [[V:%.*]] +; CHECK-NEXT: [[B:%.*]] = fdiv reassoc nsz arcp contract afn <4 x double> , [[V:%.*]] ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x double> [[V]], <4 x double> [[B]], <4 x i32> ; CHECK-NEXT: ret <4 x double> [[S]] ; @@ -778,7 +778,7 @@ define <4 x double> @fdiv_fdiv(<4 x double> %v0) { ; CHECK-LABEL: @fdiv_fdiv( -; CHECK-NEXT: [[T3:%.*]] = fdiv nnan arcp <4 x double> , [[V0:%.*]] +; CHECK-NEXT: [[T3:%.*]] = fdiv arcp <4 x double> , [[V0:%.*]] ; CHECK-NEXT: ret <4 x double> [[T3]] ; %t1 = fdiv fast <4 x double> , %v0 @@ -1271,7 +1271,7 @@ define <4 x double> @frem_2_vars(<4 x double> %v0, <4 x double> %v1) { ; CHECK-LABEL: @frem_2_vars( ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <4 x i32> -; CHECK-NEXT: [[T3:%.*]] = frem nnan <4 x double> , [[TMP1]] +; CHECK-NEXT: [[T3:%.*]] = frem <4 x double> , [[TMP1]] ; CHECK-NEXT: ret <4 x double> [[T3]] ; %t1 = frem nnan ninf <4 x double> , %v0 diff --git a/llvm/test/Transforms/InstCombine/shuffle_select.ll b/llvm/test/Transforms/InstCombine/shuffle_select.ll --- a/llvm/test/Transforms/InstCombine/shuffle_select.ll +++ b/llvm/test/Transforms/InstCombine/shuffle_select.ll @@ -371,7 +371,7 @@ define <4 x double> @fdiv_constant_op0(<4 x double> %v) { ; CHECK-LABEL: @fdiv_constant_op0( -; CHECK-NEXT: [[B:%.*]] = fdiv fast <4 x double> , [[V:%.*]] +; CHECK-NEXT: [[B:%.*]] = fdiv reassoc nsz arcp contract afn <4 x double> , [[V:%.*]] ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x double> [[V]], <4 x double> [[B]], <4 x i32> ; CHECK-NEXT: ret <4 x double> [[S]] ; @@ -778,7 +778,7 @@ define <4 x double> @fdiv_fdiv(<4 x double> %v0) { ; CHECK-LABEL: @fdiv_fdiv( -; CHECK-NEXT: [[T3:%.*]] = fdiv nnan arcp <4 x double> , [[V0:%.*]] +; CHECK-NEXT: [[T3:%.*]] = fdiv arcp <4 x double> , [[V0:%.*]] ; CHECK-NEXT: ret <4 x double> [[T3]] ; %t1 = fdiv fast <4 x double> , %v0 @@ -1271,7 +1271,7 @@ define <4 x double> @frem_2_vars(<4 x double> %v0, <4 x double> %v1) { ; CHECK-LABEL: @frem_2_vars( ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <4 x i32> -; CHECK-NEXT: [[T3:%.*]] = frem nnan <4 x double> , [[TMP1]] +; CHECK-NEXT: [[T3:%.*]] = frem <4 x double> , [[TMP1]] ; CHECK-NEXT: ret <4 x double> [[T3]] ; %t1 = frem nnan ninf <4 x double> , %v0 diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll --- a/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll @@ -435,7 +435,7 @@ define <3 x float> @shuf_fsub(<3 x float> %x) { ; CHECK-LABEL: @shuf_fsub( -; CHECK-NEXT: [[BO:%.*]] = fsub fast <3 x float> , [[X:%.*]] +; CHECK-NEXT: [[BO:%.*]] = fsub reassoc nsz arcp contract afn <3 x float> , [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; @@ -457,7 +457,7 @@ define <3 x float> @shuf_fdiv_const_op0(<3 x float> %x) { ; CHECK-LABEL: @shuf_fdiv_const_op0( -; CHECK-NEXT: [[BO:%.*]] = fdiv reassoc ninf <3 x float> , [[X:%.*]] +; CHECK-NEXT: [[BO:%.*]] = fdiv reassoc <3 x float> , [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; @@ -468,7 +468,7 @@ define <3 x float> @shuf_fdiv_const_op1(<3 x float> %x) { ; CHECK-LABEL: @shuf_fdiv_const_op1( -; CHECK-NEXT: [[BO:%.*]] = fdiv nnan ninf <3 x float> [[X:%.*]], +; CHECK-NEXT: [[BO:%.*]] = fdiv <3 x float> [[X:%.*]], ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; @@ -479,7 +479,7 @@ define <3 x float> @shuf_frem_const_op0(<3 x float> %x) { ; CHECK-LABEL: @shuf_frem_const_op0( -; CHECK-NEXT: [[BO:%.*]] = frem nnan <3 x float> , [[X:%.*]] +; CHECK-NEXT: [[BO:%.*]] = frem <3 x float> , [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; @@ -490,7 +490,7 @@ define <3 x float> @shuf_frem_const_op1(<3 x float> %x) { ; CHECK-LABEL: @shuf_frem_const_op1( -; CHECK-NEXT: [[BO:%.*]] = frem reassoc ninf <3 x float> [[X:%.*]], +; CHECK-NEXT: [[BO:%.*]] = frem reassoc <3 x float> [[X:%.*]], ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll --- a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll +++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll @@ -435,7 +435,7 @@ define <3 x float> @shuf_fsub(<3 x float> %x) { ; CHECK-LABEL: @shuf_fsub( -; CHECK-NEXT: [[BO:%.*]] = fsub fast <3 x float> , [[X:%.*]] +; CHECK-NEXT: [[BO:%.*]] = fsub reassoc nsz arcp contract afn <3 x float> , [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; @@ -457,7 +457,7 @@ define <3 x float> @shuf_fdiv_const_op0(<3 x float> %x) { ; CHECK-LABEL: @shuf_fdiv_const_op0( -; CHECK-NEXT: [[BO:%.*]] = fdiv reassoc ninf <3 x float> , [[X:%.*]] +; CHECK-NEXT: [[BO:%.*]] = fdiv reassoc <3 x float> , [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; @@ -468,7 +468,7 @@ define <3 x float> @shuf_fdiv_const_op1(<3 x float> %x) { ; CHECK-LABEL: @shuf_fdiv_const_op1( -; CHECK-NEXT: [[BO:%.*]] = fdiv nnan ninf <3 x float> [[X:%.*]], +; CHECK-NEXT: [[BO:%.*]] = fdiv <3 x float> [[X:%.*]], ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; @@ -479,7 +479,7 @@ define <3 x float> @shuf_frem_const_op0(<3 x float> %x) { ; CHECK-LABEL: @shuf_frem_const_op0( -; CHECK-NEXT: [[BO:%.*]] = frem nnan <3 x float> , [[X:%.*]] +; CHECK-NEXT: [[BO:%.*]] = frem <3 x float> , [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; @@ -490,7 +490,7 @@ define <3 x float> @shuf_frem_const_op1(<3 x float> %x) { ; CHECK-LABEL: @shuf_frem_const_op1( -; CHECK-NEXT: [[BO:%.*]] = frem reassoc ninf <3 x float> [[X:%.*]], +; CHECK-NEXT: [[BO:%.*]] = frem reassoc <3 x float> [[X:%.*]], ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> ; CHECK-NEXT: ret <3 x float> [[R]] ; diff --git a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll --- a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll @@ -199,7 +199,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr float, float* [[TMP5]], i32 0 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast float* [[TMP6]] to <4 x float>* ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* [[TMP7]], i32 4, <4 x i1> [[TMP4]], <4 x float> poison) -; CHECK-NEXT: [[TMP8:%.*]] = fadd nnan <4 x float> [[WIDE_LOAD]], [[WIDE_MASKED_LOAD]] +; CHECK-NEXT: [[TMP8:%.*]] = fadd <4 x float> [[WIDE_LOAD]], [[WIDE_MASKED_LOAD]] ; entry: br label %for.body @@ -247,7 +247,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr float, float* [[TMP7]], i32 0 ; CHECK-NEXT: [[TMP9:%.*]] = bitcast float* [[TMP8]] to <4 x float>* ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* [[TMP9]], i32 4, <4 x i1> [[TMP6]], <4 x float> poison) -; CHECK-NEXT: [[TMP10:%.*]] = fadd ninf <4 x float> [[WIDE_LOAD]], [[WIDE_MASKED_LOAD]] +; CHECK-NEXT: [[TMP10:%.*]] = fadd <4 x float> [[WIDE_LOAD]], [[WIDE_MASKED_LOAD]] entry: br label %for.body diff --git a/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll b/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll --- a/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll @@ -103,7 +103,7 @@ ; AVX-NEXT: [[TMP3:%.*]] = bitcast double* [[TMP2]] to <4 x double>* ; AVX-NEXT: [[WIDE_LOAD:%.*]] = load <4 x double>, <4 x double>* [[TMP3]], align 8 ; AVX-NEXT: [[TMP4:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD]], -; AVX-NEXT: [[TMP5:%.*]] = fadd fast <4 x double> [[VEC_PHI]], [[WIDE_LOAD]] +; AVX-NEXT: [[TMP5:%.*]] = fadd reassoc nsz arcp contract afn <4 x double> [[VEC_PHI]], [[WIDE_LOAD]] ; AVX-NEXT: [[TMP6:%.*]] = xor <4 x i1> [[TMP4]], ; AVX-NEXT: [[PREDPHI]] = select <4 x i1> [[TMP4]], <4 x double> [[TMP5]], <4 x double> [[VEC_PHI]] ; AVX-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 diff --git a/llvm/test/Transforms/LoopVectorize/if-reduction.ll b/llvm/test/Transforms/LoopVectorize/if-reduction.ll --- a/llvm/test/Transforms/LoopVectorize/if-reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/if-reduction.ll @@ -607,8 +607,8 @@ ; CHECK-LABEL: @fcmp_multi( ; CHECK: %[[C1:.*]] = fcmp ogt <4 x float> %[[V0:.*]], %[[V0]], %[[V0]], %[[V0]], %[[V0]], %[[V0]], %[[C1]], %[[C11]], <4 x i1> %[[C2]], <4 x i1> zeroinitializer ; CHECK-DAG: %[[C21:.*]] = xor <4 x i1> %[[C2]], %[[V0:.*]], %[[V0]], -; CHECK-DAG: %[[ADD:.*]] = fadd fast <4 x float> +; CHECK-DAG: %[[SUB:.*]] = fsub reassoc nsz arcp contract afn <4 x float> +; CHECK-DAG: %[[ADD:.*]] = fadd reassoc nsz arcp contract afn <4 x float> ; CHECK: %[[C11:.*]] = xor <4 x i1> %[[C1]], %[[C11]], <4 x i1> %[[C2]], <4 x i1> zeroinitializer ; CHECK-DAG: %[[C21:.*]] = xor <4 x i1> %[[C2]], [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = xor <4 x i1> [[TMP5]], ; CHECK-NEXT: [[PREDPHI_V:%.*]] = select <4 x i1> [[TMP9]], <4 x float> [[WIDE_LOAD1]], <4 x float> [[WIDE_LOAD]] -; CHECK-NEXT: [[PREDPHI:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[PREDPHI_V]] +; CHECK-NEXT: [[PREDPHI:%.*]] = fadd reassoc nsz arcp contract afn <4 x float> [[VEC_PHI]], [[PREDPHI_V]] ; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP12]], <4 x i1> , <4 x i1> [[TMP11]] ; CHECK-NEXT: [[PREDPHI3]] = select <4 x i1> [[TMP13]], <4 x float> [[VEC_PHI]], <4 x float> [[PREDPHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll --- a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll @@ -820,7 +820,7 @@ ; CHECK-NEXT: [[TMP11:%.*]] = and <4 x i1> [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = xor <4 x i1> [[TMP5]], ; CHECK-NEXT: [[PREDPHI_V:%.*]] = select <4 x i1> [[TMP9]], <4 x float> [[WIDE_LOAD1]], <4 x float> [[WIDE_LOAD]] -; CHECK-NEXT: [[PREDPHI:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[PREDPHI_V]] +; CHECK-NEXT: [[PREDPHI:%.*]] = fadd reassoc nsz arcp contract afn <4 x float> [[VEC_PHI]], [[PREDPHI_V]] ; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP12]], <4 x i1> , <4 x i1> [[TMP11]] ; CHECK-NEXT: [[PREDPHI3]] = select <4 x i1> [[TMP13]], <4 x float> [[VEC_PHI]], <4 x float> [[PREDPHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 diff --git a/llvm/test/Transforms/LoopVectorize/reduction.ll b/llvm/test/Transforms/LoopVectorize/reduction.ll --- a/llvm/test/Transforms/LoopVectorize/reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction.ll @@ -293,7 +293,7 @@ ; We can vectorize conditional reductions with multi-input phis. ; CHECK: reduction_conditional -; CHECK: fadd fast <4 x float> +; CHECK: fadd reassoc nsz arcp contract afn <4 x float> define float @reduction_conditional(float* %A, float* %B, float* %C, float %S) { entry: diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/mve-floatreduce.ll b/llvm/test/Transforms/PhaseOrdering/ARM/mve-floatreduce.ll --- a/llvm/test/Transforms/PhaseOrdering/ARM/mve-floatreduce.ll +++ b/llvm/test/Transforms/PhaseOrdering/ARM/mve-floatreduce.ll @@ -13,7 +13,7 @@ ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[TMP1]] to <4 x i32> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <8 x half> -; CHECK-NEXT: [[TMP5:%.*]] = fadd fast <8 x half> [[TMP1]], [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = fadd reassoc nsz arcp contract afn <8 x half> [[TMP1]], [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x half> [[TMP5]], i32 0 ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x half> [[TMP5]], i32 4 ; CHECK-NEXT: [[ADD:%.*]] = fadd fast half [[TMP6]], [[TMP7]] diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll --- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll @@ -251,9 +251,9 @@ ; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[P:%.*]] to <4 x float>* ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4, !tbaa [[TBAA7:![0-9]+]] ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[TMP1]], [[RDX_SHUF]] +; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd reassoc nsz arcp contract afn <4 x float> [[TMP1]], [[RDX_SHUF]] ; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX4:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF3]] +; CHECK-NEXT: [[BIN_RDX4:%.*]] = fadd reassoc nsz arcp contract afn <4 x float> [[BIN_RDX]], [[RDX_SHUF3]] ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[BIN_RDX4]], i32 0 ; CHECK-NEXT: [[BIN_RDX5:%.*]] = fadd fast float 4.200000e+01, [[TMP2]] ; CHECK-NEXT: ret float [[BIN_RDX5]] @@ -291,9 +291,9 @@ ; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[P:%.*]] to <4 x float>* ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4, !tbaa [[TBAA7]] ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul fast <4 x float> [[TMP1]], [[RDX_SHUF]] +; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul reassoc nsz arcp contract afn <4 x float> [[TMP1]], [[RDX_SHUF]] ; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[BIN_RDX4:%.*]] = fmul fast <4 x float> [[BIN_RDX]], [[RDX_SHUF3]] +; CHECK-NEXT: [[BIN_RDX4:%.*]] = fmul reassoc nsz arcp contract afn <4 x float> [[BIN_RDX]], [[RDX_SHUF3]] ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[BIN_RDX4]], i32 0 ; CHECK-NEXT: [[BIN_RDX5:%.*]] = fmul fast float 1.000000e+00, [[TMP2]] ; CHECK-NEXT: [[OP_EXTRA:%.*]] = fmul fast float [[BIN_RDX5]], 4.200000e+01 @@ -333,10 +333,10 @@ ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4, !tbaa [[TBAA7]] ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> ; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = fcmp fast olt <4 x float> [[TMP1]], [[RDX_SHUF]] -; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select fast <4 x i1> [[RDX_MINMAX_CMP]], <4 x float> [[TMP1]], <4 x float> [[RDX_SHUF]] +; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select reassoc nsz arcp contract afn <4 x i1> [[RDX_MINMAX_CMP]], <4 x float> [[TMP1]], <4 x float> [[RDX_SHUF]] ; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[RDX_MINMAX_SELECT]], <4 x float> poison, <4 x i32> ; CHECK-NEXT: [[RDX_MINMAX_CMP4:%.*]] = fcmp fast olt <4 x float> [[RDX_MINMAX_SELECT]], [[RDX_SHUF3]] -; CHECK-NEXT: [[RDX_MINMAX_SELECT5:%.*]] = select fast <4 x i1> [[RDX_MINMAX_CMP4]], <4 x float> [[RDX_MINMAX_SELECT]], <4 x float> [[RDX_SHUF3]] +; CHECK-NEXT: [[RDX_MINMAX_SELECT5:%.*]] = select reassoc nsz arcp contract afn <4 x i1> [[RDX_MINMAX_CMP4]], <4 x float> [[RDX_MINMAX_SELECT]], <4 x float> [[RDX_SHUF3]] ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[RDX_MINMAX_SELECT5]], i32 0 ; CHECK-NEXT: ret float [[TMP2]] ; @@ -412,13 +412,13 @@ ; CHECK-NEXT: [[V:%.*]] = load <8 x float>, <8 x float>* [[TMP0:%.*]], align 16, !tbaa [[TBAA0]] ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x float> [[V]], <8 x float> poison, <8 x i32> ; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = fcmp nnan ninf nsz ogt <8 x float> [[V]], [[RDX_SHUF]] -; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select nnan ninf nsz <8 x i1> [[RDX_MINMAX_CMP]], <8 x float> [[V]], <8 x float> [[RDX_SHUF]] +; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select nsz <8 x i1> [[RDX_MINMAX_CMP]], <8 x float> [[V]], <8 x float> [[RDX_SHUF]] ; CHECK-NEXT: [[RDX_SHUF8:%.*]] = shufflevector <8 x float> [[RDX_MINMAX_SELECT]], <8 x float> poison, <8 x i32> ; CHECK-NEXT: [[RDX_MINMAX_CMP9:%.*]] = fcmp nnan ninf nsz ogt <8 x float> [[RDX_MINMAX_SELECT]], [[RDX_SHUF8]] -; CHECK-NEXT: [[RDX_MINMAX_SELECT10:%.*]] = select nnan ninf nsz <8 x i1> [[RDX_MINMAX_CMP9]], <8 x float> [[RDX_MINMAX_SELECT]], <8 x float> [[RDX_SHUF8]] +; CHECK-NEXT: [[RDX_MINMAX_SELECT10:%.*]] = select nsz <8 x i1> [[RDX_MINMAX_CMP9]], <8 x float> [[RDX_MINMAX_SELECT]], <8 x float> [[RDX_SHUF8]] ; CHECK-NEXT: [[RDX_SHUF11:%.*]] = shufflevector <8 x float> [[RDX_MINMAX_SELECT10]], <8 x float> poison, <8 x i32> ; CHECK-NEXT: [[RDX_MINMAX_CMP12:%.*]] = fcmp nnan ninf nsz ogt <8 x float> [[RDX_MINMAX_SELECT10]], [[RDX_SHUF11]] -; CHECK-NEXT: [[RDX_MINMAX_SELECT13:%.*]] = select nnan ninf nsz <8 x i1> [[RDX_MINMAX_CMP12]], <8 x float> [[RDX_MINMAX_SELECT10]], <8 x float> [[RDX_SHUF11]] +; CHECK-NEXT: [[RDX_MINMAX_SELECT13:%.*]] = select nsz <8 x i1> [[RDX_MINMAX_CMP12]], <8 x float> [[RDX_MINMAX_SELECT10]], <8 x float> [[RDX_SHUF11]] ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <8 x float> [[RDX_MINMAX_SELECT13]], i32 0 ; CHECK-NEXT: ret float [[TMP1]] ;