diff --git a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll new file mode 100644 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll @@ -0,0 +1,186 @@ +; RUN: opt %s -loop-vectorize -force-vector-width=4 -S | FileCheck %s + +; Make sure that integer poison-generating flags (i.e., nuw/nsw, exact and inbounds) +; are dropped from instructions in blocks that need predication and are linearized and +; masked after vectorization. We need AVX512 target features for the loop to be +; vectorized with masks instead of predicates. + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-pc-linux-gnu" + +; Test for PR52111. +define void @scalar_nuw_nus(float* noalias nocapture readonly %input, + float* %output) local_unnamed_addr #0 { +; CHECK-LABEL: @scalar_nuw_nus( +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, {{.*}} ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , {{.*}} ] +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK: [[TMP4:%.*]] = icmp eq <4 x i64> [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = sub nuw nsw i64 [[TMP0]], 1 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, float* [[INPUT:%.*]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[TMP4]], +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, float* [[TMP6]], i32 0 +; CHECK-NEXT: [[TMP9:%.*]] = bitcast float* [[TMP8]] to <4 x float>* +; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* [[TMP9]], i32 4, <4 x i1> [[TMP7]], <4 x float> poison), !invariant.load !0 +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.inc, %if.end ] + %i23 = icmp eq i64 %iv, 0 + br i1 %i23, label %if.end, label %if.then + +if.then: + %i27 = sub nuw nsw i64 %iv, 1 + %i29 = getelementptr inbounds float, float* %input, i64 %i27 + %i30 = load float, float* %i29, align 4, !invariant.load !0 + br label %if.end + +if.end: + %i34 = phi float [ 0.000000e+00, %loop.header ], [ %i30, %if.then ] + %i35 = getelementptr inbounds float, float* %output, i64 %iv + store float %i34, float* %i35, align 4 + %iv.inc = add nuw nsw i64 %iv, 1 + %exitcond = icmp eq i64 %iv.inc, 4 + br i1 %exitcond, label %loop.exit, label %loop.header + +loop.exit: + ret void +} + +define void @vector_nuw_nus(float* noalias nocapture readonly %input, + float* %output) local_unnamed_addr #0 { +; CHECK-LABEL: @vector_nuw_nus( +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, {{.*}} ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , {{.*}} ] +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK: [[TMP4:%.*]] = icmp eq <4 x i64> [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = sub nuw nsw <4 x i64> [[VEC_IND]], +; CHECK-NEXT: [[TMP6:%.*]] = mul nuw nsw <4 x i64> [[TMP5]], +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, float* [[INPUT:%.*]], <4 x i64> [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = xor <4 x i1> [[TMP4]], +; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> [[TMP7]], i32 4, <4 x i1> [[TMP8]], <4 x float> undef), !invariant.load !0 +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.inc, %if.end ] + %i23 = icmp eq i64 %iv, 0 + br i1 %i23, label %if.end, label %if.then + +if.then: + %i27 = sub nuw nsw i64 %iv, 1 + %i28 = mul nuw nsw i64 %i27, 2 + %i29 = getelementptr inbounds float, float* %input, i64 %i28 + %i30 = load float, float* %i29, align 4, !invariant.load !0 + br label %if.end + +if.end: + %i34 = phi float [ 0.000000e+00, %loop.header ], [ %i30, %if.then ] + %i35 = getelementptr inbounds float, float* %output, i64 %iv + store float %i34, float* %i35, align 4 + %iv.inc = add nuw nsw i64 %iv, 1 + %exitcond = icmp eq i64 %iv.inc, 4 + br i1 %exitcond, label %loop.exit, label %loop.header + +loop.exit: + ret void +} + +define void @scalar_exact(float* noalias nocapture readonly %input, + float* %output) local_unnamed_addr #0 { +; CHECK-LABEL: @scalar_exact( +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, {{.*}} ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , {{.*}} ] +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK: [[TMP4:%.*]] = icmp ne <4 x i64> [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i64> [[VEC_IND]], +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP5]], zeroinitializer +; CHECK-NEXT: [[TMP7:%.*]] = and <4 x i1> [[TMP4]], [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = sdiv exact i64 [[TMP0]], 1 +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, float* [[INPUT:%.*]], i64 [[TMP8]] +; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, float* [[TMP9]], i32 0 +; CHECK-NEXT: [[TMP12:%.*]] = bitcast float* [[TMP11]] to <4 x float>* +; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* [[TMP12]], i32 4, <4 x i1> [[TMP10]], <4 x float> poison), !invariant.load !0 +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.inc, %if.end ] + %i7 = icmp ne i64 %iv, 0 + %i8 = and i64 %iv, 1 + %i9 = icmp eq i64 %i8, 0 + %i10 = and i1 %i7, %i9 + br i1 %i10, label %if.end, label %if.then + +if.then: + %i26 = sdiv exact i64 %iv, 1 + %i29 = getelementptr inbounds float, float* %input, i64 %i26 + %i30 = load float, float* %i29, align 4, !invariant.load !0 + br label %if.end + +if.end: + %i34 = phi float [ 0.000000e+00, %loop.header ], [ %i30, %if.then ] + %i35 = getelementptr inbounds float, float* %output, i64 %iv + store float %i34, float* %i35, align 4 + %iv.inc = add nuw nsw i64 %iv, 1 + %exitcond = icmp eq i64 %iv.inc, 4 + br i1 %exitcond, label %loop.exit, label %loop.header + +loop.exit: + ret void +} + + +define void @vector_exact(float* noalias nocapture readonly %input, + float* %output) local_unnamed_addr #0 { +; CHECK-LABEL: @vector_exact( +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, {{.*}} ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , {{.*}} ] +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK: [[TMP4:%.*]] = icmp ne <4 x i64> [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i64> [[VEC_IND]], +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP5]], zeroinitializer +; CHECK-NEXT: [[TMP7:%.*]] = and <4 x i1> [[TMP4]], [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = sdiv exact <4 x i64> [[VEC_IND]], +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, float* [[INPUT:%.*]], <4 x i64> [[TMP8]] +; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP7]], +; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> [[TMP9]], i32 4, <4 x i1> [[TMP10]], <4 x float> undef), !invariant.load !0 +; +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.inc, %if.end ] + %i7 = icmp ne i64 %iv, 0 + %i8 = and i64 %iv, 1 + %i9 = icmp eq i64 %i8, 0 + %i10 = and i1 %i7, %i9 + br i1 %i10, label %if.end, label %if.then + +if.then: + %i26 = sdiv exact i64 %iv, 2 + %i29 = getelementptr inbounds float, float* %input, i64 %i26 + %i30 = load float, float* %i29, align 4, !invariant.load !0 + br label %if.end + +if.end: + %i34 = phi float [ 0.000000e+00, %loop.header ], [ %i30, %if.then ] + %i35 = getelementptr inbounds float, float* %output, i64 %iv + store float %i34, float* %i35, align 4 + %iv.inc = add nuw nsw i64 %iv, 1 + %exitcond = icmp eq i64 %iv.inc, 4 + br i1 %exitcond, label %loop.exit, label %loop.header + +loop.exit: + ret void +} + +attributes #0 = { noinline nounwind uwtable "target-features"="+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl" } + +!0 = !{}