diff --git a/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp b/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp --- a/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp +++ b/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp @@ -111,9 +111,6 @@ std::array, 32> x_regs; std::array, 32> v_regs; - std::bitset<32> have_w_regs; - std::bitset<32> have_s_regs; - std::bitset<32> have_d_regs; for (auto it : llvm::enumerate(regs)) { lldb_private::DynamicRegisterInfo::Register &info = it.value(); @@ -133,14 +130,11 @@ if (get_reg("x")) x_regs[reg_num] = it.index(); - if (get_reg("v")) + else if (get_reg("v")) v_regs[reg_num] = it.index(); - if (get_reg("w")) - have_w_regs[reg_num] = true; - if (get_reg("s")) - have_s_regs[reg_num] = true; - if (get_reg("d")) - have_d_regs[reg_num] = true; + // if we have at least one subregister, abort + else if (get_reg("w") || get_reg("s") || get_reg("d")) + return; } // Create aliases for partial registers: wN for xN, and sN/dN for vN. diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py b/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py --- a/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py +++ b/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py @@ -582,3 +582,97 @@ self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") self.match("register read s31", ["s31 = 128"]) + + @skipIfXmlSupportMissing + @skipIfRemote + @skipIfLLVMTargetMissing("AArch64") + def test_aarch64_no_duplicate_subregs(self): + """Test that duplicate subregisters are not added.""" + class MyResponder(MockGDBServerResponder): + reg_data = ( + "0102030405060708" # x0 + "1112131415161718" # x1 + ) + 27 * ( + "2122232425262728" # x2..x28 + ) + ( + "3132333435363738" # x29 (fp) + "4142434445464748" # x30 (lr) + "5152535455565758" # x31 (sp) + "6162636465666768" # pc + "71727374" # cpsr + ) + + def qXferRead(self, obj, annex, offset, length): + if annex == "target.xml": + return """ + + + aarch64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + """, False + else: + return None, False + + def readRegister(self, regnum): + return "" + + def readRegisters(self): + return self.reg_data + + def haltReason(self): + return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" + + self.server.responder = MyResponder() + + target = self.createTarget("basic_eh_frame-aarch64.yaml") + process = self.connect(target) + lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, + [lldb.eStateStopped]) + + self.match("register read x0", + ["x0 = 0x0807060504030201"]) + # w0 comes from target.xml + self.match("register read w0", + ["w0 = 0x04030201"]) + self.match("register read x1", + ["x1 = 0x1817161514131211"]) + # w1 should not be added + self.match("register read w1", + ["error: Invalid register name 'w1'."], + error=True)