Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -1653,7 +1653,8 @@
   // The AUTIASP instruction assembles to a hint instruction before v8.3a so
   // this instruction can safely used for any v8a architecture.
   // From v8.3a onwards there are optimised authenticate LR and return
-  // instructions, namely RETA{A,B}, that can be used instead.
+  // instructions, namely RETA{A,B}, that can be used instead. In this case the
+  // DW_CFA_AARCH64_negate_ra_state can't be emitted.
   if (Subtarget.hasPAuth() && MBBI != MBB.end() &&
       MBBI->getOpcode() == AArch64::RET_ReallyLR) {
     BuildMI(MBB, MBBI, DL,
@@ -1665,6 +1666,12 @@
         MBB, MBBI, DL,
         TII->get(MFI.shouldSignWithBKey() ? AArch64::AUTIBSP : AArch64::AUTIASP))
         .setMIFlag(MachineInstr::FrameDestroy);
+
+    unsigned CFIIndex =
+          MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
+      BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+          .addCFIIndex(CFIIndex)
+          .setMIFlags(MachineInstr::FrameSetup);
   }
 }
 
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -7161,7 +7161,8 @@
         .setMIFlags(MachineInstr::FrameSetup);
 
     // If v8.3a features are available we can replace a RET instruction by
-    // RETAA or RETAB and omit the AUT instructions
+    // RETAA or RETAB and omit the AUT instructions. In this case the
+    // DW_CFA_AARCH64_negate_ra_state can't be emitted.
     if (Subtarget.hasPAuth() && MBBAUT != MBB.end() &&
         MBBAUT->getOpcode() == AArch64::RET) {
       BuildMI(MBB, MBBAUT, DL,
@@ -7174,6 +7175,11 @@
               TII->get(ShouldSignReturnAddrWithAKey ? AArch64::AUTIASP
                                                     : AArch64::AUTIBSP))
           .setMIFlag(MachineInstr::FrameDestroy);
+      unsigned CFIIndexAuth =
+          MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
+      BuildMI(MBB, MBBAUT, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+          .addCFIIndex(CFIIndexAuth)
+          .setMIFlags(MachineInstr::FrameSetup);
     }
   }
 }
Index: llvm/test/CodeGen/AArch64/sign-return-address.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sign-return-address.ll
+++ llvm/test/CodeGen/AArch64/sign-return-address.ll
@@ -24,7 +24,9 @@
 
 ; CHECK-LABEL: @leaf_sign_all
 ; CHECK:       hint #25
+; CHECK-NEXT:  .cfi_negate_ra_state
 ; CHECK:       hint #29
+; CHECK-NEXT:  .cfi_negate_ra_state
 ; CHECK:       ret
 ; CHECK-V83A:  pacia x30, sp
 ; CHECK-V83A:  retaa
@@ -34,10 +36,12 @@
 
 ; CHECK:             @leaf_clobbers_lr
 ; CHECK:             hint #25
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK-V83A:        pacia x30, sp
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK:             hint #29
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             ret
 ; CHECK-V32A-NEXT:   retaa
 define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf"  {
@@ -49,7 +53,9 @@
 
 ; CHECK:      @non_leaf_sign_all
 ; CHECK:      hint #25
+; CHECK-NEXT: .cfi_negate_ra_state
 ; CHECK:      hint #29
+; CHECK-NEXT: .cfi_negate_ra_state
 ; CHECK:      ret
 ; CHECK-V83A: pacia x30, sp
 ; CHECK-V83A: retaa
@@ -60,10 +66,12 @@
 
 ; CHECK:             @non_leaf_sign_non_leaf
 ; CHECK:             hint #25
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK-V83A:        pacia x30, sp
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK:             hint #29
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             ret
 ; CHECK-V83A:        retaa
 define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf"  {
@@ -72,10 +80,11 @@
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83
-; CHECK: pacia x30, sp
-; CHECK-NOT: ret
-; CHECK: retaa
-; CHECK-NOT: ret
+; CHECK:        pacia x30, sp
+; CHECK-NEXT:  .cfi_negate_ra_state
+; CHECK-NOT:   ret
+; CHECK:       retaa
+; CHECK-NOT:   ret
 define i32 @leaf_sign_all_v83(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" {
   ret i32 %x
 }
@@ -84,11 +93,14 @@
 
 ; CHECK-LABEL:       @spill_lr_and_tail_call
 ; CHECK:             hint #25
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK-V83A:        pacia x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK-V83A:        autiasp
 ; CHECK:             hint #29
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             b bar
 define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" {
   call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
@@ -97,57 +109,71 @@
 }
 
 ; CHECK-LABEL: @leaf_sign_all_a_key
-; CHECK:       hint #25
-; CHECK:       hint #29
-; CHECK-V83A:  pacia x30, sp
-; CHECK-V83A:  retaa
+; CHECK:            hint #25
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK:            hint #29
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK-V83A:       pacia x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
+; CHECK-V83A:       retaa
 define i32 @leaf_sign_all_a_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_b_key
-; CHECK:       hint #27
-; CHECK:       hint #31
-; CHECK-V83A:  pacib x30, sp
-; CHECK-V83A:  retab
+; CHECK:            hint #27
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK:            hint #31
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK-V83A:       pacib x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
+; CHECK-V83A:       retab
 define i32 @leaf_sign_all_b_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83_b_key
-; CHECK: pacib x30, sp
-; CHECK-NOT: ret
-; CHECK: retab
-; CHECK-NOT: ret
+; CHECK:       pacib x30, sp
+; CHECK-NEXT:  .cfi_negate_ra_state
+; CHECK-NOT:   ret
+; CHECK:       retab
+; CHECK-NOT:   ret
 define i32 @leaf_sign_all_v83_b_key(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_a_key_bti
-; CHECK-NOT:   hint #34
-; CHECK:       hint #25
-; CHECK:       hint #29
-; CHECK-V83A:  pacia x30, sp
-; CHECK-V83A:  retaa
+; CHECK-NOT:        hint #34
+; CHECK:            hint #25
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK:            hint #29
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK-V83A:       pacia x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
+; CHECK-V83A:       retaa
 define i32 @leaf_sign_all_a_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" "branch-target-enforcement"="true"{
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_b_key_bti
-; CHECK-NOT:   hint #34
-; CHECK:       hint #27
-; CHECK:       hint #31
-; CHECK-V83A:  pacib x30, sp
-; CHECK-V83A:  retab
+; CHECK-NOT:        hint #34
+; CHECK:            hint #27
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK:            hint #31
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK-V83A:       pacib x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
+; CHECK-V83A:       retab
 define i32 @leaf_sign_all_b_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" "branch-target-enforcement"="true"{
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83_b_key_bti
 ; CHECK:       pacib x30, sp
-; CHECK-NOT: ret
-; CHECK: retab
-; CHECK-NOT: ret
+; CHECK-NEXT:  .cfi_negate_ra_state
+; CHECK-NOT:   ret
+; CHECK:       retab
+; CHECK-NOT:   ret
 define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" "branch-target-enforcement"="true" {
   ret i32 %x
 }