Index: llvm/test/CodeGen/RISCV/imm.ll =================================================================== --- llvm/test/CodeGen/RISCV/imm.ll +++ llvm/test/CodeGen/RISCV/imm.ll @@ -776,3 +776,38 @@ ; RV64IB-NEXT: ret ret i64 9223354442718100411 ; 0x7fffefff8bbbbbbb } + +define i64 @imm_2863311530() { +; RV32IB-LABEL: imm_2863311530: +; RV32IB: # %bb.0: +; RV32IB-NEXT: lui a0, 699051 +; RV32IB-NEXT: addi a0, a0, -1366 +; RV32IB-NEXT: mv a1, zero +; RV32IB-NEXT: ret +; +; RV64IB-LABEL: imm_2863311530: +; RV64IB: # %bb.0: +; RV64IB-NEXT: lui a0, 699051 +; RV64IB-NEXT: addiw a0, a0, -1366 +; RV64IB-NEXT: zext.w a0, a0 +; RV64IB-NEXT: ret + ret i64 2863311530 ; #0xaaaaaaaa +} + +define i64 @imm_neg_2863311530() { +; RV32IB-LABEL: imm_neg_2863311530: +; RV32IB: # %bb.0: +; RV32IB-NEXT: lui a0, 349525 +; RV32IB-NEXT: addi a0, a0, 1366 +; RV32IB-NEXT: addi a1, zero, -1 +; RV32IB-NEXT: ret +; +; RV64IB-LABEL: imm_neg_2863311530: +; RV64IB: # %bb.0: +; RV64IB-NEXT: lui a0, 1048405 +; RV64IB-NEXT: addiw a0, a0, 1365 +; RV64IB-NEXT: slli a0, a0, 12 +; RV64IB-NEXT: addi a0, a0, 1366 +; RV64IB-NEXT: ret + ret i64 -2863311530 ; #0xffffffff55555556 +}