diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -541,6 +541,7 @@ const RISCVRegisterInfo *RI = STI.getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); + const RISCVInstrInfo *TII = STI.getInstrInfo(); Register FPReg = getFPReg(STI); Register SPReg = getSPReg(STI); @@ -606,6 +607,50 @@ adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount, MachineInstr::FrameDestroy); + + // Emit ".cfi_def_cfa_offset FirstSPAdjustAmount" if using an sp-based CFA + if (!hasFP(MF)) { + unsigned CFIIndex = MF.addFrameInst( + MCCFIInstruction::cfiDefCfaOffset(nullptr, -FirstSPAdjustAmount)); + BuildMI(MBB, LastFrameDestroy, DL, + TII->get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + } + } + + if (hasFP(MF)) { + // To find the instruction restoring FP from stack. + for (auto &I = LastFrameDestroy; I != MBBI; ++I) { + if (I->mayLoad() && I->getOperand(0).isReg()) { + Register DestReg = I->getOperand(0).getReg(); + if (DestReg == FPReg) { + // If there is frame pointer, after restoring $fp registers, we + // need adjust CFA back to the correct sp-based offset. + // Emit ".cfi_def_cfa $sp, CFAOffset" + uint64_t CFAOffset = + FirstSPAdjustAmount + ? FirstSPAdjustAmount + RVFI->getVarArgsSaveSize() + : FPOffset; + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( + nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset)); + BuildMI(MBB, std::next(I), DL, + TII->get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + break; + } + } + } + } + + // Add CFI directives for callee-saved registers. + // Iterate over list of callee-saved registers and emit .cfi_restore + // directives. + for (const auto &Entry : CSI) { + Register Reg = Entry.getReg(); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore( + nullptr, RI->getDwarfRegNum(Reg, true))); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); } if (FirstSPAdjustAmount) @@ -616,6 +661,13 @@ // Emit epilogue for shadow call stack. emitSCSEpilogue(MF, MBB, MBBI, DL); + + // After restoring $sp, we need to adjust CFA to $(sp + 0) + // Emit ".cfi_def_cfa_offset 0" + unsigned CFIIndex = + MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0)); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); } StackOffset diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll b/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll --- a/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll @@ -5,13 +5,16 @@ ; RUN: | FileCheck -check-prefix=RV64I %s define void @foo() { - ; RV32I-LABEL: foo - ; RV32I: # %bb.0: # %entry - ; RV32I: ret +; RV32I-LABEL: foo: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: .cfi_def_cfa_offset 0 +; RV32I-NEXT: ret +; +; RV64I-LABEL: foo: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: .cfi_def_cfa_offset 0 +; RV64I-NEXT: ret - ; RV64I-LABEL: foo - ; RV64I: # %bb.0: # %entry - ; RV64I: ret entry: ret void } diff --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll --- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll +++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll @@ -13,6 +13,7 @@ ; RV32IMB-NEXT: addi a1, zero, 29 ; RV32IMB-NEXT: mul a0, a0, a1 ; RV32IMB-NEXT: addi a0, a0, 1073 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_accept_a1: @@ -20,6 +21,7 @@ ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mulw a0, a0, a1 ; RV64IMB-NEXT: addiw a0, a0, 1073 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 37 %tmp1 = mul i32 %tmp0, 29 @@ -32,6 +34,7 @@ ; RV32IMB-NEXT: addi a1, zero, 29 ; RV32IMB-NEXT: mul a0, a0, a1 ; RV32IMB-NEXT: addi a0, a0, 1073 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_accept_a2: @@ -39,6 +42,7 @@ ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mulw a0, a0, a1 ; RV64IMB-NEXT: addiw a0, a0, 1073 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 37 %tmp1 = mul i32 %tmp0, 29 @@ -56,6 +60,7 @@ ; RV32IMB-NEXT: addi a0, a2, 1073 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_accept_a3: @@ -63,6 +68,7 @@ ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mul a0, a0, a1 ; RV64IMB-NEXT: addi a0, a0, 1073 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i64 %x, 37 %tmp1 = mul i64 %tmp0, 29 @@ -77,6 +83,7 @@ ; RV32IMB-NEXT: lui a1, 50 ; RV32IMB-NEXT: addi a1, a1, 1119 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_accept_b1: @@ -86,6 +93,7 @@ ; RV64IMB-NEXT: lui a1, 50 ; RV64IMB-NEXT: addiw a1, a1, 1119 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 8953 %tmp1 = mul i32 %tmp0, 23 @@ -100,6 +108,7 @@ ; RV32IMB-NEXT: lui a1, 50 ; RV32IMB-NEXT: addi a1, a1, 1119 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_accept_b2: @@ -109,6 +118,7 @@ ; RV64IMB-NEXT: lui a1, 50 ; RV64IMB-NEXT: addiw a1, a1, 1119 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 8953 %tmp1 = mul i32 %tmp0, 23 @@ -128,6 +138,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_accept_b3: @@ -137,6 +148,7 @@ ; RV64IMB-NEXT: lui a1, 50 ; RV64IMB-NEXT: addiw a1, a1, 1119 ; RV64IMB-NEXT: add a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i64 %x, 8953 %tmp1 = mul i64 %tmp0, 23 @@ -149,6 +161,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1971 ; RV32IMB-NEXT: addi a1, zero, 29 ; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_a1: @@ -156,6 +169,7 @@ ; RV64IMB-NEXT: addiw a0, a0, 1971 ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mulw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 1971 %tmp1 = mul i32 %tmp0, 29 @@ -168,6 +182,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1971 ; RV32IMB-NEXT: addi a1, zero, 29 ; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_a2: @@ -175,6 +190,7 @@ ; RV64IMB-NEXT: addiw a0, a0, 1971 ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mulw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 1971 %tmp1 = mul i32 %tmp0, 29 @@ -194,6 +210,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_a3: @@ -201,6 +218,7 @@ ; RV64IMB-NEXT: addi a0, a0, 1971 ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i64 %x, 1971 %tmp1 = mul i64 %tmp0, 29 @@ -213,6 +231,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1000 ; RV32IMB-NEXT: sh3add a1, a0, a0 ; RV32IMB-NEXT: sh3add a0, a1, a0 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_c1: @@ -221,6 +240,7 @@ ; RV64IMB-NEXT: sh3add a1, a0, a0 ; RV64IMB-NEXT: sh3add a0, a1, a0 ; RV64IMB-NEXT: sext.w a0, a0 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 1000 %tmp1 = mul i32 %tmp0, 73 @@ -233,6 +253,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1000 ; RV32IMB-NEXT: sh3add a1, a0, a0 ; RV32IMB-NEXT: sh3add a0, a1, a0 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_c2: @@ -241,6 +262,7 @@ ; RV64IMB-NEXT: sh3add a1, a0, a0 ; RV64IMB-NEXT: sh3add a0, a1, a0 ; RV64IMB-NEXT: sext.w a0, a0 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 1000 %tmp1 = mul i32 %tmp0, 73 @@ -260,6 +282,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_c3: @@ -267,6 +290,7 @@ ; RV64IMB-NEXT: addi a0, a0, 1000 ; RV64IMB-NEXT: sh3add a1, a0, a0 ; RV64IMB-NEXT: sh3add a0, a1, a0 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i64 %x, 1000 %tmp1 = mul i64 %tmp0, 73 @@ -279,6 +303,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1000 ; RV32IMB-NEXT: sh1add a0, a0, a0 ; RV32IMB-NEXT: slli a0, a0, 6 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_d1: @@ -286,6 +311,7 @@ ; RV64IMB-NEXT: addi a0, a0, 1000 ; RV64IMB-NEXT: sh1add a0, a0, a0 ; RV64IMB-NEXT: slliw a0, a0, 6 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 1000 %tmp1 = mul i32 %tmp0, 192 @@ -298,6 +324,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1000 ; RV32IMB-NEXT: sh1add a0, a0, a0 ; RV32IMB-NEXT: slli a0, a0, 6 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_d2: @@ -305,6 +332,7 @@ ; RV64IMB-NEXT: addi a0, a0, 1000 ; RV64IMB-NEXT: sh1add a0, a0, a0 ; RV64IMB-NEXT: slliw a0, a0, 6 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 1000 %tmp1 = mul i32 %tmp0, 192 @@ -326,6 +354,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_d3: @@ -333,6 +362,7 @@ ; RV64IMB-NEXT: addi a0, a0, 1000 ; RV64IMB-NEXT: sh1add a0, a0, a0 ; RV64IMB-NEXT: slli a0, a0, 6 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = add i64 %x, 1000 %tmp1 = mul i64 %tmp0, 192 @@ -345,6 +375,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1971 ; RV32IMB-NEXT: addi a1, zero, 29 ; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_e1: @@ -352,6 +383,7 @@ ; RV64IMB-NEXT: addiw a0, a0, 1971 ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mulw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 29 %tmp1 = add i32 %tmp0, 57159 @@ -364,6 +396,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1971 ; RV32IMB-NEXT: addi a1, zero, 29 ; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_e2: @@ -371,6 +404,7 @@ ; RV64IMB-NEXT: addiw a0, a0, 1971 ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mulw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 29 %tmp1 = add i32 %tmp0, 57159 @@ -390,6 +424,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_e3: @@ -397,6 +432,7 @@ ; RV64IMB-NEXT: addi a0, a0, 1971 ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 29 %tmp1 = add i64 %tmp0, 57159 @@ -410,6 +446,7 @@ ; RV32IMB-NEXT: addi a1, zero, 29 ; RV32IMB-NEXT: mul a0, a0, a1 ; RV32IMB-NEXT: addi a0, a0, 11 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_f1: @@ -418,6 +455,7 @@ ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mulw a0, a0, a1 ; RV64IMB-NEXT: addiw a0, a0, 11 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 29 %tmp1 = add i32 %tmp0, 57199 @@ -431,6 +469,7 @@ ; RV32IMB-NEXT: addi a1, zero, 29 ; RV32IMB-NEXT: mul a0, a0, a1 ; RV32IMB-NEXT: addi a0, a0, 11 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_f2: @@ -439,6 +478,7 @@ ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mulw a0, a0, a1 ; RV64IMB-NEXT: addiw a0, a0, 11 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 29 %tmp1 = add i32 %tmp0, 57199 @@ -458,6 +498,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_f3: @@ -466,6 +507,7 @@ ; RV64IMB-NEXT: addi a1, zero, 29 ; RV64IMB-NEXT: mul a0, a0, a1 ; RV64IMB-NEXT: addi a0, a0, 11 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 29 %tmp1 = add i64 %tmp0, 57199 @@ -479,6 +521,7 @@ ; RV32IMB-NEXT: sh3add a1, a0, a0 ; RV32IMB-NEXT: sh3add a0, a1, a0 ; RV32IMB-NEXT: addi a0, a0, 10 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_g1: @@ -487,6 +530,7 @@ ; RV64IMB-NEXT: sh3add a1, a0, a0 ; RV64IMB-NEXT: sh3add a0, a1, a0 ; RV64IMB-NEXT: addiw a0, a0, 10 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 73 %tmp1 = add i32 %tmp0, 7310 @@ -500,6 +544,7 @@ ; RV32IMB-NEXT: sh3add a1, a0, a0 ; RV32IMB-NEXT: sh3add a0, a1, a0 ; RV32IMB-NEXT: addi a0, a0, 10 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_g2: @@ -508,6 +553,7 @@ ; RV64IMB-NEXT: sh3add a1, a0, a0 ; RV64IMB-NEXT: sh3add a0, a1, a0 ; RV64IMB-NEXT: addiw a0, a0, 10 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 73 %tmp1 = add i32 %tmp0, 7310 @@ -527,6 +573,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_g3: @@ -535,6 +582,7 @@ ; RV64IMB-NEXT: sh3add a1, a0, a0 ; RV64IMB-NEXT: sh3add a0, a1, a0 ; RV64IMB-NEXT: addi a0, a0, 10 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 73 %tmp1 = add i64 %tmp0, 7310 @@ -555,6 +603,7 @@ ; RV32IMB-NEXT: addi a0, a0, 1024 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_infinite_loop: @@ -563,6 +612,7 @@ ; RV64IMB-NEXT: lui a1, 1 ; RV64IMB-NEXT: addiw a1, a1, -2048 ; RV64IMB-NEXT: sh3add a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 24 %tmp1 = add i64 %tmp0, 2048 @@ -578,6 +628,7 @@ ; RV32IMB-NEXT: lui a1, 2 ; RV32IMB-NEXT: addi a1, a1, 798 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mul3000_add8990_a: @@ -588,6 +639,7 @@ ; RV64IMB-NEXT: lui a1, 2 ; RV64IMB-NEXT: addiw a1, a1, 798 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 3000 %tmp1 = add i32 %tmp0, 8990 @@ -603,6 +655,7 @@ ; RV32IMB-NEXT: lui a1, 2 ; RV32IMB-NEXT: addi a1, a1, 798 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mul3000_add8990_b: @@ -613,6 +666,7 @@ ; RV64IMB-NEXT: lui a1, 2 ; RV64IMB-NEXT: addiw a1, a1, 798 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 3000 %tmp1 = add i32 %tmp0, 8990 @@ -633,6 +687,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mul3000_add8990_c: @@ -643,6 +698,7 @@ ; RV64IMB-NEXT: lui a1, 2 ; RV64IMB-NEXT: addiw a1, a1, 798 ; RV64IMB-NEXT: add a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 3000 %tmp1 = add i64 %tmp0, 8990 @@ -658,6 +714,7 @@ ; RV32IMB-NEXT: lui a1, 1048574 ; RV32IMB-NEXT: addi a1, a1, -798 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mul3000_sub8990_a: @@ -668,6 +725,7 @@ ; RV64IMB-NEXT: lui a1, 1048574 ; RV64IMB-NEXT: addiw a1, a1, -798 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 3000 %tmp1 = add i32 %tmp0, -8990 @@ -683,6 +741,7 @@ ; RV32IMB-NEXT: lui a1, 1048574 ; RV32IMB-NEXT: addi a1, a1, -798 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mul3000_sub8990_b: @@ -693,6 +752,7 @@ ; RV64IMB-NEXT: lui a1, 1048574 ; RV64IMB-NEXT: addiw a1, a1, -798 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 3000 %tmp1 = add i32 %tmp0, -8990 @@ -714,6 +774,7 @@ ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 ; RV32IMB-NEXT: addi a1, a1, -1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mul3000_sub8990_c: @@ -724,6 +785,7 @@ ; RV64IMB-NEXT: lui a1, 1048574 ; RV64IMB-NEXT: addiw a1, a1, -798 ; RV64IMB-NEXT: add a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 3000 %tmp1 = add i64 %tmp0, -8990 @@ -739,6 +801,7 @@ ; RV32IMB-NEXT: lui a1, 2 ; RV32IMB-NEXT: addi a1, a1, 798 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mulneg3000_add8990_a: @@ -749,6 +812,7 @@ ; RV64IMB-NEXT: lui a1, 2 ; RV64IMB-NEXT: addiw a1, a1, 798 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, -3000 %tmp1 = add i32 %tmp0, 8990 @@ -764,6 +828,7 @@ ; RV32IMB-NEXT: lui a1, 2 ; RV32IMB-NEXT: addi a1, a1, 798 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mulneg3000_add8990_b: @@ -774,6 +839,7 @@ ; RV64IMB-NEXT: lui a1, 2 ; RV64IMB-NEXT: addiw a1, a1, 798 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, -3000 %tmp1 = add i32 %tmp0, 8990 @@ -795,6 +861,7 @@ ; RV32IMB-NEXT: add a0, a2, a0 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mulneg3000_add8990_c: @@ -805,6 +872,7 @@ ; RV64IMB-NEXT: lui a1, 2 ; RV64IMB-NEXT: addiw a1, a1, 798 ; RV64IMB-NEXT: add a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, -3000 %tmp1 = add i64 %tmp0, 8990 @@ -820,6 +888,7 @@ ; RV32IMB-NEXT: lui a1, 1048574 ; RV32IMB-NEXT: addi a1, a1, -798 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mulneg3000_sub8990_a: @@ -830,6 +899,7 @@ ; RV64IMB-NEXT: lui a1, 1048574 ; RV64IMB-NEXT: addiw a1, a1, -798 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, -3000 %tmp1 = add i32 %tmp0, -8990 @@ -845,6 +915,7 @@ ; RV32IMB-NEXT: lui a1, 1048574 ; RV32IMB-NEXT: addi a1, a1, -798 ; RV32IMB-NEXT: add a0, a0, a1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mulneg3000_sub8990_b: @@ -855,6 +926,7 @@ ; RV64IMB-NEXT: lui a1, 1048574 ; RV64IMB-NEXT: addiw a1, a1, -798 ; RV64IMB-NEXT: addw a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, -3000 %tmp1 = add i32 %tmp0, -8990 @@ -877,6 +949,7 @@ ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 ; RV32IMB-NEXT: addi a1, a1, -1 +; RV32IMB-NEXT: .cfi_def_cfa_offset 0 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: mulneg3000_sub8990_c: @@ -887,6 +960,7 @@ ; RV64IMB-NEXT: lui a1, 1048574 ; RV64IMB-NEXT: addiw a1, a1, -798 ; RV64IMB-NEXT: add a0, a0, a1 +; RV64IMB-NEXT: .cfi_def_cfa_offset 0 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, -3000 %tmp1 = add i64 %tmp0, -8990 diff --git a/llvm/test/CodeGen/RISCV/addrspacecast.ll b/llvm/test/CodeGen/RISCV/addrspacecast.ll --- a/llvm/test/CodeGen/RISCV/addrspacecast.ll +++ b/llvm/test/CodeGen/RISCV/addrspacecast.ll @@ -8,11 +8,13 @@ ; RV32I-LABEL: cast0: ; RV32I: # %bb.0: ; RV32I-NEXT: sw zero, 0(a0) +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: cast0: ; RV64I: # %bb.0: ; RV64I-NEXT: sw zero, 0(a0) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret %ptr0 = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(0)* store i32 0, i32* %ptr0 @@ -28,7 +30,9 @@ ; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: call foo@plt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: .cfi_restore ra ; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: cast1: @@ -39,7 +43,9 @@ ; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: call foo@plt ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: .cfi_restore ra ; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret %castptr = addrspacecast i32* %ptr to i32 addrspace(10)* call void @foo(i32 addrspace(10)* %castptr) diff --git a/llvm/test/CodeGen/RISCV/aext-to-sext.ll b/llvm/test/CodeGen/RISCV/aext-to-sext.ll --- a/llvm/test/CodeGen/RISCV/aext-to-sext.ll +++ b/llvm/test/CodeGen/RISCV/aext-to-sext.ll @@ -62,6 +62,7 @@ ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: beq a0, a1, .LBB1_1 ; RV64I-NEXT: # %bb.2: # %bar +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret br label %bb diff --git a/llvm/test/CodeGen/RISCV/alu32.ll b/llvm/test/CodeGen/RISCV/alu32.ll --- a/llvm/test/CodeGen/RISCV/alu32.ll +++ b/llvm/test/CodeGen/RISCV/alu32.ll @@ -133,12 +133,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: srli a0, a0, 3 ; RV32I-NEXT: ori a0, a0, 1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: srli_demandedbits: ; RV64I: # %bb.0: ; RV64I-NEXT: srliw a0, a0, 3 ; RV64I-NEXT: ori a0, a0, 1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret %2 = lshr i32 %0, 3 %3 = or i32 %2, 1 diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll --- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll +++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll @@ -1286,6 +1286,7 @@ ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: andi a0, a0, 1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_parity_i32: @@ -1303,6 +1304,7 @@ ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: andi a0, a0, 1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ctpop.i32(i32 %a) %2 = and i32 %1, 1 @@ -1325,6 +1327,7 @@ ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: mv a1, zero +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_parity_i64: @@ -1342,6 +1345,7 @@ ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: andi a0, a0, 1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret %1 = call i64 @llvm.ctpop.i64(i64 %a) %2 = and i64 %1, 1 diff --git a/llvm/test/CodeGen/RISCV/byval.ll b/llvm/test/CodeGen/RISCV/byval.ll --- a/llvm/test/CodeGen/RISCV/byval.ll +++ b/llvm/test/CodeGen/RISCV/byval.ll @@ -33,7 +33,7 @@ ; RV32I-NEXT: lw a0, 4(a0) ; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: addi a0, sp, 12 -; RV32I-NEXT: call callee +; RV32I-NEXT: call callee@plt ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll b/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll --- a/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll @@ -15,12 +15,14 @@ ; RV64-NEXT: fadd.s ft0, ft1, ft0 ; RV64-NEXT: fmv.x.w a0, ft0 ; RV64-NEXT: fmv.x.w a1, ft2 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ; ; RV64LP64F-LABEL: callee_v2f32: ; RV64LP64F: # %bb.0: ; RV64LP64F-NEXT: fadd.s fa0, fa0, fa2 ; RV64LP64F-NEXT: fadd.s fa1, fa1, fa3 +; RV64LP64F-NEXT: .cfi_def_cfa_offset 0 ; RV64LP64F-NEXT: ret %z = fadd <2 x float> %x, %y ret <2 x float> %z @@ -45,6 +47,7 @@ ; RV64-NEXT: fsw ft1, 8(a0) ; RV64-NEXT: fsw ft3, 4(a0) ; RV64-NEXT: fsw ft5, 0(a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ; ; RV64LP64F-LABEL: callee_v4f32: @@ -57,6 +60,7 @@ ; RV64LP64F-NEXT: fsw ft2, 8(a0) ; RV64LP64F-NEXT: fsw ft1, 4(a0) ; RV64LP64F-NEXT: fsw ft0, 0(a0) +; RV64LP64F-NEXT: .cfi_def_cfa_offset 0 ; RV64LP64F-NEXT: ret %z = fadd <4 x float> %x, %y ret <4 x float> %z diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll --- a/llvm/test/CodeGen/RISCV/calls.ll +++ b/llvm/test/CodeGen/RISCV/calls.ll @@ -71,7 +71,7 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call defined_function +; RV32I-NEXT: call defined_function@plt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -178,7 +178,7 @@ ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: call fastcc_function +; RV32I-NEXT: call fastcc_function@plt ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -282,7 +282,7 @@ ; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a7, a0 -; RV32I-NEXT: call defined_many_args +; RV32I-NEXT: call defined_many_args@plt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/copy-frameindex.mir b/llvm/test/CodeGen/RISCV/copy-frameindex.mir --- a/llvm/test/CodeGen/RISCV/copy-frameindex.mir +++ b/llvm/test/CodeGen/RISCV/copy-frameindex.mir @@ -39,15 +39,19 @@ body: | ; CHECK-LABEL: name: sink_addi_fi ; CHECK: bb.0: - ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) - ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10 - ; CHECK: BEQ killed [[COPY]], $x0, %bb.2 - ; CHECK: bb.1: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0 - ; CHECK: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0) - ; CHECK: bb.2: - ; CHECK: PseudoRET + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: BEQ killed [[COPY]], $x0, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0 + ; CHECK-NEXT: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoRET bb.0: liveins: $x10 %0:gpr = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -144,6 +144,7 @@ ; RV32IFD-NEXT: mv a0, a1 ; RV32IFD-NEXT: .LBB5_2: ; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: .cfi_def_cfa_offset 0 ; RV32IFD-NEXT: ret ; ; RV64IFD-LABEL: fcvt_wu_d_multiple_use: @@ -155,6 +156,7 @@ ; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: mv a0, a1 ; RV64IFD-NEXT: .LBB5_2: +; RV64IFD-NEXT: .cfi_def_cfa_offset 0 ; RV64IFD-NEXT: ret %a = fptoui double %x to i32 %b = icmp eq i32 %a, 0 @@ -639,6 +641,7 @@ ; RV32IFD-NEXT: addi a0, a0, 1 ; RV32IFD-NEXT: fcvt.d.w ft0, a0 ; RV32IFD-NEXT: fsd ft0, 0(a1) +; RV32IFD-NEXT: .cfi_def_cfa_offset 0 ; RV32IFD-NEXT: ret ; ; RV64IFD-LABEL: fcvt_d_w_demanded_bits: @@ -646,6 +649,7 @@ ; RV64IFD-NEXT: addiw a0, a0, 1 ; RV64IFD-NEXT: fcvt.d.w ft0, a0 ; RV64IFD-NEXT: fsd ft0, 0(a1) +; RV64IFD-NEXT: .cfi_def_cfa_offset 0 ; RV64IFD-NEXT: ret %3 = add i32 %0, 1 %4 = sitofp i32 %3 to double @@ -660,6 +664,7 @@ ; RV32IFD-NEXT: addi a0, a0, 1 ; RV32IFD-NEXT: fcvt.d.wu ft0, a0 ; RV32IFD-NEXT: fsd ft0, 0(a1) +; RV32IFD-NEXT: .cfi_def_cfa_offset 0 ; RV32IFD-NEXT: ret ; ; RV64IFD-LABEL: fcvt_d_wu_demanded_bits: @@ -667,6 +672,7 @@ ; RV64IFD-NEXT: addiw a0, a0, 1 ; RV64IFD-NEXT: fcvt.d.wu ft0, a0 ; RV64IFD-NEXT: fsd ft0, 0(a1) +; RV64IFD-NEXT: .cfi_def_cfa_offset 0 ; RV64IFD-NEXT: ret %3 = add i32 %0, 1 %4 = uitofp i32 %3 to double diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -19,7 +19,7 @@ ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: mv a0, zero -; RV32IFD-NEXT: call test +; RV32IFD-NEXT: call test@plt ; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: fld ft0, 0(sp) diff --git a/llvm/test/CodeGen/RISCV/exception-pointer-register.ll b/llvm/test/CodeGen/RISCV/exception-pointer-register.ll --- a/llvm/test/CodeGen/RISCV/exception-pointer-register.ll +++ b/llvm/test/CodeGen/RISCV/exception-pointer-register.ll @@ -40,7 +40,11 @@ ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: .cfi_restore ra +; RV32I-NEXT: .cfi_restore s0 +; RV32I-NEXT: .cfi_restore s1 ; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB0_4: # %lpad ; RV32I-NEXT: .Ltmp4: @@ -77,7 +81,11 @@ ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: .cfi_restore ra +; RV64I-NEXT: .cfi_restore s0 +; RV64I-NEXT: .cfi_restore s1 ; RV64I-NEXT: addi sp, sp, 32 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB0_4: # %lpad ; RV64I-NEXT: .Ltmp4: @@ -111,10 +119,12 @@ define internal void @callee(i1* %p) { ; RV32I-LABEL: callee: ; RV32I: # %bb.0: +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: callee: ; RV64I: # %bb.0: +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ret void } diff --git a/llvm/test/CodeGen/RISCV/fastcc-int.ll b/llvm/test/CodeGen/RISCV/fastcc-int.ll --- a/llvm/test/CodeGen/RISCV/fastcc-int.ll +++ b/llvm/test/CodeGen/RISCV/fastcc-int.ll @@ -44,7 +44,7 @@ ; RV32-NEXT: sw s0, 4(sp) ; RV32-NEXT: sw t1, 0(sp) ; RV32-NEXT: mv a0, t0 -; RV32-NEXT: call callee +; RV32-NEXT: call callee@plt ; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 32 @@ -75,7 +75,7 @@ ; RV64-NEXT: sd s0, 8(sp) ; RV64-NEXT: sd t1, 0(sp) ; RV64-NEXT: mv a0, t0 -; RV64-NEXT: call callee +; RV64-NEXT: call callee@plt ; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 48 diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -82,6 +82,7 @@ ; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: mv a0, a1 ; RV32IF-NEXT: .LBB3_2: +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fcvt_wu_s_multiple_use: @@ -93,6 +94,7 @@ ; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: mv a0, a1 ; RV64IF-NEXT: .LBB3_2: +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret %a = fptoui float %x to i32 %b = icmp eq i32 %a, 0 @@ -526,6 +528,7 @@ ; RV32IF-NEXT: addi a0, a0, 1 ; RV32IF-NEXT: fcvt.s.w ft0, a0 ; RV32IF-NEXT: fsw ft0, 0(a1) +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fcvt_s_w_demanded_bits: @@ -533,6 +536,7 @@ ; RV64IF-NEXT: addiw a0, a0, 1 ; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fsw ft0, 0(a1) +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret %3 = add i32 %0, 1 %4 = sitofp i32 %3 to float @@ -547,6 +551,7 @@ ; RV32IF-NEXT: addi a0, a0, 1 ; RV32IF-NEXT: fcvt.s.wu ft0, a0 ; RV32IF-NEXT: fsw ft0, 0(a1) +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fcvt_s_wu_demanded_bits: @@ -554,6 +559,7 @@ ; RV64IF-NEXT: addiw a0, a0, 1 ; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fsw ft0, 0(a1) +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret %3 = add i32 %0, 1 %4 = uitofp i32 %3 to float diff --git a/llvm/test/CodeGen/RISCV/fpenv.ll b/llvm/test/CodeGen/RISCV/fpenv.ll --- a/llvm/test/CodeGen/RISCV/fpenv.ll +++ b/llvm/test/CodeGen/RISCV/fpenv.ll @@ -11,6 +11,7 @@ ; RV32IF-NEXT: addi a1, a1, 769 ; RV32IF-NEXT: srl a0, a1, a0 ; RV32IF-NEXT: andi a0, a0, 7 +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: func_01: @@ -21,6 +22,7 @@ ; RV64IF-NEXT: addiw a1, a1, 769 ; RV64IF-NEXT: srl a0, a1, a0 ; RV64IF-NEXT: andi a0, a0, 7 +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret %rm = call i32 @llvm.flt.rounds() ret i32 %rm @@ -35,6 +37,7 @@ ; RV32IF-NEXT: srl a0, a1, a0 ; RV32IF-NEXT: andi a0, a0, 7 ; RV32IF-NEXT: fsrm a0 +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: func_02: @@ -46,6 +49,7 @@ ; RV64IF-NEXT: srl a0, a1, a0 ; RV64IF-NEXT: andi a0, a0, 7 ; RV64IF-NEXT: fsrm a0 +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret call void @llvm.set.rounding(i32 %rm) ret void @@ -55,11 +59,13 @@ ; RV32IF-LABEL: func_03: ; RV32IF: # %bb.0: ; RV32IF-NEXT: fsrmi 1 +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: func_03: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fsrmi 1 +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret call void @llvm.set.rounding(i32 0) ret void @@ -69,11 +75,13 @@ ; RV32IF-LABEL: func_04: ; RV32IF: # %bb.0: ; RV32IF-NEXT: fsrmi 0 +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: func_04: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fsrmi 0 +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret call void @llvm.set.rounding(i32 1) ret void @@ -83,11 +91,13 @@ ; RV32IF-LABEL: func_05: ; RV32IF: # %bb.0: ; RV32IF-NEXT: fsrmi 3 +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: func_05: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fsrmi 3 +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret call void @llvm.set.rounding(i32 2) ret void @@ -97,11 +107,13 @@ ; RV32IF-LABEL: func_06: ; RV32IF: # %bb.0: ; RV32IF-NEXT: fsrmi 2 +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: func_06: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fsrmi 2 +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret call void @llvm.set.rounding(i32 3) ret void @@ -111,11 +123,13 @@ ; RV32IF-LABEL: func_07: ; RV32IF: # %bb.0: ; RV32IF-NEXT: fsrmi 4 +; RV32IF-NEXT: .cfi_def_cfa_offset 0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: func_07: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fsrmi 4 +; RV64IF-NEXT: .cfi_def_cfa_offset 0 ; RV64IF-NEXT: ret call void @llvm.set.rounding(i32 4) ret void diff --git a/llvm/test/CodeGen/RISCV/frame-info.ll b/llvm/test/CodeGen/RISCV/frame-info.ll --- a/llvm/test/CodeGen/RISCV/frame-info.ll +++ b/llvm/test/CodeGen/RISCV/frame-info.ll @@ -11,10 +11,12 @@ define void @trivial() { ; RV32-LABEL: trivial: ; RV32: # %bb.0: +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: trivial: ; RV64: # %bb.0: +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ; ; RV32-WITHFP-LABEL: trivial: @@ -28,8 +30,12 @@ ; RV32-WITHFP-NEXT: addi s0, sp, 16 ; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16 ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32-WITHFP-NEXT: .cfi_restore ra +; RV32-WITHFP-NEXT: .cfi_restore s0 ; RV32-WITHFP-NEXT: addi sp, sp, 16 +; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV32-WITHFP-NEXT: ret ; ; RV64-WITHFP-LABEL: trivial: @@ -43,8 +49,12 @@ ; RV64-WITHFP-NEXT: addi s0, sp, 16 ; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16 ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-WITHFP-NEXT: .cfi_restore ra +; RV64-WITHFP-NEXT: .cfi_restore s0 ; RV64-WITHFP-NEXT: addi sp, sp, 16 +; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV64-WITHFP-NEXT: ret ret void } @@ -67,8 +77,12 @@ ; RV32-NEXT: call callee_with_args@plt ; RV32-NEXT: addi sp, s0, -16 ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32-NEXT: .cfi_def_cfa sp, 16 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32-NEXT: .cfi_restore ra +; RV32-NEXT: .cfi_restore s0 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: stack_alloc: @@ -90,8 +104,12 @@ ; RV64-NEXT: call callee_with_args@plt ; RV64-NEXT: addi sp, s0, -16 ; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64-NEXT: .cfi_def_cfa sp, 16 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-NEXT: .cfi_restore ra +; RV64-NEXT: .cfi_restore s0 ; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ; ; RV32-WITHFP-LABEL: stack_alloc: @@ -111,8 +129,12 @@ ; RV32-WITHFP-NEXT: call callee_with_args@plt ; RV32-WITHFP-NEXT: addi sp, s0, -16 ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16 ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32-WITHFP-NEXT: .cfi_restore ra +; RV32-WITHFP-NEXT: .cfi_restore s0 ; RV32-WITHFP-NEXT: addi sp, sp, 16 +; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV32-WITHFP-NEXT: ret ; ; RV64-WITHFP-LABEL: stack_alloc: @@ -134,8 +156,12 @@ ; RV64-WITHFP-NEXT: call callee_with_args@plt ; RV64-WITHFP-NEXT: addi sp, s0, -16 ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16 ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-WITHFP-NEXT: .cfi_restore ra +; RV64-WITHFP-NEXT: .cfi_restore s0 ; RV64-WITHFP-NEXT: addi sp, sp, 16 +; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV64-WITHFP-NEXT: ret entry: %0 = alloca i8, i32 %size, align 16 @@ -157,7 +183,9 @@ ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: call callee2@plt ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32-NEXT: .cfi_restore ra ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: branch_and_tail_call: @@ -173,7 +201,9 @@ ; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: call callee2@plt ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-NEXT: .cfi_restore ra ; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: cfi_def_cfa_offset 0 ; RV64-NEXT: ret ; ; RV32-WITHFP-LABEL: branch_and_tail_call: @@ -193,8 +223,12 @@ ; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV32-WITHFP-NEXT: call callee2@plt ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16 ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32-WITHFP-NEXT: .cfi_restore ra +; RV32-WITHFP-NEXT: .cfi_restore s0 ; RV32-WITHFP-NEXT: addi sp, sp, 16 +; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV32-WITHFP-NEXT: ret ; ; RV64-WITHFP-LABEL: branch_and_tail_call: @@ -214,8 +248,12 @@ ; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV64-WITHFP-NEXT: call callee2@plt ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16 ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-WITHFP-NEXT: .cfi_restore ra +; RV64-WITHFP-NEXT: .cfi_restore s0 ; RV64-WITHFP-NEXT: addi sp, sp, 16 +; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV64-WITHFP-NEXT: ret br i1 %a, label %blue_pill, label %red_pill blue_pill: diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -146,6 +146,7 @@ ; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: mv a0, a1 ; RV32IZFH-NEXT: .LBB3_2: +; RV32IZFH-NEXT: .cfi_def_cfa_offset 0 ; RV32IZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_ui_h_multiple_use: @@ -156,6 +157,7 @@ ; RV32IDZFH-NEXT: # %bb.1: ; RV32IDZFH-NEXT: mv a0, a1 ; RV32IDZFH-NEXT: .LBB3_2: +; RV32IDZFH-NEXT: .cfi_def_cfa_offset 0 ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_ui_h_multiple_use: @@ -166,6 +168,7 @@ ; RV64IZFH-NEXT: # %bb.1: ; RV64IZFH-NEXT: mv a0, a1 ; RV64IZFH-NEXT: .LBB3_2: +; RV64IZFH-NEXT: .cfi_def_cfa_offset 0 ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_ui_h_multiple_use: @@ -176,6 +179,7 @@ ; RV64IDZFH-NEXT: # %bb.1: ; RV64IDZFH-NEXT: mv a0, a1 ; RV64IDZFH-NEXT: .LBB3_2: +; RV64IDZFH-NEXT: .cfi_def_cfa_offset 0 ; RV64IDZFH-NEXT: ret %a = fptoui half %x to i32 %b = icmp eq i32 %a, 0 @@ -1154,6 +1158,7 @@ ; RV32IZFH-NEXT: addi a0, a0, 1 ; RV32IZFH-NEXT: fcvt.h.w ft0, a0 ; RV32IZFH-NEXT: fsh ft0, 0(a1) +; RV32IZFH-NEXT: .cfi_def_cfa_offset 0 ; RV32IZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits: @@ -1161,6 +1166,7 @@ ; RV32IDZFH-NEXT: addi a0, a0, 1 ; RV32IDZFH-NEXT: fcvt.h.w ft0, a0 ; RV32IDZFH-NEXT: fsh ft0, 0(a1) +; RV32IDZFH-NEXT: .cfi_def_cfa_offset 0 ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_h_w_demanded_bits: @@ -1168,6 +1174,7 @@ ; RV64IZFH-NEXT: addiw a0, a0, 1 ; RV64IZFH-NEXT: fcvt.h.w ft0, a0 ; RV64IZFH-NEXT: fsh ft0, 0(a1) +; RV64IZFH-NEXT: .cfi_def_cfa_offset 0 ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits: @@ -1175,6 +1182,7 @@ ; RV64IDZFH-NEXT: addiw a0, a0, 1 ; RV64IDZFH-NEXT: fcvt.h.w ft0, a0 ; RV64IDZFH-NEXT: fsh ft0, 0(a1) +; RV64IDZFH-NEXT: .cfi_def_cfa_offset 0 ; RV64IDZFH-NEXT: ret %3 = add i32 %0, 1 %4 = sitofp i32 %3 to half @@ -1189,6 +1197,7 @@ ; RV32IZFH-NEXT: addi a0, a0, 1 ; RV32IZFH-NEXT: fcvt.h.wu ft0, a0 ; RV32IZFH-NEXT: fsh ft0, 0(a1) +; RV32IZFH-NEXT: .cfi_def_cfa_offset 0 ; RV32IZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits: @@ -1196,6 +1205,7 @@ ; RV32IDZFH-NEXT: addi a0, a0, 1 ; RV32IDZFH-NEXT: fcvt.h.wu ft0, a0 ; RV32IDZFH-NEXT: fsh ft0, 0(a1) +; RV32IDZFH-NEXT: .cfi_def_cfa_offset 0 ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits: @@ -1203,6 +1213,7 @@ ; RV64IZFH-NEXT: addiw a0, a0, 1 ; RV64IZFH-NEXT: fcvt.h.wu ft0, a0 ; RV64IZFH-NEXT: fsh ft0, 0(a1) +; RV64IZFH-NEXT: .cfi_def_cfa_offset 0 ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits: @@ -1210,6 +1221,7 @@ ; RV64IDZFH-NEXT: addiw a0, a0, 1 ; RV64IDZFH-NEXT: fcvt.h.wu ft0, a0 ; RV64IDZFH-NEXT: fsh ft0, 0(a1) +; RV64IDZFH-NEXT: .cfi_def_cfa_offset 0 ; RV64IDZFH-NEXT: ret %3 = add i32 %0, 1 %4 = uitofp i32 %3 to half diff --git a/llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll b/llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll --- a/llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll +++ b/llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll @@ -11,6 +11,7 @@ ; RV32-NEXT: lui a0, %hi(var) ; RV32-NEXT: addi a0, a0, %lo(var) ; RV32-NEXT: #NO_APP +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: constraint_S: @@ -19,6 +20,7 @@ ; RV64-NEXT: lui a0, %hi(var) ; RV64-NEXT: addi a0, a0, %lo(var) ; RV64-NEXT: #NO_APP +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ret = tail call i8* asm "lui $0, %hi($1)\0Aaddi $0, $0, %lo($1)", "=r,S"(i32* nonnull @var) ret i8* %ret @@ -34,6 +36,7 @@ ; RV32-NEXT: lui a0, %hi(.Ltmp0) ; RV32-NEXT: addi a0, a0, %lo(.Ltmp0) ; RV32-NEXT: #NO_APP +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: constraint_S_label: @@ -44,6 +47,7 @@ ; RV64-NEXT: lui a0, %hi(.Ltmp0) ; RV64-NEXT: addi a0, a0, %lo(.Ltmp0) ; RV64-NEXT: #NO_APP +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret entry: br label %L1 diff --git a/llvm/test/CodeGen/RISCV/large-stack.ll b/llvm/test/CodeGen/RISCV/large-stack.ll --- a/llvm/test/CodeGen/RISCV/large-stack.ll +++ b/llvm/test/CodeGen/RISCV/large-stack.ll @@ -16,6 +16,7 @@ ; RV32I-FPELIM-NEXT: lui a0, 74565 ; RV32I-FPELIM-NEXT: addi a0, a0, 1664 ; RV32I-FPELIM-NEXT: add sp, sp, a0 +; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0 ; RV32I-FPELIM-NEXT: ret ; ; RV32I-WITHFP-LABEL: test: @@ -35,8 +36,12 @@ ; RV32I-WITHFP-NEXT: addi a0, a0, -352 ; RV32I-WITHFP-NEXT: add sp, sp, a0 ; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload +; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 2032 ; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32I-WITHFP-NEXT: .cfi_restore ra +; RV32I-WITHFP-NEXT: .cfi_restore s0 ; RV32I-WITHFP-NEXT: addi sp, sp, 2032 +; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV32I-WITHFP-NEXT: ret %tmp = alloca [ 305419896 x i8 ] , align 4 ret void @@ -74,9 +79,13 @@ ; RV32I-FPELIM-NEXT: lui a0, 97 ; RV32I-FPELIM-NEXT: addi a0, a0, 672 ; RV32I-FPELIM-NEXT: add sp, sp, a0 +; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset -2032 ; RV32I-FPELIM-NEXT: lw s1, 2024(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: lw s0, 2028(sp) # 4-byte Folded Reload +; RV32I-FPELIM-NEXT: .cfi_restore s0 +; RV32I-FPELIM-NEXT: .cfi_restore s1 ; RV32I-FPELIM-NEXT: addi sp, sp, 2032 +; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0 ; RV32I-FPELIM-NEXT: ret ; ; RV32I-WITHFP-LABEL: test_emergency_spill_slot: @@ -117,8 +126,14 @@ ; RV32I-WITHFP-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload +; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 2032 ; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32I-WITHFP-NEXT: .cfi_restore ra +; RV32I-WITHFP-NEXT: .cfi_restore s0 +; RV32I-WITHFP-NEXT: .cfi_restore s1 +; RV32I-WITHFP-NEXT: .cfi_restore s2 ; RV32I-WITHFP-NEXT: addi sp, sp, 2032 +; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV32I-WITHFP-NEXT: ret %data = alloca [ 100000 x i32 ] , align 4 %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000 diff --git a/llvm/test/CodeGen/RISCV/neg-abs.ll b/llvm/test/CodeGen/RISCV/neg-abs.ll --- a/llvm/test/CodeGen/RISCV/neg-abs.ll +++ b/llvm/test/CodeGen/RISCV/neg-abs.ll @@ -17,6 +17,7 @@ ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: sub a0, a1, a0 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32IBT-LABEL: neg_abs32: @@ -24,6 +25,7 @@ ; RV32IBT-NEXT: srai a1, a0, 31 ; RV32IBT-NEXT: xor a0, a0, a1 ; RV32IBT-NEXT: sub a0, a1, a0 +; RV32IBT-NEXT: .cfi_def_cfa_offset 0 ; RV32IBT-NEXT: ret ; ; RV64I-LABEL: neg_abs32: @@ -31,6 +33,7 @@ ; RV64I-NEXT: sraiw a1, a0, 31 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: subw a0, a1, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64IBT-LABEL: neg_abs32: @@ -38,6 +41,7 @@ ; RV64IBT-NEXT: sraiw a1, a0, 31 ; RV64IBT-NEXT: xor a0, a0, a1 ; RV64IBT-NEXT: subw a0, a1, a0 +; RV64IBT-NEXT: .cfi_def_cfa_offset 0 ; RV64IBT-NEXT: ret %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) %neg = sub nsw i32 0, %abs @@ -50,6 +54,7 @@ ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: sub a0, a1, a0 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32IBT-LABEL: select_neg_abs32: @@ -57,6 +62,7 @@ ; RV32IBT-NEXT: srai a1, a0, 31 ; RV32IBT-NEXT: xor a0, a0, a1 ; RV32IBT-NEXT: sub a0, a1, a0 +; RV32IBT-NEXT: .cfi_def_cfa_offset 0 ; RV32IBT-NEXT: ret ; ; RV64I-LABEL: select_neg_abs32: @@ -64,6 +70,7 @@ ; RV64I-NEXT: sraiw a1, a0, 31 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: subw a0, a1, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64IBT-LABEL: select_neg_abs32: @@ -71,6 +78,7 @@ ; RV64IBT-NEXT: sraiw a1, a0, 31 ; RV64IBT-NEXT: xor a0, a0, a1 ; RV64IBT-NEXT: subw a0, a1, a0 +; RV64IBT-NEXT: .cfi_def_cfa_offset 0 ; RV64IBT-NEXT: ret %1 = icmp slt i32 %x, 0 %2 = sub nsw i32 0, %x @@ -88,6 +96,7 @@ ; RV32I-NEXT: sub a1, a2, a1 ; RV32I-NEXT: sub a1, a1, a3 ; RV32I-NEXT: sub a0, a2, a0 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32IBT-LABEL: neg_abs64: @@ -99,6 +108,7 @@ ; RV32IBT-NEXT: sub a1, a2, a1 ; RV32IBT-NEXT: sub a1, a1, a3 ; RV32IBT-NEXT: sub a0, a2, a0 +; RV32IBT-NEXT: .cfi_def_cfa_offset 0 ; RV32IBT-NEXT: ret ; ; RV64I-LABEL: neg_abs64: @@ -106,6 +116,7 @@ ; RV64I-NEXT: srai a1, a0, 63 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: sub a0, a1, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64IBT-LABEL: neg_abs64: @@ -113,6 +124,7 @@ ; RV64IBT-NEXT: srai a1, a0, 63 ; RV64IBT-NEXT: xor a0, a0, a1 ; RV64IBT-NEXT: sub a0, a1, a0 +; RV64IBT-NEXT: .cfi_def_cfa_offset 0 ; RV64IBT-NEXT: ret %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %neg = sub nsw i64 0, %abs @@ -129,6 +141,7 @@ ; RV32I-NEXT: sub a1, a2, a1 ; RV32I-NEXT: sub a1, a1, a3 ; RV32I-NEXT: sub a0, a2, a0 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32IBT-LABEL: select_neg_abs64: @@ -140,6 +153,7 @@ ; RV32IBT-NEXT: sub a1, a2, a1 ; RV32IBT-NEXT: sub a1, a1, a3 ; RV32IBT-NEXT: sub a0, a2, a0 +; RV32IBT-NEXT: .cfi_def_cfa_offset 0 ; RV32IBT-NEXT: ret ; ; RV64I-LABEL: select_neg_abs64: @@ -147,6 +161,7 @@ ; RV64I-NEXT: srai a1, a0, 63 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: sub a0, a1, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64IBT-LABEL: select_neg_abs64: @@ -154,6 +169,7 @@ ; RV64IBT-NEXT: srai a1, a0, 63 ; RV64IBT-NEXT: xor a0, a0, a1 ; RV64IBT-NEXT: sub a0, a1, a0 +; RV64IBT-NEXT: .cfi_def_cfa_offset 0 ; RV64IBT-NEXT: ret %1 = icmp slt i64 %x, 0 %2 = sub nsw i64 0, %x diff --git a/llvm/test/CodeGen/RISCV/patchable-function-entry.ll b/llvm/test/CodeGen/RISCV/patchable-function-entry.ll --- a/llvm/test/CodeGen/RISCV/patchable-function-entry.ll +++ b/llvm/test/CodeGen/RISCV/patchable-function-entry.ll @@ -18,8 +18,10 @@ ; CHECK-LABEL: f1: ; CHECK-NEXT: .Lfunc_begin1: ; NORVC: addi zero, zero, 0 +; NORVC-NEXT: cfi_def_cfa_offset 0 ; NORVC-NEXT: jalr zero, 0(ra) ; RVC: c.nop +; RVC-NEXT: cfi_def_cfa_offset 0 ; RVC-NEXT: c.jr ra ; CHECK: .section __patchable_function_entries,"awo",@progbits,f1{{$}} ; 32: .p2align 2 @@ -34,8 +36,10 @@ ; CHECK-LABEL: f5: ; CHECK-NEXT: .Lfunc_begin2: ; NORVC-COUNT-5: addi zero, zero, 0 +; NORVC-NEXT: cfi_def_cfa_offset 0 ; NORVC-NEXT: jalr zero, 0(ra) ; RVC-COUNT-5: c.nop +; RVC-NEXT: cfi_def_cfa_offset 0 ; RVC-NEXT: c.jr ra ; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}} ; RV32: .p2align 2 diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll --- a/llvm/test/CodeGen/RISCV/rv32zba.ll +++ b/llvm/test/CodeGen/RISCV/rv32zba.ll @@ -10,12 +10,14 @@ ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: lh a0, 0(a0) +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: sh1add: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a2 ; RV32ZBA-NEXT: lh a0, 0(a0) +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %3 = getelementptr inbounds i16, i16* %1, i64 %0 %4 = load i16, i16* %3 @@ -28,12 +30,14 @@ ; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: lw a0, 0(a0) +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: sh2add: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a2 ; RV32ZBA-NEXT: lw a0, 0(a0) +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %3 = getelementptr inbounds i32, i32* %1, i64 %0 %4 = load i32, i32* %3 @@ -47,6 +51,7 @@ ; RV32I-NEXT: add a1, a2, a0 ; RV32I-NEXT: lw a0, 0(a1) ; RV32I-NEXT: lw a1, 4(a1) +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: sh3add: @@ -54,6 +59,7 @@ ; RV32ZBA-NEXT: sh3add a1, a0, a2 ; RV32ZBA-NEXT: lw a0, 0(a1) ; RV32ZBA-NEXT: lw a1, 4(a1) +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %3 = getelementptr inbounds i64, i64* %1, i64 %0 %4 = load i64, i64* %3 @@ -66,12 +72,14 @@ ; RV32I-NEXT: addi a2, zero, 6 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul6: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 6 %d = add i32 %c, %b @@ -84,12 +92,14 @@ ; RV32I-NEXT: addi a2, zero, 10 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul10: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 10 %d = add i32 %c, %b @@ -102,12 +112,14 @@ ; RV32I-NEXT: addi a2, zero, 12 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul12: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 12 %d = add i32 %c, %b @@ -120,12 +132,14 @@ ; RV32I-NEXT: addi a2, zero, 18 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul18: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 18 %d = add i32 %c, %b @@ -138,12 +152,14 @@ ; RV32I-NEXT: addi a2, zero, 20 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul20: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 20 %d = add i32 %c, %b @@ -156,12 +172,14 @@ ; RV32I-NEXT: addi a2, zero, 24 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul24: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 24 %d = add i32 %c, %b @@ -174,12 +192,14 @@ ; RV32I-NEXT: addi a2, zero, 36 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul36: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 36 %d = add i32 %c, %b @@ -192,12 +212,14 @@ ; RV32I-NEXT: addi a2, zero, 40 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul40: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 40 %d = add i32 %c, %b @@ -210,12 +232,14 @@ ; RV32I-NEXT: addi a2, zero, 72 ; RV32I-NEXT: mul a0, a0, a2 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addmul72: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 72 %d = add i32 %c, %b @@ -227,12 +251,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 96 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul96: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a0 ; RV32ZBA-NEXT: slli a0, a0, 5 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 96 ret i32 %c @@ -243,12 +269,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 160 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul160: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a0 ; RV32ZBA-NEXT: slli a0, a0, 5 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 160 ret i32 %c @@ -259,12 +287,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 288 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul288: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: slli a0, a0, 5 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 288 ret i32 %c @@ -275,12 +305,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 258 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul258: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 258 ; RV32ZBA-NEXT: mul a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 258 ret i32 %c @@ -291,12 +323,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 260 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul260: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 260 ; RV32ZBA-NEXT: mul a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 260 ret i32 %c @@ -307,12 +341,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 264 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul264: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 264 ; RV32ZBA-NEXT: mul a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 264 ret i32 %c @@ -323,12 +359,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 11 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul11: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a1, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 11 ret i32 %c @@ -339,12 +377,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 19 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul19: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a1, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 19 ret i32 %c @@ -355,12 +395,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 13 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul13: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a1, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 13 ret i32 %c @@ -371,12 +413,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 21 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul21: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a1, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 21 ret i32 %c @@ -387,12 +431,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 37 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul37: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a1, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 37 ret i32 %c @@ -403,12 +449,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 25 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul25: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a1, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 25 ret i32 %c @@ -419,12 +467,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 41 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul41: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a1, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 41 ret i32 %c @@ -435,12 +485,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 73 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul73: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a1, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 73 ret i32 %c @@ -451,12 +503,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 27 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul27: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh1add a0, a0, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 27 ret i32 %c @@ -467,12 +521,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 45 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul45: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh2add a0, a0, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 45 ret i32 %c @@ -483,12 +539,14 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 81 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul81: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 ; RV32ZBA-NEXT: sh3add a0, a0, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 81 ret i32 %c @@ -500,12 +558,14 @@ ; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: addi a1, a1, 2 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul4098: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: slli a1, a0, 12 ; RV32ZBA-NEXT: sh1add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 4098 ret i32 %c @@ -517,12 +577,14 @@ ; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: addi a1, a1, 4 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul4100: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: slli a1, a0, 12 ; RV32ZBA-NEXT: sh2add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 4100 ret i32 %c @@ -534,12 +596,14 @@ ; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: addi a1, a1, 8 ; RV32I-NEXT: mul a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: mul4104: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: slli a1, a0, 12 ; RV32ZBA-NEXT: sh3add a0, a0, a1 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = mul i32 %a, 4104 ret i32 %c @@ -551,12 +615,14 @@ ; RV32I-NEXT: lui a1, 1 ; RV32I-NEXT: addi a1, a1, 8 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: add4104: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 1026 ; RV32ZBA-NEXT: sh2add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = add i32 %a, 4104 ret i32 %c @@ -568,12 +634,14 @@ ; RV32I-NEXT: lui a1, 2 ; RV32I-NEXT: addi a1, a1, 16 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: add8208: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 1026 ; RV32ZBA-NEXT: sh3add a0, a1, a0 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = add i32 %a, 8208 ret i32 %c @@ -585,12 +653,14 @@ ; RV32I-NEXT: slli a0, a0, 5 ; RV32I-NEXT: slli a1, a1, 6 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addshl_5_6: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a1, a0 ; RV32ZBA-NEXT: slli a0, a0, 5 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = shl i32 %a, 5 %d = shl i32 %b, 6 @@ -604,12 +674,14 @@ ; RV32I-NEXT: slli a0, a0, 5 ; RV32I-NEXT: slli a1, a1, 7 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addshl_5_7: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a1, a0 ; RV32ZBA-NEXT: slli a0, a0, 5 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = shl i32 %a, 5 %d = shl i32 %b, 7 @@ -623,12 +695,14 @@ ; RV32I-NEXT: slli a0, a0, 5 ; RV32I-NEXT: slli a1, a1, 8 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: addshl_5_8: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a1, a0 ; RV32ZBA-NEXT: slli a0, a0, 5 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBA-NEXT: ret %c = shl i32 %a, 5 %d = shl i32 %b, 8 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll --- a/llvm/test/CodeGen/RISCV/rv32zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll @@ -734,12 +734,14 @@ ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: abs_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: neg a1, a0 ; RV32ZBB-NEXT: max a0, a0, a1 +; RV32ZBB-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBB-NEXT: ret %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) ret i32 %abs @@ -757,6 +759,7 @@ ; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: neg a1, a1 ; RV32I-NEXT: .LBB19_2: +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: abs_i64: @@ -768,6 +771,7 @@ ; RV32ZBB-NEXT: add a1, a1, a2 ; RV32ZBB-NEXT: neg a1, a1 ; RV32ZBB-NEXT: .LBB19_2: +; RV32ZBB-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBB-NEXT: ret %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) ret i64 %abs @@ -861,6 +865,7 @@ ; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: bswap_i64: @@ -868,6 +873,7 @@ ; RV32ZBB-NEXT: rev8 a2, a1 ; RV32ZBB-NEXT: rev8 a1, a0 ; RV32ZBB-NEXT: mv a0, a2 +; RV32ZBB-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBB-NEXT: ret %1 = call i64 @llvm.bswap.i64(i64 %a) ret i64 %1 diff --git a/llvm/test/CodeGen/RISCV/rv32zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbp.ll --- a/llvm/test/CodeGen/RISCV/rv32zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbp.ll @@ -2141,6 +2141,7 @@ ; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBP-LABEL: bswap_i64: @@ -2148,6 +2149,7 @@ ; RV32ZBP-NEXT: rev8 a2, a1 ; RV32ZBP-NEXT: rev8 a1, a0 ; RV32ZBP-NEXT: mv a0, a2 +; RV32ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBP-NEXT: ret %1 = call i64 @llvm.bswap.i64(i64 %a) ret i64 %1 @@ -2362,11 +2364,13 @@ ; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBP-LABEL: bswap_rotr_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8.h a0, a0 +; RV32ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBP-NEXT: ret %1 = call i32 @llvm.bswap.i32(i32 %a) %2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16) @@ -2391,11 +2395,13 @@ ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBP-LABEL: bswap_rotl_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8.h a0, a0 +; RV32ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBP-NEXT: ret %1 = call i32 @llvm.bswap.i32(i32 %a) %2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16) @@ -2447,11 +2453,13 @@ ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBP-LABEL: bitreverse_bswap_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.b a0, a0 +; RV32ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBP-NEXT: ret %1 = call i32 @llvm.bitreverse.i32(i32 %a) %2 = call i32 @llvm.bswap.i32(i32 %1) @@ -2536,12 +2544,14 @@ ; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBP-LABEL: bitreverse_bswap_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a1, a1 +; RV32ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBP-NEXT: ret %1 = call i64 @llvm.bitreverse.i64(i64 %a) %2 = call i64 @llvm.bswap.i64(i64 %1) diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll --- a/llvm/test/CodeGen/RISCV/rv32zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll @@ -459,12 +459,14 @@ ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: addi a1, a1, -5 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBS-LABEL: sbclri_i32_large2: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclri a0, a0, 2 ; RV32ZBS-NEXT: bclri a0, a0, 31 +; RV32ZBS-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBS-NEXT: ret %2 = and i32 %0, 2147483643 ret i32 %2 @@ -476,12 +478,14 @@ ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: addi a1, a1, -6 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV32ZBS-LABEL: sbclri_i32_large3: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: andi a0, a0, -6 ; RV32ZBS-NEXT: bclri a0, a0, 31 +; RV32ZBS-NEXT: .cfi_def_cfa_offset 0 ; RV32ZBS-NEXT: ret %2 = and i32 %0, 2147483642 ret i32 %2 diff --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll --- a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll +++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll @@ -15,6 +15,7 @@ ; CHECK-NEXT: addw a0, a0, a2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: sllw a0, a0, a1 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = mul i32 %x, %x %c = add i32 %b, 1 diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -28,6 +28,7 @@ ; RV64I-NEXT: add a1, a1, a0 ; RV64I-NEXT: ld a0, 0(a1) ; RV64I-NEXT: ld a1, 8(a1) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: slliuw_2: @@ -36,6 +37,7 @@ ; RV64ZBA-NEXT: add a1, a1, a0 ; RV64ZBA-NEXT: ld a0, 0(a1) ; RV64ZBA-NEXT: ld a1, 8(a1) +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = zext i32 %0 to i64 %4 = getelementptr inbounds i128, i128* %1, i64 %3 @@ -67,12 +69,14 @@ ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lb a0, 0(a0) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: adduw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: add.uw a0, a0, a1 ; RV64ZBA-NEXT: lb a0, 0(a0) +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = zext i32 %0 to i64 %4 = getelementptr inbounds i8, i8* %1, i64 %3 @@ -103,12 +107,14 @@ ; RV64I-NEXT: ori a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: zextw_demandedbits_i64: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: ori a0, a0, 1 ; RV64ZBA-NEXT: zext.w a0, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %2 = and i64 %0, 4294967294 %3 = or i64 %2, 1 @@ -121,12 +127,14 @@ ; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lh a0, 0(a0) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh1add: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a1 ; RV64ZBA-NEXT: lh a0, 0(a0) +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = getelementptr inbounds i16, i16* %1, i64 %0 %4 = load i16, i16* %3 @@ -139,12 +147,14 @@ ; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh2add: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a1 ; RV64ZBA-NEXT: lw a0, 0(a0) +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = getelementptr inbounds i32, i32* %1, i64 %0 %4 = load i32, i32* %3 @@ -157,12 +167,14 @@ ; RV64I-NEXT: slli a0, a0, 3 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ld a0, 0(a0) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh3add: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a1 ; RV64ZBA-NEXT: ld a0, 0(a0) +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = getelementptr inbounds i64, i64* %1, i64 %0 %4 = load i64, i64* %3 @@ -176,12 +188,14 @@ ; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lh a0, 0(a0) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh1adduw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add.uw a0, a0, a1 ; RV64ZBA-NEXT: lh a0, 0(a0) +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = zext i32 %0 to i64 %4 = getelementptr inbounds i16, i16* %1, i64 %3 @@ -195,11 +209,13 @@ ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh1adduw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add.uw a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = shl i64 %0, 1 %4 = and i64 %3, 8589934590 @@ -214,12 +230,14 @@ ; RV64I-NEXT: srli a0, a0, 30 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh2adduw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add.uw a0, a0, a1 ; RV64ZBA-NEXT: lw a0, 0(a0) +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = zext i32 %0 to i64 %4 = getelementptr inbounds i32, i32* %1, i64 %3 @@ -233,11 +251,13 @@ ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 30 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh2adduw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add.uw a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = shl i64 %0, 2 %4 = and i64 %3, 17179869180 @@ -252,12 +272,14 @@ ; RV64I-NEXT: srli a0, a0, 29 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ld a0, 0(a0) +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh3adduw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add.uw a0, a0, a1 ; RV64ZBA-NEXT: ld a0, 0(a0) +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = zext i32 %0 to i64 %4 = getelementptr inbounds i64, i64* %1, i64 %3 @@ -271,11 +293,13 @@ ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 29 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh3adduw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add.uw a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %3 = shl i64 %0, 3 %4 = and i64 %3, 34359738360 @@ -296,6 +320,7 @@ ; RV64I-NEXT: sllw a1, a2, a0 ; RV64I-NEXT: sraiw a0, a0, 2 ; RV64I-NEXT: mul a0, a1, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh2add_extra_sext: @@ -304,6 +329,7 @@ ; RV64ZBA-NEXT: sllw a1, a2, a0 ; RV64ZBA-NEXT: sraiw a0, a0, 2 ; RV64ZBA-NEXT: mul a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %a = shl i32 %x, 2 %b = add i32 %a, %y @@ -321,12 +347,14 @@ ; RV64I-NEXT: addi a2, zero, 6 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul6: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 6 %d = add i64 %c, %b @@ -339,12 +367,14 @@ ; RV64I-NEXT: addi a2, zero, 10 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul10: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 10 %d = add i64 %c, %b @@ -357,12 +387,14 @@ ; RV64I-NEXT: addi a2, zero, 12 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul12: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 12 %d = add i64 %c, %b @@ -375,12 +407,14 @@ ; RV64I-NEXT: addi a2, zero, 18 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul18: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 18 %d = add i64 %c, %b @@ -393,12 +427,14 @@ ; RV64I-NEXT: addi a2, zero, 20 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul20: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 20 %d = add i64 %c, %b @@ -411,12 +447,14 @@ ; RV64I-NEXT: addi a2, zero, 24 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul24: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 24 %d = add i64 %c, %b @@ -429,12 +467,14 @@ ; RV64I-NEXT: addi a2, zero, 36 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul36: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 36 %d = add i64 %c, %b @@ -447,12 +487,14 @@ ; RV64I-NEXT: addi a2, zero, 40 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul40: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 40 %d = add i64 %c, %b @@ -465,12 +507,14 @@ ; RV64I-NEXT: addi a2, zero, 72 ; RV64I-NEXT: mul a0, a0, a2 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addmul72: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 72 %d = add i64 %c, %b @@ -482,12 +526,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 96 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul96: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 96 ret i64 %c @@ -498,12 +544,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 160 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul160: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 160 ret i64 %c @@ -514,12 +562,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 288 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul288: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 288 ret i64 %c @@ -530,12 +580,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: addi a0, a0, 5 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh1add_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a0, a0, 1 ; RV64ZBA-NEXT: addi a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %a = shl i64 %0, 1 %b = add i64 %a, 5 @@ -547,12 +599,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: addi a0, a0, -6 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh2add_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a0, a0, 2 ; RV64ZBA-NEXT: addi a0, a0, -6 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %a = shl i64 %0, 2 %b = add i64 %a, -6 @@ -564,12 +618,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 3 ; RV64I-NEXT: ori a0, a0, 7 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh3add_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a0, a0, 3 ; RV64ZBA-NEXT: ori a0, a0, 7 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %a = shl i64 %0, 3 %b = add i64 %a, 7 @@ -582,12 +638,14 @@ ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: addi a0, a0, 11 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh1adduw_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli.uw a0, a0, 1 ; RV64ZBA-NEXT: addi a0, a0, 11 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %a = zext i32 %0 to i64 %b = shl i64 %a, 1 @@ -601,12 +659,14 @@ ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 30 ; RV64I-NEXT: addi a0, a0, -12 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh2adduw_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli.uw a0, a0, 2 ; RV64ZBA-NEXT: addi a0, a0, -12 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %a = zext i32 %0 to i64 %b = shl i64 %a, 2 @@ -620,12 +680,14 @@ ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 29 ; RV64I-NEXT: addi a0, a0, 13 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh3adduw_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli.uw a0, a0, 3 ; RV64ZBA-NEXT: addi a0, a0, 13 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %a = zext i32 %0 to i64 %b = shl i64 %a, 3 @@ -656,12 +718,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 258 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul258: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 258 ; RV64ZBA-NEXT: mul a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 258 ret i64 %c @@ -672,12 +736,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 260 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul260: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 260 ; RV64ZBA-NEXT: mul a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 260 ret i64 %c @@ -688,12 +754,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 264 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul264: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 264 ; RV64ZBA-NEXT: mul a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 264 ret i64 %c @@ -738,12 +806,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 11 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul11: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a1, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 11 ret i64 %c @@ -754,12 +824,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 19 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul19: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a1, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 19 ret i64 %c @@ -770,12 +842,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 13 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul13: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a1, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 13 ret i64 %c @@ -786,12 +860,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 21 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul21: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a1, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 21 ret i64 %c @@ -802,12 +878,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 37 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul37: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a1, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 37 ret i64 %c @@ -818,12 +896,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 25 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul25: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a1, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 25 ret i64 %c @@ -834,12 +914,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 41 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul41: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a1, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 41 ret i64 %c @@ -850,12 +932,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 73 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul73: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a1, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 73 ret i64 %c @@ -866,12 +950,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 27 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul27: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh1add a0, a0, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 27 ret i64 %c @@ -882,12 +968,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 45 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul45: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh2add a0, a0, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 45 ret i64 %c @@ -898,12 +986,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 81 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul81: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: sh3add a0, a0, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 81 ret i64 %c @@ -915,12 +1005,14 @@ ; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: addiw a1, a1, 2 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul4098: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a1, a0, 12 ; RV64ZBA-NEXT: sh1add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 4098 ret i64 %c @@ -932,12 +1024,14 @@ ; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: addiw a1, a1, 4 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul4100: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a1, a0, 12 ; RV64ZBA-NEXT: sh2add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 4100 ret i64 %c @@ -949,12 +1043,14 @@ ; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: addiw a1, a1, 8 ; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mul4104: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a1, a0, 12 ; RV64ZBA-NEXT: sh3add a0, a0, a1 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i64 %a, 4104 ret i64 %c @@ -965,12 +1061,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 192 ; RV64I-NEXT: mulw a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mulw192: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: slliw a0, a0, 6 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i32 %a, 192 ret i32 %c @@ -981,12 +1079,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 320 ; RV64I-NEXT: mulw a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mulw320: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: slliw a0, a0, 6 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i32 %a, 320 ret i32 %c @@ -997,12 +1097,14 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi a1, zero, 576 ; RV64I-NEXT: mulw a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: mulw576: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: slliw a0, a0, 6 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = mul i32 %a, 576 ret i32 %c @@ -1014,12 +1116,14 @@ ; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: addiw a1, a1, 8 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: add4104: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 1026 ; RV64ZBA-NEXT: sh2add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = add i64 %a, 4104 ret i64 %c @@ -1031,12 +1135,14 @@ ; RV64I-NEXT: lui a1, 2 ; RV64I-NEXT: addiw a1, a1, 16 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: add8208: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 1026 ; RV64ZBA-NEXT: sh3add a0, a1, a0 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = add i64 %a, 8208 ret i64 %c @@ -1048,12 +1154,14 @@ ; RV64I-NEXT: slliw a0, a0, 5 ; RV64I-NEXT: slliw a1, a1, 6 ; RV64I-NEXT: addw a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addshl32_5_6: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a1, a0 ; RV64ZBA-NEXT: slliw a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = shl i32 %a, 5 %d = shl i32 %b, 6 @@ -1067,12 +1175,14 @@ ; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a1, a1, 6 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addshl64_5_6: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a1, a0 ; RV64ZBA-NEXT: slli a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = shl i64 %a, 5 %d = shl i64 %b, 6 @@ -1086,12 +1196,14 @@ ; RV64I-NEXT: slliw a0, a0, 5 ; RV64I-NEXT: slliw a1, a1, 7 ; RV64I-NEXT: addw a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addshl32_5_7: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: slliw a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = shl i32 %a, 5 %d = shl i32 %b, 7 @@ -1105,12 +1217,14 @@ ; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a1, a1, 7 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addshl64_5_7: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: slli a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = shl i64 %a, 5 %d = shl i64 %b, 7 @@ -1124,12 +1238,14 @@ ; RV64I-NEXT: slliw a0, a0, 5 ; RV64I-NEXT: slliw a1, a1, 8 ; RV64I-NEXT: addw a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addshl32_5_8: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: slliw a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = shl i32 %a, 5 %d = shl i32 %b, 8 @@ -1143,12 +1259,14 @@ ; RV64I-NEXT: slli a0, a0, 5 ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: addshl64_5_8: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: slli a0, a0, 5 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBA-NEXT: ret %c = shl i64 %a, 5 %d = shl i64 %b, 8 diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll --- a/llvm/test/CodeGen/RISCV/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll @@ -421,7 +421,9 @@ ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: addi a0, a0, -32 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: .cfi_restore ra ; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: addi a0, zero, 32 @@ -431,6 +433,7 @@ ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: srliw a0, a0, 1 ; RV64ZBB-NEXT: clzw a0, a0 +; RV64ZBB-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBB-NEXT: ret %1 = lshr i32 %a, 1 %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) @@ -1264,6 +1267,7 @@ ; RV64I-NEXT: srai a1, a0, 63 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: abs_i32: @@ -1271,7 +1275,9 @@ ; RV64ZBB-NEXT: sext.w a0, a0 ; RV64ZBB-NEXT: neg a1, a0 ; RV64ZBB-NEXT: max a0, a0, a1 +; RV64ZBB-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBB-NEXT: ret + %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) ret i32 %abs } @@ -1284,12 +1290,14 @@ ; RV64I-NEXT: srai a1, a0, 63 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: abs_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: neg a1, a0 ; RV64ZBB-NEXT: max a0, a0, a1 +; RV64ZBB-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBB-NEXT: ret %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) ret i64 %abs @@ -1418,11 +1426,13 @@ ; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: bswap_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rev8 a0, a0 +; RV64ZBB-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBB-NEXT: ret %1 = call i64 @llvm.bswap.i64(i64 %a) ret i64 %1 diff --git a/llvm/test/CodeGen/RISCV/rv64zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbp.ll --- a/llvm/test/CodeGen/RISCV/rv64zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbp.ll @@ -2469,11 +2469,13 @@ ; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBP-LABEL: bswap_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev8 a0, a0 +; RV64ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBP-NEXT: ret %1 = call i64 @llvm.bswap.i64(i64 %a) ret i64 %1 @@ -2742,11 +2744,13 @@ ; RV64I-NEXT: slliw a0, a0, 16 ; RV64I-NEXT: srliw a1, a1, 16 ; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBP-LABEL: bswap_rotr_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 8 +; RV64ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBP-NEXT: ret %1 = call i32 @llvm.bswap.i32(i32 %a) %2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16) @@ -2768,11 +2772,13 @@ ; RV64I-NEXT: srliw a0, a0, 16 ; RV64I-NEXT: slliw a1, a1, 16 ; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBP-LABEL: bswap_rotl_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 8 +; RV64ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBP-NEXT: ret %1 = call i32 @llvm.bswap.i32(i32 %a) %2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16) @@ -2824,11 +2830,13 @@ ; RV64I-NEXT: slliw a0, a0, 24 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBP-LABEL: bitreverse_bswap_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 7 +; RV64ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBP-NEXT: ret %1 = call i32 @llvm.bitreverse.i32(i32 %a) %2 = call i32 @llvm.bswap.i32(i32 %1) @@ -2926,11 +2934,13 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; ; RV64ZBP-LABEL: bitreverse_bswap_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev.b a0, a0 +; RV64ZBP-NEXT: .cfi_def_cfa_offset 0 ; RV64ZBP-NEXT: ret %1 = call i64 @llvm.bitreverse.i64(i64 %a) %2 = call i64 @llvm.bswap.i64(i64 %1) diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll @@ -10,6 +10,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vrsub.vi v25, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv1i16( %v, i1 false) ret %r @@ -23,6 +24,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vrsub.vi v25, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv2i16( %v, i1 false) ret %r @@ -36,6 +38,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vrsub.vi v25, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv4i16( %v, i1 false) ret %r @@ -49,6 +52,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vrsub.vi v26, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv8i16( %v, i1 false) ret %r @@ -62,6 +66,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vrsub.vi v28, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv16i16( %v, i1 false) ret %r @@ -75,6 +80,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv32i16( %v, i1 false) ret %r @@ -88,6 +94,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vrsub.vi v25, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv1i32( %v, i1 false) ret %r @@ -101,6 +108,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vrsub.vi v25, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv2i32( %v, i1 false) ret %r @@ -114,6 +122,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vrsub.vi v26, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv4i32( %v, i1 false) ret %r @@ -127,6 +136,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vrsub.vi v28, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv8i32( %v, i1 false) ret %r @@ -140,6 +150,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv16i32( %v, i1 false) ret %r @@ -153,6 +164,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vrsub.vi v25, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv1i64( %v, i1 false) ret %r @@ -166,6 +178,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vrsub.vi v26, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv2i64( %v, i1 false) ret %r @@ -179,6 +192,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vrsub.vi v28, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv4i64( %v, i1 false) ret %r @@ -192,6 +206,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv8i64( %v, i1 false) ret %r diff --git a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll --- a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll @@ -12,6 +12,7 @@ ; RV64IV-NEXT: ld a1, 520(sp) ; RV64IV-NEXT: sd a1, 0(a0) ; RV64IV-NEXT: addi sp, sp, 528 +; RV64IV-NEXT: .cfi_def_cfa_offset 0 ; RV64IV-NEXT: ret %local = alloca i64 %array = alloca [64 x i64] @@ -44,6 +45,7 @@ ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: addi sp, sp, 544 +; RV64IV-NEXT: .cfi_def_cfa_offset 0 ; RV64IV-NEXT: ret %local = alloca i64 %vector = alloca diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir --- a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir +++ b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir @@ -51,8 +51,12 @@ ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240 ; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4) + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa $x2, 2032 ; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3) + ; CHECK-NEXT: CFI_INSTRUCTION restore $x1 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x8 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 0 ; CHECK-NEXT: PseudoRET %1:gprnox0 = COPY $x11 %0:gpr = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll --- a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll @@ -9,6 +9,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load , * %p ret %v @@ -18,6 +19,7 @@ ; CHECK-LABEL: ret_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vl2re32.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load , * %p ret %v @@ -27,6 +29,7 @@ ; CHECK-LABEL: ret_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vl4re32.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load , * %p ret %v @@ -40,6 +43,7 @@ ; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: vl8re64.v v16, (a1) ; CHECK-NEXT: vl8re64.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load , * %p ret %v @@ -50,6 +54,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load , * %p ret %v @@ -60,6 +65,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load , * %p ret %v @@ -88,6 +94,7 @@ ; CHECK-NEXT: vs8r.v v0, (a1) ; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: vs8r.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load , * %x ret %v @@ -184,6 +191,7 @@ ; CHECK-NEXT: slli a0, a0, 5 ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load , * %x ret %v @@ -194,6 +202,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = add %v, %w ret %r @@ -204,6 +213,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = add %v, %w ret %r @@ -214,6 +224,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = xor %v, %w ret %r @@ -224,6 +235,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu ; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = and %v, %w ret %r @@ -271,6 +283,7 @@ ; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = add %x, %y %s = add %r, %z @@ -312,7 +325,9 @@ ; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32-NEXT: .cfi_restore ra ; RV32-NEXT: addi sp, sp, 32 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_i32: @@ -343,7 +358,9 @@ ; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64-NEXT: .cfi_restore ra ; RV64-NEXT: addi sp, sp, 32 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %t = call fastcc @ext2( %y, %x, i32 %w, i32 2) ret %t @@ -419,7 +436,9 @@ ; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32-NEXT: .cfi_restore ra ; RV32-NEXT: addi sp, sp, 32 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_i32: @@ -491,7 +510,9 @@ ; RV64-NEXT: mul a0, a0, a1 ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64-NEXT: .cfi_restore ra ; RV64-NEXT: addi sp, sp, 32 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %t = call fastcc @ext3( %z, %y, %x, i32 %w, i32 42) ret %t @@ -511,6 +532,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v24 ; CHECK-NEXT: vadd.vv v16, v16, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = add %x, %z ret %s @@ -567,7 +589,9 @@ ; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32-NEXT: .cfi_restore ra ; RV32-NEXT: addi sp, sp, 32 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: pass_vector_arg_indirect_stack: @@ -619,7 +643,9 @@ ; RV64-NEXT: slli a0, a0, 5 ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64-NEXT: .cfi_restore ra ; RV64-NEXT: addi sp, sp, 32 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = call fastcc @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, zeroinitializer, zeroinitializer, zeroinitializer, i32 8) ret %s diff --git a/llvm/test/CodeGen/RISCV/rvv/calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/calling-conv.ll --- a/llvm/test/CodeGen/RISCV/rvv/calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/calling-conv.ll @@ -14,6 +14,7 @@ ; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v16, v16, v0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: callee_scalable_vector_split_indirect: @@ -26,6 +27,7 @@ ; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; RV64-NEXT: vadd.vv v8, v8, v24 ; RV64-NEXT: vadd.vv v16, v16, v0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = add %x, %y ret %a @@ -58,7 +60,9 @@ ; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload +; RV32-NEXT: .cfi_restore ra ; RV32-NEXT: addi sp, sp, 48 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: caller_scalable_vector_split_indirect: @@ -86,7 +90,9 @@ ; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64-NEXT: .cfi_restore ra ; RV64-NEXT: addi sp, sp, 32 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %c = alloca i64 %a = call @callee_scalable_vector_split_indirect( zeroinitializer, %x) diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-sats.ll b/llvm/test/CodeGen/RISCV/rvv/combine-sats.ll --- a/llvm/test/CodeGen/RISCV/rvv/combine-sats.ll +++ b/llvm/test/CodeGen/RISCV/rvv/combine-sats.ll @@ -12,6 +12,7 @@ ; CHECK-NEXT: addi a0, zero, 7 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a0, <2 x i64> ) %v2 = add <2 x i64> %v1, @@ -24,6 +25,7 @@ ; CHECK-NEXT: addi a0, zero, 7 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %ins1 = insertelement poison, i64 7, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -42,6 +44,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a0, <2 x i64> %a1) %v2 = sub <2 x i64> %v1, %a1 @@ -53,6 +56,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = call @llvm.umax.nxv2i64( %a0, %a1) %v2 = sub %v1, %a1 @@ -64,6 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %a0, <2 x i64> %a1) %v2 = sub <2 x i64> %a0, %v1 @@ -75,6 +80,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = call @llvm.umin.nxv2i64( %a0, %a1) %v2 = sub %a0, %v1 @@ -90,6 +96,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp uge <2 x i64> %a0, %a1 %v1 = sub <2 x i64> %a0, %a1 @@ -102,6 +109,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp uge %a0, %a1 %v1 = sub %a0, %a1 @@ -148,6 +156,7 @@ ; CHECK-NEXT: addi a0, zero, 6 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = add <2 x i64> %a0, %cmp = icmp ugt <2 x i64> %a0, @@ -161,6 +170,7 @@ ; CHECK-NEXT: addi a0, zero, 6 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cm1 = insertelement poison, i64 -6, i32 0 %splatcm1 = shufflevector %cm1, poison, zeroinitializer @@ -179,6 +189,7 @@ ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vssubu.vx v8, v8, a0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vselect_add_const_signbit_v2i16: @@ -187,6 +198,7 @@ ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vssubu.vx v8, v8, a0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %cmp = icmp ugt <2 x i16> %a0, %v1 = add <2 x i16> %a0, @@ -201,6 +213,7 @@ ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; RV32-NEXT: vssubu.vx v8, v8, a0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vselect_add_const_signbit_nxv2i16: @@ -209,6 +222,7 @@ ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; RV64-NEXT: vssubu.vx v8, v8, a0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %cm1 = insertelement poison, i16 32766, i32 0 %splatcm1 = shufflevector %cm1, poison, zeroinitializer @@ -228,6 +242,7 @@ ; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp slt <2 x i16> %a0, zeroinitializer %v1 = xor <2 x i16> %a0, @@ -241,6 +256,7 @@ ; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp slt %a0, zeroinitializer %ins = insertelement poison, i16 -32768, i32 0 @@ -260,6 +276,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = add <2 x i64> %a0, %a1 %cmp = icmp ule <2 x i64> %a0, %v1 @@ -272,6 +289,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsaddu.vv v8, v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = add %a0, %a1 %cmp = icmp ule %a0, %v1 @@ -289,6 +307,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsaddu.vi v8, v8, 6 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v1 = add <2 x i64> %a0, %cmp = icmp ule <2 x i64> %a0, @@ -301,6 +320,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsaddu.vi v8, v8, 6 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cm1 = insertelement poison, i64 6, i32 0 %splatcm1 = shufflevector %cm1, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll b/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll --- a/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll +++ b/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll @@ -9,6 +9,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vmv.v.i v8, 8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %ins1 = insertelement poison, i32 255, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -27,6 +28,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vor.vi v26, v8, 3 ; CHECK-NEXT: vand.vi v8, v26, 7 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %ins1 = insertelement poison, i64 7, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -44,6 +46,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vmv.v.i v8, 3 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %ins1 = insertelement poison, i64 1, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -66,6 +69,7 @@ ; CHECK-NEXT: vmv.s.x v28, a0 ; CHECK-NEXT: vsll.vv v26, v8, v26 ; CHECK-NEXT: vsll.vv v8, v26, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %ins1 = insertelement poison, i32 2, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -83,6 +87,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsra.vi v8, v8, 6 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %ins1 = insertelement poison, i32 2, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -100,6 +105,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsrl.vi v8, v8, 8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %ins1 = insertelement poison, i16 2, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll @@ -9,6 +9,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %addr1 = getelementptr float, float * %ptr, i64 1 %addr2 = getelementptr float, float * %ptr, i64 2 diff --git a/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll b/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll --- a/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll +++ b/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll @@ -34,6 +34,7 @@ ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vrgather.vv v8, v28, v12, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret entry: %v2 = shufflevector <8 x i16> %v0, <8 x i16> poison, <16 x i32> diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll --- a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll +++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll @@ -22,6 +22,7 @@ ; RV32-NEXT: vand.vx v25, v25, a0 ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vnsrl.wi v8, v25, 0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: fixedlen: @@ -33,6 +34,7 @@ ; RV64-NEXT: vand.vx v25, v25, a0 ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vnsrl.wi v8, v25, 0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v41 = insertelement <2 x i32> undef, i32 16, i32 0 %v42 = shufflevector <2 x i32> %v41, <2 x i32> undef, <2 x i32> zeroinitializer @@ -54,6 +56,7 @@ ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vand.vx v8, v25, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v41 = insertelement undef, i32 16, i32 0 %v42 = shufflevector %v41, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir --- a/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir +++ b/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir @@ -175,8 +175,23 @@ ; CHECK-NEXT: $x18 = LD $x2, 2000 :: (load (s64) from %stack.6) ; CHECK-NEXT: $x9 = LD $x2, 2008 :: (load (s64) from %stack.5) ; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4) + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa $x2, 2032 ; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3) + ; CHECK-NEXT: CFI_INSTRUCTION restore $x1 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x8 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x9 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x18 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x19 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x20 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x21 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x22 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x23 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x24 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x25 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x26 + ; CHECK-NEXT: CFI_INSTRUCTION restore $x27 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 0 ; CHECK-NEXT: PseudoRET bb.0: successors: %bb.1, %bb.2 diff --git a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll --- a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll @@ -9,6 +9,7 @@ ; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -22,6 +23,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -35,6 +37,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -48,6 +51,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -61,6 +65,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -74,6 +79,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -87,6 +93,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -100,6 +107,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -113,6 +121,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -126,6 +135,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -139,6 +149,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -152,6 +163,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -165,6 +177,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -178,6 +191,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -191,6 +205,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -204,6 +219,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -217,6 +233,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -230,6 +247,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -243,6 +261,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -255,6 +274,7 @@ ; CHECK-NEXT: vl1r.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -267,6 +287,7 @@ ; CHECK-NEXT: vl1r.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -279,6 +300,7 @@ ; CHECK-NEXT: vl1r.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -291,6 +313,7 @@ ; CHECK-NEXT: vl1r.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -303,6 +326,7 @@ ; CHECK-NEXT: vl1r.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -315,6 +339,7 @@ ; CHECK-NEXT: vl1r.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -327,6 +352,7 @@ ; CHECK-NEXT: vl2r.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -339,6 +365,7 @@ ; CHECK-NEXT: vl2r.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -351,6 +378,7 @@ ; CHECK-NEXT: vl2r.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -363,6 +391,7 @@ ; CHECK-NEXT: vl2r.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -375,6 +404,7 @@ ; CHECK-NEXT: vl4r.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -387,6 +417,7 @@ ; CHECK-NEXT: vl4r.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -400,6 +431,7 @@ ; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v25, v25, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -412,6 +444,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -425,6 +458,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -438,6 +472,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -451,6 +486,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -464,6 +500,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -476,6 +513,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -489,6 +527,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -502,6 +541,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -515,6 +555,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -528,6 +569,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -540,6 +582,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -552,6 +595,7 @@ ; CHECK-NEXT: vl1re16.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -564,6 +608,7 @@ ; CHECK-NEXT: vl1re16.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -576,6 +621,7 @@ ; CHECK-NEXT: vl1re16.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -588,6 +634,7 @@ ; CHECK-NEXT: vl1re16.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -600,6 +647,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -612,6 +660,7 @@ ; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -624,6 +673,7 @@ ; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -636,6 +686,7 @@ ; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -648,6 +699,7 @@ ; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -660,6 +712,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu ; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -672,6 +725,7 @@ ; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -684,6 +738,7 @@ ; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -696,6 +751,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu ; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -710,6 +766,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -722,6 +779,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -735,6 +793,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -748,6 +807,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -762,6 +822,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -774,6 +835,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -786,6 +848,7 @@ ; CHECK-NEXT: vl1re32.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -798,6 +861,7 @@ ; CHECK-NEXT: vl1re32.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -812,6 +876,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -824,6 +889,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -836,6 +902,7 @@ ; CHECK-NEXT: vl2re32.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -848,6 +915,7 @@ ; CHECK-NEXT: vl2re32.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -862,6 +930,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v26, 0 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -874,6 +943,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -886,6 +956,7 @@ ; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -898,6 +969,7 @@ ; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -912,6 +984,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; CHECK-NEXT: vnsrl.wi v26, v28, 0 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -924,6 +997,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -940,6 +1014,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -954,6 +1029,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -966,6 +1042,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -982,6 +1059,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -996,6 +1074,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1008,6 +1087,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1024,6 +1104,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1038,6 +1119,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v26, 0 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1050,6 +1132,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1066,6 +1149,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v26, 0 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1080,6 +1164,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vnsrl.wi v26, v28, 0 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1092,6 +1177,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1104,6 +1190,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1118,6 +1205,7 @@ ; CHECK-NEXT: vfwcvt.f.f.v v26, v25 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1130,6 +1218,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1144,6 +1233,7 @@ ; CHECK-NEXT: vfwcvt.f.f.v v26, v25 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1156,6 +1246,7 @@ ; CHECK-NEXT: vl1re16.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1170,6 +1261,7 @@ ; CHECK-NEXT: vfwcvt.f.f.v v26, v25 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1182,6 +1274,7 @@ ; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1196,6 +1289,7 @@ ; CHECK-NEXT: vfwcvt.f.f.v v28, v26 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1208,6 +1302,7 @@ ; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1220,6 +1315,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v8 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1232,6 +1328,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1244,6 +1341,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v8 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1256,6 +1354,7 @@ ; CHECK-NEXT: vl1re32.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1268,6 +1367,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v8 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1280,6 +1380,7 @@ ; CHECK-NEXT: vl2re32.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1292,6 +1393,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v8 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1304,6 +1406,7 @@ ; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1316,6 +1419,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v28, v8 ; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1330,6 +1434,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v25 ; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1342,6 +1447,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v8 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1356,6 +1462,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v25 ; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1368,6 +1475,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v8 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1382,6 +1490,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v26 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1394,6 +1503,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v8 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1408,6 +1518,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v28 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -1420,6 +1531,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v28, v8 ; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z diff --git a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll @@ -6,6 +6,7 @@ ; CHECK-LABEL: extract_nxv8i32_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m4 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i32.nxv8i32( %vec, i64 0) ret %c @@ -15,6 +16,7 @@ ; CHECK-LABEL: extract_nxv8i32_nxv4i32_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv2r.v v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i32.nxv8i32( %vec, i64 4) ret %c @@ -24,6 +26,7 @@ ; CHECK-LABEL: extract_nxv8i32_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m4 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv8i32( %vec, i64 0) ret %c @@ -33,6 +36,7 @@ ; CHECK-LABEL: extract_nxv8i32_nxv2i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv8i32( %vec, i64 2) ret %c @@ -42,6 +46,7 @@ ; CHECK-LABEL: extract_nxv8i32_nxv2i32_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv8i32( %vec, i64 4) ret %c @@ -51,6 +56,7 @@ ; CHECK-LABEL: extract_nxv8i32_nxv2i32_6: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v11 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv8i32( %vec, i64 6) ret %c @@ -60,6 +66,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv8i32.nxv16i32( %vec, i64 0) ret %c @@ -69,6 +76,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv8i32_8: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv4r.v v8, v12 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv8i32.nxv16i32( %vec, i64 8) ret %c @@ -78,6 +86,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i32.nxv16i32( %vec, i64 0) ret %c @@ -87,6 +96,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv4i32_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv2r.v v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i32.nxv16i32( %vec, i64 4) ret %c @@ -96,6 +106,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv4i32_8: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv2r.v v8, v12 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i32.nxv16i32( %vec, i64 8) ret %c @@ -105,6 +116,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv4i32_12: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv2r.v v8, v14 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i32.nxv16i32( %vec, i64 12) ret %c @@ -114,6 +126,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( %vec, i64 0) ret %c @@ -123,6 +136,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv2i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( %vec, i64 2) ret %c @@ -132,6 +146,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv2i32_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( %vec, i64 4) ret %c @@ -141,6 +156,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv2i32_6: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v11 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( %vec, i64 6) ret %c @@ -150,6 +166,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv2i32_8: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v12 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( %vec, i64 8) ret %c @@ -159,6 +176,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv2i32_10: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v13 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( %vec, i64 10) ret %c @@ -168,6 +186,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv2i32_12: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v14 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( %vec, i64 12) ret %c @@ -177,6 +196,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv2i32_14: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v15 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( %vec, i64 14) ret %c @@ -186,6 +206,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( %vec, i64 0) ret %c @@ -198,6 +219,7 @@ ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( %vec, i64 1) ret %c @@ -210,6 +232,7 @@ ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( %vec, i64 3) ret %c @@ -222,6 +245,7 @@ ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v15, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( %vec, i64 15) ret %c @@ -231,6 +255,7 @@ ; CHECK-LABEL: extract_nxv16i32_nxv1i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( %vec, i64 2) ret %c @@ -239,6 +264,7 @@ define @extract_nxv2i32_nxv1i32_0( %vec) { ; CHECK-LABEL: extract_nxv2i32_nxv1i32_0: ; CHECK: # %bb.0: +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv1i32.nxv2i32( %vec, i64 0) ret %c @@ -248,6 +274,7 @@ ; CHECK-LABEL: extract_nxv32i8_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m4 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( %vec, i64 0) ret %c @@ -260,6 +287,7 @@ ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( %vec, i64 2) ret %c @@ -272,6 +300,7 @@ ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( %vec, i64 4) ret %c @@ -286,6 +315,7 @@ ; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( %vec, i64 6) ret %c @@ -295,6 +325,7 @@ ; CHECK-LABEL: extract_nxv32i8_nxv2i8_8: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( %vec, i64 8) ret %c @@ -309,6 +340,7 @@ ; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v10, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( %vec, i64 22) ret %c @@ -323,6 +355,7 @@ ; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv1i8.nxv8i8( %vec, i64 7) ret %c @@ -337,6 +370,7 @@ ; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv1i8.nxv4i8( %vec, i64 3) ret %c @@ -346,6 +380,7 @@ ; CHECK-LABEL: extract_nxv2f16_nxv16f16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m4 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2f16.nxv16f16( %vec, i64 0) ret %c @@ -358,6 +393,7 @@ ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2f16.nxv16f16( %vec, i64 2) ret %c @@ -367,6 +403,7 @@ ; CHECK-LABEL: extract_nxv2f16_nxv16f16_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2f16.nxv16f16( %vec, i64 4) ret %c @@ -375,6 +412,7 @@ define @extract_nxv64i1_nxv8i1_0( %mask) { ; CHECK-LABEL: extract_nxv64i1_nxv8i1_0: ; CHECK: # %bb.0: +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv8i1( %mask, i64 0) ret %c @@ -387,6 +425,7 @@ ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v0, v0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv8i1( %mask, i64 8) ret %c @@ -395,6 +434,7 @@ define @extract_nxv64i1_nxv2i1_0( %mask) { ; CHECK-LABEL: extract_nxv64i1_nxv2i1_0: ; CHECK: # %bb.0: +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i1( %mask, i64 0) ret %c @@ -412,6 +452,7 @@ ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i1( %mask, i64 2) ret %c @@ -420,6 +461,7 @@ define @extract_nxv4i1_nxv32i1_0( %x) { ; CHECK-LABEL: extract_nxv4i1_nxv32i1_0: ; CHECK: # %bb.0: +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i1( %x, i64 0) ret %c @@ -437,6 +479,7 @@ ; CHECK-NEXT: vslidedown.vx v25, v28, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i1( %x, i64 4) ret %c @@ -445,6 +488,7 @@ define @extract_nxv16i1_nxv32i1_0( %x) { ; CHECK-LABEL: extract_nxv16i1_nxv32i1_0: ; CHECK: # %bb.0: +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv16i1( %x, i64 0) ret %c @@ -457,6 +501,7 @@ ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v0, v0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv16i1( %x, i64 16) ret %c @@ -469,6 +514,7 @@ ; CHECK-LABEL: extract_nxv6f16_nxv12f16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m4 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.extract.nxv6f16.nxv12f16( %in, i64 0) ret %res @@ -489,6 +535,7 @@ ; CHECK-NEXT: vslideup.vx v27, v25, a0 ; CHECK-NEXT: vslideup.vx v26, v10, a0 ; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.extract.nxv6f16.nxv12f16( %in, i64 6) ret %res diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll @@ -7,6 +7,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -18,6 +19,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -29,6 +31,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -39,6 +42,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -50,6 +54,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -61,6 +66,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -71,6 +77,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m1, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -82,6 +89,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -93,6 +101,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -103,6 +112,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -114,6 +124,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -125,6 +136,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -135,6 +147,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -146,6 +159,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -157,6 +171,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -167,6 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m8, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -178,6 +194,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -189,6 +206,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -199,6 +217,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -210,6 +229,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -221,6 +241,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -231,6 +252,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -242,6 +264,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -253,6 +276,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -263,6 +287,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -274,6 +299,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -285,6 +311,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -295,6 +322,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m4, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -306,6 +334,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -317,6 +346,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -327,6 +357,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m8, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -338,6 +369,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -349,6 +381,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -359,6 +392,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret double %r @@ -370,6 +404,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -381,6 +416,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -391,6 +427,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret double %r @@ -402,6 +439,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -413,6 +451,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -423,6 +462,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m4, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret double %r @@ -434,6 +474,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -445,6 +486,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -455,6 +497,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret double %r @@ -466,6 +509,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -477,6 +521,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll @@ -7,6 +7,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -18,6 +19,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -29,6 +31,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -39,6 +42,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -50,6 +54,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -61,6 +66,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -71,6 +77,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m1, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -82,6 +89,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -93,6 +101,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -103,6 +112,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -114,6 +124,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -125,6 +136,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -135,6 +147,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -146,6 +159,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -157,6 +171,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -167,6 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m8, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret half %r @@ -178,6 +194,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -189,6 +206,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -199,6 +217,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -210,6 +229,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -221,6 +241,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -231,6 +252,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -242,6 +264,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -253,6 +276,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -263,6 +287,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -274,6 +299,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -285,6 +311,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -295,6 +322,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m4, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -306,6 +334,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -317,6 +346,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -327,6 +357,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m8, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret float %r @@ -338,6 +369,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -349,6 +381,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -359,6 +392,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret double %r @@ -370,6 +404,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -381,6 +416,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -391,6 +427,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret double %r @@ -402,6 +439,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -413,6 +451,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -423,6 +462,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m4, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret double %r @@ -434,6 +474,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -445,6 +486,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -455,6 +497,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, mu ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret double %r @@ -466,6 +509,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -477,6 +521,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll @@ -7,6 +7,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -18,6 +19,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -29,6 +31,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -39,6 +42,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -50,6 +54,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -61,6 +66,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -71,6 +77,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -82,6 +89,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -93,6 +101,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -103,6 +112,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -114,6 +124,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -125,6 +136,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -135,6 +147,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, m2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -146,6 +159,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -157,6 +171,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -167,6 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, m4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -178,6 +194,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -189,6 +206,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -199,6 +217,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -210,6 +229,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -221,6 +241,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -231,6 +252,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -242,6 +264,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -253,6 +276,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -263,6 +287,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -274,6 +299,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -285,6 +311,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -295,6 +322,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m1, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -306,6 +334,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -317,6 +346,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -327,6 +357,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -338,6 +369,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -349,6 +381,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -359,6 +392,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -370,6 +404,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -381,6 +416,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -391,6 +427,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -402,6 +439,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -413,6 +451,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -423,6 +462,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -434,6 +474,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -445,6 +486,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -455,6 +497,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -466,6 +509,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -477,6 +521,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -487,6 +532,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -498,6 +544,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -509,6 +556,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -519,6 +567,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -530,6 +579,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -541,6 +591,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -551,6 +602,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -562,6 +614,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -573,6 +626,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -586,6 +640,7 @@ ; CHECK-NEXT: vsrl.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a1, v25 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i64 %r @@ -600,6 +655,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -614,6 +670,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -627,6 +684,7 @@ ; CHECK-NEXT: vsrl.vx v26, v8, a0 ; CHECK-NEXT: vmv.x.s a1, v26 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i64 %r @@ -641,6 +699,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vmv.x.s a1, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -655,6 +714,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vmv.x.s a1, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -668,6 +728,7 @@ ; CHECK-NEXT: vsrl.vx v28, v8, a0 ; CHECK-NEXT: vmv.x.s a1, v28 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i64 %r @@ -682,6 +743,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vmv.x.s a1, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -696,6 +758,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vmv.x.s a1, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -709,6 +772,7 @@ ; CHECK-NEXT: vsrl.vx v16, v8, a0 ; CHECK-NEXT: vmv.x.s a1, v16 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i64 %r @@ -723,6 +787,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a1, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -737,6 +802,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a1, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll @@ -7,6 +7,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -18,6 +19,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -29,6 +31,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -39,6 +42,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -50,6 +54,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -61,6 +66,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -71,6 +77,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -82,6 +89,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -93,6 +101,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -103,6 +112,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -114,6 +124,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -125,6 +136,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -135,6 +147,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, m2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -146,6 +159,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -157,6 +171,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -167,6 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, m4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -178,6 +194,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -189,6 +206,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -199,6 +217,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i8 %r @@ -210,6 +229,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -221,6 +241,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -231,6 +252,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -242,6 +264,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -253,6 +276,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -263,6 +287,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -274,6 +299,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -285,6 +311,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -295,6 +322,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m1, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -306,6 +334,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -317,6 +346,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -327,6 +357,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -338,6 +369,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -349,6 +381,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -359,6 +392,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -370,6 +404,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -381,6 +416,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -391,6 +427,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, m8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i16 %r @@ -402,6 +439,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -413,6 +451,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -423,6 +462,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -434,6 +474,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -445,6 +486,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -455,6 +497,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -466,6 +509,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -477,6 +521,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -487,6 +532,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -498,6 +544,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -509,6 +556,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -519,6 +567,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -530,6 +579,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -541,6 +591,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -551,6 +602,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, m8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i32 %r @@ -562,6 +614,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -573,6 +626,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -583,6 +637,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i64 %r @@ -594,6 +649,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -605,6 +661,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -615,6 +672,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i64 %r @@ -626,6 +684,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -637,6 +696,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -647,6 +707,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i64 %r @@ -658,6 +719,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -669,6 +731,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -679,6 +742,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 ret i64 %r @@ -690,6 +754,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -701,6 +766,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll @@ -47,6 +47,7 @@ ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB0_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -117,6 +118,7 @@ ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB1_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -183,6 +185,7 @@ ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB2_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -247,6 +250,7 @@ ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bne a2, a4, .LBB3_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -318,6 +322,7 @@ ; CHECK-ASM-NEXT: addi a0, a0, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB4_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -389,6 +394,7 @@ ; CHECK-ASM-NEXT: addi a0, a0, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB5_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -460,6 +466,7 @@ ; CHECK-ASM-NEXT: addi a1, a1, 128 ; CHECK-ASM-NEXT: bnez a2, .LBB6_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -533,6 +540,7 @@ ; CHECK-ASM-NEXT: addi a0, a0, 128 ; CHECK-ASM-NEXT: bnez a2, .LBB7_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -623,6 +631,7 @@ ; CHECK-ASM-NEXT: addi a1, a1, 256 ; CHECK-ASM-NEXT: bnez a2, .LBB8_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -775,6 +784,7 @@ ; CHECK-ASM-NEXT: addi a0, a0, 128 ; CHECK-ASM-NEXT: bnez a2, .LBB9_1 ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret entry: br label %vector.body @@ -873,6 +883,7 @@ ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bnez a2, .LBB10_1 ; CHECK-ASM-NEXT: # %bb.2: +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret br label %3 @@ -949,6 +960,7 @@ ; CHECK-ASM-NEXT: addi a0, a0, 160 ; CHECK-ASM-NEXT: bnez a2, .LBB11_1 ; CHECK-ASM-NEXT: # %bb.2: +; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ASM-NEXT: ret br label %3 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll @@ -12,6 +12,7 @@ ; CHECK-NEXT: vrsub.vi v26, v25, 0 ; CHECK-NEXT: vmax.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 false) @@ -28,6 +29,7 @@ ; CHECK-NEXT: vrsub.vi v26, v25, 0 ; CHECK-NEXT: vmax.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false) @@ -44,6 +46,7 @@ ; CHECK-NEXT: vrsub.vi v26, v25, 0 ; CHECK-NEXT: vmax.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false) @@ -60,6 +63,7 @@ ; CHECK-NEXT: vrsub.vi v26, v25, 0 ; CHECK-NEXT: vmax.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a, i1 false) @@ -77,6 +81,7 @@ ; LMULMAX2-NEXT: vrsub.vi v28, v26, 0 ; LMULMAX2-NEXT: vmax.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: abs_v32i8: @@ -91,6 +96,7 @@ ; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 ; LMULMAX1-RV32-NEXT: vse8.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: abs_v32i8: @@ -105,6 +111,7 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vse8.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 false) @@ -121,6 +128,7 @@ ; LMULMAX2-NEXT: vrsub.vi v28, v26, 0 ; LMULMAX2-NEXT: vmax.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: abs_v16i16: @@ -135,6 +143,7 @@ ; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 ; LMULMAX1-RV32-NEXT: vse16.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: abs_v16i16: @@ -149,6 +158,7 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vse16.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 false) @@ -165,6 +175,7 @@ ; LMULMAX2-NEXT: vrsub.vi v28, v26, 0 ; LMULMAX2-NEXT: vmax.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: abs_v8i32: @@ -179,6 +190,7 @@ ; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 ; LMULMAX1-RV32-NEXT: vse32.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: abs_v8i32: @@ -193,6 +205,7 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vse32.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false) @@ -209,6 +222,7 @@ ; LMULMAX2-NEXT: vrsub.vi v28, v26, 0 ; LMULMAX2-NEXT: vmax.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: abs_v4i64: @@ -223,6 +237,7 @@ ; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 ; LMULMAX1-RV32-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: abs_v4i64: @@ -237,6 +252,7 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 false) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll @@ -13,6 +13,7 @@ ; VLEN256-NEXT: vle8.v v0, (a1) ; VLEN256-NEXT: vadd.vv v8, v24, v8 ; VLEN256-NEXT: vadd.vv v16, v0, v16 +; VLEN256-NEXT: .cfi_def_cfa_offset 0 ; VLEN256-NEXT: ret ; ; VLEN512-LABEL: bitcast_1024B: @@ -20,6 +21,7 @@ ; VLEN512-NEXT: addi a0, zero, 512 ; VLEN512-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; VLEN512-NEXT: vadd.vv v8, v16, v8 +; VLEN512-NEXT: .cfi_def_cfa_offset 0 ; VLEN512-NEXT: ret ; ; VLEN1024-LABEL: bitcast_1024B: @@ -27,6 +29,7 @@ ; VLEN1024-NEXT: addi a0, zero, 512 ; VLEN1024-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; VLEN1024-NEXT: vadd.vv v8, v12, v8 +; VLEN1024-NEXT: .cfi_def_cfa_offset 0 ; VLEN1024-NEXT: ret %c = bitcast <256 x i16> %a to <512 x i8> %v = add <512 x i8> %b, %c diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll @@ -8,6 +8,7 @@ ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = bitcast <4 x i8> %a to <32 x i1> %d = xor <32 x i1> %b, %c @@ -19,6 +20,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <1 x i8> %a to i8 ret i8 %b @@ -29,6 +31,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <2 x i8> %a to i16 ret i16 %b @@ -39,6 +42,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <1 x i16> %a to i16 ret i16 %b @@ -49,6 +53,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <4 x i8> %a to i32 ret i32 %b @@ -59,6 +64,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <2 x i16> %a to i32 ret i32 %b @@ -69,6 +75,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <1 x i32> %a to i32 ret i32 %b @@ -82,12 +89,14 @@ ; RV32-NEXT: vsrl.vx v25, v8, a0 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_v8i8_i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast <8 x i8> %a to i64 ret i64 %b @@ -101,12 +110,14 @@ ; RV32-NEXT: vsrl.vx v25, v8, a0 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_v4i16_i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast <4 x i16> %a to i64 ret i64 %b @@ -120,12 +131,14 @@ ; RV32-NEXT: vsrl.vx v25, v8, a0 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_v2i32_i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast <2 x i32> %a to i64 ret i64 %b @@ -139,12 +152,14 @@ ; RV32-NEXT: vsrl.vx v25, v8, a0 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_v1i64_i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast <1 x i64> %a to i64 ret i64 %b @@ -155,6 +170,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <2 x i8> %a to half ret half %b @@ -165,6 +181,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <1 x i16> %a to half ret half %b @@ -175,6 +192,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <4 x i8> %a to float ret float %b @@ -185,6 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <2 x i16> %a to float ret float %b @@ -195,6 +214,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <1 x i32> %a to float ret float %b @@ -208,12 +228,14 @@ ; RV32-NEXT: vsrl.vx v25, v8, a0 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_v8i8_f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast <8 x i8> %a to double ret double %b @@ -227,12 +249,14 @@ ; RV32-NEXT: vsrl.vx v25, v8, a0 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_v4i16_f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast <4 x i16> %a to double ret double %b @@ -246,12 +270,14 @@ ; RV32-NEXT: vsrl.vx v25, v8, a0 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_v2i32_f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast <2 x i32> %a to double ret double %b @@ -265,12 +291,14 @@ ; RV32-NEXT: vsrl.vx v25, v8, a0 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_v1i64_f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast <1 x i64> %a to double ret double %b @@ -281,6 +309,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast i16 %a to <1 x i16> ret <1 x i16> %b @@ -291,12 +320,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-NEXT: vmv.s.x v8, a0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_i32_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-NEXT: vmv.v.x v8, a0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast i32 %a to <2 x i16> ret <2 x i16> %b @@ -307,12 +338,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-NEXT: vmv.s.x v8, a0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_i32_v1i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-NEXT: vmv.v.x v8, a0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast i32 %a to <1 x i32> ret <1 x i32> %b @@ -327,12 +360,14 @@ ; RV32-NEXT: vslide1up.vx v25, v26, a0 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vslideup.vi v8, v25, 0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_i64_v4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vmv.s.x v8, a0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast i64 %a to <4 x i16> ret <4 x i16> %b @@ -347,12 +382,14 @@ ; RV32-NEXT: vslide1up.vx v25, v26, a0 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vslideup.vi v8, v25, 0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_i64_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vmv.s.x v8, a0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast i64 %a to <2 x i32> ret <2 x i32> %b @@ -367,12 +404,14 @@ ; RV32-NEXT: vslide1up.vx v25, v26, a0 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vslideup.vi v8, v25, 0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_i64_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vmv.s.x v8, a0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %b = bitcast i64 %a to <1 x i64> ret <1 x i64> %b diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll @@ -34,6 +34,7 @@ ; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25 ; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 ; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v8i16: @@ -65,6 +66,7 @@ ; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25 ; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 ; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v8i16: @@ -96,6 +98,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 ; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v8i16: @@ -127,6 +130,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 ; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -175,6 +179,7 @@ ; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25 ; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 ; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v4i32: @@ -215,6 +220,7 @@ ; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25 ; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 ; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v4i32: @@ -255,6 +261,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 ; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v4i32: @@ -295,6 +302,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 ; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -387,6 +395,7 @@ ; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25 ; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 ; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v2i64: @@ -464,6 +473,7 @@ ; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25 ; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 ; LMULMAX2-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v2i64: @@ -548,6 +558,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 ; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v2i64: @@ -625,6 +636,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 ; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -664,6 +676,7 @@ ; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26 ; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 ; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v16i16: @@ -695,6 +708,7 @@ ; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26 ; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 ; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v16i16: @@ -747,6 +761,7 @@ ; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 ; LMULMAX1-RV32-NEXT: vse16.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v16i16: @@ -799,6 +814,7 @@ ; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 ; LMULMAX1-RV64-NEXT: vse16.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -847,6 +863,7 @@ ; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26 ; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 ; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v8i32: @@ -887,6 +904,7 @@ ; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26 ; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 ; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v8i32: @@ -954,6 +972,7 @@ ; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 ; LMULMAX1-RV32-NEXT: vse32.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v8i32: @@ -1021,6 +1040,7 @@ ; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 ; LMULMAX1-RV64-NEXT: vse32.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -1113,6 +1133,7 @@ ; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26 ; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v4i64: @@ -1190,6 +1211,7 @@ ; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26 ; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v4i64: @@ -1313,6 +1335,7 @@ ; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v29, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v4i64: @@ -1429,6 +1452,7 @@ ; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a7) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll @@ -72,6 +72,7 @@ ; LMULMAX2-RV32-NEXT: vle16.v v25, (a1) ; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bswap_v8i16: @@ -141,6 +142,7 @@ ; LMULMAX2-RV64-NEXT: vle16.v v25, (a1) ; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bswap_v8i16: @@ -210,6 +212,7 @@ ; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bswap_v8i16: @@ -279,6 +282,7 @@ ; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -351,6 +355,7 @@ ; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) ; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bswap_v4i32: @@ -415,6 +420,7 @@ ; LMULMAX2-RV64-NEXT: vle32.v v25, (a1) ; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bswap_v4i32: @@ -479,6 +485,7 @@ ; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bswap_v4i32: @@ -543,6 +550,7 @@ ; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -617,6 +625,7 @@ ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bswap_v2i64: @@ -681,6 +690,7 @@ ; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bswap_v2i64: @@ -747,6 +757,7 @@ ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bswap_v2i64: @@ -811,6 +822,7 @@ ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -952,8 +964,12 @@ ; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bswap_v16i16: @@ -1087,8 +1103,12 @@ ; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bswap_v16i16: @@ -1218,6 +1238,7 @@ ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a1) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bswap_v16i16: @@ -1347,6 +1368,7 @@ ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a1) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -1475,8 +1497,12 @@ ; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bswap_v8i32: @@ -1597,8 +1623,12 @@ ; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bswap_v8i32: @@ -1715,6 +1745,7 @@ ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bswap_v8i32: @@ -1831,6 +1862,7 @@ ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -1961,8 +1993,12 @@ ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bswap_v4i64: @@ -2087,8 +2123,12 @@ ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bswap_v4i64: @@ -2207,6 +2247,7 @@ ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bswap_v4i64: @@ -2324,6 +2365,7 @@ ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1 ; LMULMAX1-RV64-NEXT: vse64.v v27, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a6) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll @@ -7,6 +7,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %p ret <4 x i8> %v @@ -17,6 +18,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %p ret <4 x i32> %v @@ -27,6 +29,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %p ret <8 x i32> %v @@ -37,6 +40,7 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; LMULMAX8-NEXT: vle64.v v8, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v16i64: @@ -45,6 +49,7 @@ ; LMULMAX4-NEXT: vle64.v v8, (a0) ; LMULMAX4-NEXT: addi a0, a0, 64 ; LMULMAX4-NEXT: vle64.v v12, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %v = load <16 x i64>, <16 x i64>* %p ret <16 x i64> %v @@ -55,6 +60,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i1>, <8 x i1>* %p ret <8 x i1> %v @@ -66,6 +72,7 @@ ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i1>, <32 x i1>* %p ret <32 x i1> %v @@ -80,6 +87,7 @@ ; LMULMAX8-NEXT: vle32.v v8, (a0) ; LMULMAX8-NEXT: addi a0, a0, 128 ; LMULMAX8-NEXT: vle32.v v16, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_split_v64i32: @@ -92,6 +100,7 @@ ; LMULMAX4-NEXT: vle32.v v16, (a1) ; LMULMAX4-NEXT: addi a0, a0, 192 ; LMULMAX4-NEXT: vle32.v v20, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x ret <64 x i32> %v @@ -117,6 +126,7 @@ ; LMULMAX8-NEXT: addi a1, a0, 128 ; LMULMAX8-NEXT: vse32.v v16, (a1) ; LMULMAX8-NEXT: vse32.v v8, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_split_v128i32: @@ -152,6 +162,7 @@ ; LMULMAX4-NEXT: addi a1, a0, 64 ; LMULMAX4-NEXT: vse32.v v8, (a1) ; LMULMAX4-NEXT: vse32.v v28, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %v = load <128 x i32>, <128 x i32>* %x ret <128 x i32> %v @@ -162,6 +173,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vi v8, v8, 2 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = add <4 x i8> %v, ret <4 x i8> %r @@ -172,6 +184,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = add <4 x i8> %v, %w ret <4 x i8> %r @@ -182,6 +195,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = add <4 x i64> %v, %w ret <4 x i64> %r @@ -192,6 +206,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = xor <8 x i1> %v, %w ret <8 x i1> %r @@ -203,6 +218,7 @@ ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = and <32 x i1> %v, %w ret <32 x i1> %r @@ -217,6 +233,7 @@ ; LMULMAX8-NEXT: vadd.vv v8, v8, v16 ; LMULMAX8-NEXT: vadd.vv v8, v8, v24 ; LMULMAX8-NEXT: vadd.vx v8, v8, a1 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v32i32_param_v32i32_v32i32_v32i32_i32: @@ -231,6 +248,7 @@ ; LMULMAX4-NEXT: vadd.vv v8, v8, v24 ; LMULMAX4-NEXT: vadd.vx v8, v8, a2 ; LMULMAX4-NEXT: vadd.vx v12, v28, a2 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %r = add <32 x i32> %x, %y %s = add <32 x i32> %r, %z @@ -256,7 +274,9 @@ ; LMULMAX8-NEXT: vmv8r.v v16, v24 ; LMULMAX8-NEXT: call ext2@plt ; LMULMAX8-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra ; LMULMAX8-NEXT: addi sp, sp, 16 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v32i32_call_v32i32_v32i32_i32: @@ -274,7 +294,9 @@ ; LMULMAX4-NEXT: vmv4r.v v20, v28 ; LMULMAX4-NEXT: call ext2@plt ; LMULMAX4-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra ; LMULMAX4-NEXT: addi sp, sp, 16 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %t = call fastcc <32 x i32> @ext2(<32 x i32> %y, <32 x i32> %x, i32 %w, i32 2) ret <32 x i32> %t @@ -303,8 +325,12 @@ ; LMULMAX8-NEXT: call ext3@plt ; LMULMAX8-NEXT: addi sp, s0, -384 ; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra +; LMULMAX8-NEXT: .cfi_restore s0 ; LMULMAX8-NEXT: addi sp, sp, 384 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: @@ -333,8 +359,12 @@ ; LMULMAX4-NEXT: call ext3@plt ; LMULMAX4-NEXT: addi sp, s0, -384 ; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra +; LMULMAX4-NEXT: .cfi_restore s0 ; LMULMAX4-NEXT: addi sp, sp, 384 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %t = call fastcc <32 x i32> @ext3(<32 x i32> %z, <32 x i32> %y, <32 x i32> %x, i32 %w, i32 42) ret <32 x i32> %t @@ -350,6 +380,7 @@ ; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; LMULMAX8-NEXT: vle32.v v16, (t2) ; LMULMAX8-NEXT: vadd.vv v8, v8, v16 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: vector_arg_indirect_stack: @@ -360,6 +391,7 @@ ; LMULMAX4-NEXT: vle32.v v16, (a0) ; LMULMAX4-NEXT: vadd.vv v8, v8, v28 ; LMULMAX4-NEXT: vadd.vv v12, v12, v16 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %s = add <32 x i32> %x, %z ret <32 x i32> %s @@ -397,8 +429,12 @@ ; LMULMAX8-NEXT: call vector_arg_indirect_stack@plt ; LMULMAX8-NEXT: addi sp, s0, -384 ; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra +; LMULMAX8-NEXT: .cfi_restore s0 ; LMULMAX8-NEXT: addi sp, sp, 384 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: pass_vector_arg_indirect_stack: @@ -434,8 +470,12 @@ ; LMULMAX4-NEXT: call vector_arg_indirect_stack@plt ; LMULMAX4-NEXT: addi sp, s0, -384 ; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra +; LMULMAX4-NEXT: .cfi_restore s0 ; LMULMAX4-NEXT: addi sp, sp, 384 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %s = call fastcc <32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, i32 8) ret <32 x i32> %s @@ -454,6 +494,7 @@ ; LMULMAX8-NEXT: vadd.vv v8, v8, v16 ; LMULMAX8-NEXT: vadd.vv v8, v8, v24 ; LMULMAX8-NEXT: addi sp, sp, 16 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: vector_arg_direct_stack: @@ -470,6 +511,7 @@ ; LMULMAX4-NEXT: vadd.vv v8, v8, v28 ; LMULMAX4-NEXT: vadd.vv v12, v12, v24 ; LMULMAX4-NEXT: addi sp, sp, 16 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %s = add <32 x i32> %x, %y %t = add <32 x i32> %s, %z @@ -509,7 +551,9 @@ ; LMULMAX8-NEXT: vmv8r.v v16, v8 ; LMULMAX8-NEXT: call vector_arg_direct_stack@plt ; LMULMAX8-NEXT: ld ra, 152(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra ; LMULMAX8-NEXT: addi sp, sp, 160 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: pass_vector_arg_direct_stack: @@ -546,7 +590,9 @@ ; LMULMAX4-NEXT: vmv4r.v v20, v8 ; LMULMAX4-NEXT: call vector_arg_direct_stack@plt ; LMULMAX4-NEXT: ld ra, 152(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra ; LMULMAX4-NEXT: addi sp, sp, 160 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %s = call fastcc <32 x i32> @vector_arg_direct_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, i32 1) ret <32 x i32> %s @@ -564,6 +610,7 @@ ; CHECK-NEXT: vlm.v v25, (a0) ; CHECK-NEXT: vmxor.mm v0, v0, v25 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = xor <4 x i1> %m1, %m2 ret <4 x i1> %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll @@ -9,6 +9,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %p ret <4 x i8> %v @@ -19,6 +20,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %p ret <4 x i32> %v @@ -29,18 +31,21 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX8-NEXT: vle32.v v8, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v8i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vle32.v v8, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_v8i32: @@ -49,6 +54,7 @@ ; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vle32.v v9, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %v = load <8 x i32>, <8 x i32>* %p ret <8 x i32> %v @@ -59,6 +65,7 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; LMULMAX8-NEXT: vle64.v v8, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v16i64: @@ -67,6 +74,7 @@ ; LMULMAX4-NEXT: vle64.v v8, (a0) ; LMULMAX4-NEXT: addi a0, a0, 64 ; LMULMAX4-NEXT: vle64.v v12, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_v16i64: @@ -79,6 +87,7 @@ ; LMULMAX2-NEXT: vle64.v v12, (a1) ; LMULMAX2-NEXT: addi a0, a0, 96 ; LMULMAX2-NEXT: vle64.v v14, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_v16i64: @@ -99,6 +108,7 @@ ; LMULMAX1-NEXT: vle64.v v14, (a1) ; LMULMAX1-NEXT: addi a0, a0, 112 ; LMULMAX1-NEXT: vle64.v v15, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %v = load <16 x i64>, <16 x i64>* %p ret <16 x i64> %v @@ -109,6 +119,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i1>, <8 x i1>* %p ret <8 x i1> %v @@ -120,6 +131,7 @@ ; LMULMAX8-NEXT: addi a1, zero, 32 ; LMULMAX8-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX8-NEXT: vlm.v v0, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_mask_v32i1: @@ -127,6 +139,7 @@ ; LMULMAX4-NEXT: addi a1, zero, 32 ; LMULMAX4-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX4-NEXT: vlm.v v0, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_mask_v32i1: @@ -134,6 +147,7 @@ ; LMULMAX2-NEXT: addi a1, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX2-NEXT: vlm.v v0, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_mask_v32i1: @@ -142,6 +156,7 @@ ; LMULMAX1-NEXT: vlm.v v0, (a0) ; LMULMAX1-NEXT: addi a0, a0, 2 ; LMULMAX1-NEXT: vlm.v v8, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %v = load <32 x i1>, <32 x i1>* %p ret <32 x i1> %v @@ -156,6 +171,7 @@ ; LMULMAX8-NEXT: vle32.v v8, (a0) ; LMULMAX8-NEXT: addi a0, a0, 128 ; LMULMAX8-NEXT: vle32.v v16, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_split_v64i32: @@ -168,6 +184,7 @@ ; LMULMAX4-NEXT: vle32.v v16, (a1) ; LMULMAX4-NEXT: addi a0, a0, 192 ; LMULMAX4-NEXT: vle32.v v20, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_split_v64i32: @@ -188,6 +205,7 @@ ; LMULMAX2-NEXT: vle32.v v20, (a1) ; LMULMAX2-NEXT: addi a0, a0, 224 ; LMULMAX2-NEXT: vle32.v v22, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_split_v64i32: @@ -224,6 +242,7 @@ ; LMULMAX1-NEXT: vle32.v v22, (a1) ; LMULMAX1-NEXT: addi a0, a0, 240 ; LMULMAX1-NEXT: vle32.v v23, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x ret <64 x i32> %v @@ -249,6 +268,7 @@ ; LMULMAX8-NEXT: addi a1, a0, 128 ; LMULMAX8-NEXT: vse32.v v16, (a1) ; LMULMAX8-NEXT: vse32.v v8, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_split_v128i32: @@ -284,6 +304,7 @@ ; LMULMAX4-NEXT: addi a1, a0, 64 ; LMULMAX4-NEXT: vse32.v v8, (a1) ; LMULMAX4-NEXT: vse32.v v28, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_split_v128i32: @@ -351,6 +372,7 @@ ; LMULMAX2-NEXT: addi a1, a0, 32 ; LMULMAX2-NEXT: vse32.v v28, (a1) ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_split_v128i32: @@ -482,6 +504,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse32.v v26, (a1) ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %v = load <128 x i32>, <128 x i32>* %x ret <128 x i32> %v @@ -492,6 +515,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vi v8, v8, 2 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = add <4 x i8> %v, ret <4 x i8> %r @@ -502,6 +526,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = add <4 x i8> %v, %w ret <4 x i8> %r @@ -512,18 +537,21 @@ ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX8-NEXT: vadd.vv v8, v8, v10 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v4i64_param_v4i64_v4i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX4-NEXT: vadd.vv v8, v8, v10 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_v4i64_param_v4i64_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_v4i64_param_v4i64_v4i64: @@ -531,6 +559,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-NEXT: vadd.vv v9, v9, v11 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %r = add <4 x i64> %v, %w ret <4 x i64> %r @@ -541,6 +570,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = xor <8 x i1> %v, %w ret <8 x i1> %r @@ -552,6 +582,7 @@ ; LMULMAX8-NEXT: addi a0, zero, 32 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; LMULMAX8-NEXT: vmand.mm v0, v0, v8 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v32i1_param_v32i1_v32i1: @@ -559,6 +590,7 @@ ; LMULMAX4-NEXT: addi a0, zero, 32 ; LMULMAX4-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; LMULMAX4-NEXT: vmand.mm v0, v0, v8 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_v32i1_param_v32i1_v32i1: @@ -566,6 +598,7 @@ ; LMULMAX2-NEXT: addi a0, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; LMULMAX2-NEXT: vmand.mm v0, v0, v8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_v32i1_param_v32i1_v32i1: @@ -573,6 +606,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vmand.mm v0, v0, v9 ; LMULMAX1-NEXT: vmand.mm v8, v8, v10 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %r = and <32 x i1> %v, %w ret <32 x i1> %r @@ -587,6 +621,7 @@ ; LMULMAX8-NEXT: vadd.vv v8, v8, v16 ; LMULMAX8-NEXT: vadd.vv v8, v8, v24 ; LMULMAX8-NEXT: vadd.vx v8, v8, a1 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v32i32_param_v32i32_v32i32_v32i32_i32: @@ -601,6 +636,7 @@ ; LMULMAX4-NEXT: vadd.vv v8, v8, v24 ; LMULMAX4-NEXT: vadd.vx v8, v8, a2 ; LMULMAX4-NEXT: vadd.vx v12, v28, a2 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_v32i32_param_v32i32_v32i32_v32i32_i32: @@ -625,6 +661,7 @@ ; LMULMAX2-NEXT: vadd.vx v10, v28, a4 ; LMULMAX2-NEXT: vadd.vx v12, v30, a4 ; LMULMAX2-NEXT: vadd.vx v14, v14, a4 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_v32i32_param_v32i32_v32i32_v32i32_i32: @@ -670,6 +707,7 @@ ; LMULMAX1-NEXT: vadd.vx v13, v30, a0 ; LMULMAX1-NEXT: vadd.vx v14, v31, a0 ; LMULMAX1-NEXT: vadd.vx v15, v15, a0 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %r = add <32 x i32> %x, %y %s = add <32 x i32> %r, %z @@ -695,7 +733,9 @@ ; LMULMAX8-NEXT: vmv8r.v v16, v24 ; LMULMAX8-NEXT: call ext2@plt ; LMULMAX8-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra ; LMULMAX8-NEXT: addi sp, sp, 16 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v32i32_call_v32i32_v32i32_i32: @@ -713,7 +753,9 @@ ; LMULMAX4-NEXT: vmv4r.v v20, v28 ; LMULMAX4-NEXT: call ext2@plt ; LMULMAX4-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra ; LMULMAX4-NEXT: addi sp, sp, 16 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_v32i32_call_v32i32_v32i32_i32: @@ -737,7 +779,9 @@ ; LMULMAX2-NEXT: vmv2r.v v22, v26 ; LMULMAX2-NEXT: call ext2@plt ; LMULMAX2-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; LMULMAX2-NEXT: .cfi_restore ra ; LMULMAX2-NEXT: addi sp, sp, 16 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_v32i32_call_v32i32_v32i32_i32: @@ -773,7 +817,9 @@ ; LMULMAX1-NEXT: vmv1r.v v23, v25 ; LMULMAX1-NEXT: call ext2@plt ; LMULMAX1-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; LMULMAX1-NEXT: .cfi_restore ra ; LMULMAX1-NEXT: addi sp, sp, 16 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %t = call <32 x i32> @ext2(<32 x i32> %y, <32 x i32> %x, i32 %w, i32 2) ret <32 x i32> %t @@ -802,8 +848,12 @@ ; LMULMAX8-NEXT: call ext3@plt ; LMULMAX8-NEXT: addi sp, s0, -384 ; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra +; LMULMAX8-NEXT: .cfi_restore s0 ; LMULMAX8-NEXT: addi sp, sp, 384 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: @@ -832,8 +882,12 @@ ; LMULMAX4-NEXT: call ext3@plt ; LMULMAX4-NEXT: addi sp, s0, -384 ; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra +; LMULMAX4-NEXT: .cfi_restore s0 ; LMULMAX4-NEXT: addi sp, sp, 384 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: @@ -872,8 +926,12 @@ ; LMULMAX2-NEXT: call ext3@plt ; LMULMAX2-NEXT: addi sp, s0, -384 ; LMULMAX2-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX2-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX2-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX2-NEXT: .cfi_restore ra +; LMULMAX2-NEXT: .cfi_restore s0 ; LMULMAX2-NEXT: addi sp, sp, 384 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: @@ -935,8 +993,12 @@ ; LMULMAX1-NEXT: call ext3@plt ; LMULMAX1-NEXT: addi sp, s0, -384 ; LMULMAX1-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX1-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX1-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX1-NEXT: .cfi_restore ra +; LMULMAX1-NEXT: .cfi_restore s0 ; LMULMAX1-NEXT: addi sp, sp, 384 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %t = call <32 x i32> @ext3(<32 x i32> %z, <32 x i32> %y, <32 x i32> %x, i32 %w, i32 42) ret <32 x i32> %t @@ -962,6 +1024,7 @@ ; LMULMAX8-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; LMULMAX8-NEXT: vle32.v v8, (a0) ; LMULMAX8-NEXT: vadd.vv v8, v16, v8 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: split_vector_args: @@ -972,6 +1035,7 @@ ; LMULMAX4-NEXT: vle32.v v12, (a1) ; LMULMAX4-NEXT: vadd.vv v8, v16, v28 ; LMULMAX4-NEXT: vadd.vv v12, v20, v12 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: split_vector_args: @@ -986,6 +1050,7 @@ ; LMULMAX2-NEXT: vadd.vv v10, v16, v26 ; LMULMAX2-NEXT: vadd.vv v12, v18, v28 ; LMULMAX2-NEXT: vadd.vv v14, v20, v30 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: split_vector_args: @@ -1008,6 +1073,7 @@ ; LMULMAX1-NEXT: vadd.vv v13, v18, v27 ; LMULMAX1-NEXT: vadd.vv v14, v19, v26 ; LMULMAX1-NEXT: vadd.vv v15, v20, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %v0 = add <32 x i32> %y, %z ret <32 x i32> %v0 @@ -1040,8 +1106,12 @@ ; LMULMAX8-NEXT: call split_vector_args@plt ; LMULMAX8-NEXT: addi sp, s0, -384 ; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra +; LMULMAX8-NEXT: .cfi_restore s0 ; LMULMAX8-NEXT: addi sp, sp, 384 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: call_split_vector_args: @@ -1073,8 +1143,12 @@ ; LMULMAX4-NEXT: call split_vector_args@plt ; LMULMAX4-NEXT: addi sp, s0, -384 ; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_def_cfa sp, 384 ; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra +; LMULMAX4-NEXT: .cfi_restore s0 ; LMULMAX4-NEXT: addi sp, sp, 384 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: call_split_vector_args: @@ -1113,8 +1187,12 @@ ; LMULMAX2-NEXT: call split_vector_args@plt ; LMULMAX2-NEXT: addi sp, s0, -256 ; LMULMAX2-NEXT: ld s0, 240(sp) # 8-byte Folded Reload +; LMULMAX2-NEXT: .cfi_def_cfa sp, 256 ; LMULMAX2-NEXT: ld ra, 248(sp) # 8-byte Folded Reload +; LMULMAX2-NEXT: .cfi_restore ra +; LMULMAX2-NEXT: .cfi_restore s0 ; LMULMAX2-NEXT: addi sp, sp, 256 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: call_split_vector_args: @@ -1167,8 +1245,12 @@ ; LMULMAX1-NEXT: call split_vector_args@plt ; LMULMAX1-NEXT: addi sp, s0, -256 ; LMULMAX1-NEXT: ld s0, 240(sp) # 8-byte Folded Reload +; LMULMAX1-NEXT: .cfi_def_cfa sp, 256 ; LMULMAX1-NEXT: ld ra, 248(sp) # 8-byte Folded Reload +; LMULMAX1-NEXT: .cfi_restore ra +; LMULMAX1-NEXT: .cfi_restore s0 ; LMULMAX1-NEXT: addi sp, sp, 256 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <2 x i32>, <2 x i32>* %pa %b = load <32 x i32>, <32 x i32>* %pb @@ -1189,6 +1271,7 @@ ; LMULMAX8-NEXT: vle32.v v16, (a0) ; LMULMAX8-NEXT: vadd.vv v8, v8, v16 ; LMULMAX8-NEXT: addi sp, sp, 16 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: vector_arg_via_stack: @@ -1203,6 +1286,7 @@ ; LMULMAX4-NEXT: vadd.vv v8, v8, v28 ; LMULMAX4-NEXT: vadd.vv v12, v12, v16 ; LMULMAX4-NEXT: addi sp, sp, 16 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: vector_arg_via_stack: @@ -1223,6 +1307,7 @@ ; LMULMAX2-NEXT: vadd.vv v12, v12, v30 ; LMULMAX2-NEXT: vadd.vv v14, v14, v16 ; LMULMAX2-NEXT: addi sp, sp, 16 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: vector_arg_via_stack: @@ -1255,6 +1340,7 @@ ; LMULMAX1-NEXT: vadd.vv v14, v14, v26 ; LMULMAX1-NEXT: vadd.vv v15, v15, v25 ; LMULMAX1-NEXT: addi sp, sp, 16 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %s = add <32 x i32> %x, %z ret <32 x i32> %s @@ -1285,7 +1371,9 @@ ; LMULMAX8-NEXT: vmv8r.v v16, v8 ; LMULMAX8-NEXT: call vector_arg_via_stack@plt ; LMULMAX8-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra ; LMULMAX8-NEXT: addi sp, sp, 144 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: pass_vector_arg_via_stack: @@ -1314,7 +1402,9 @@ ; LMULMAX4-NEXT: vmv4r.v v20, v8 ; LMULMAX4-NEXT: call vector_arg_via_stack@plt ; LMULMAX4-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra ; LMULMAX4-NEXT: addi sp, sp, 144 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: pass_vector_arg_via_stack: @@ -1351,7 +1441,9 @@ ; LMULMAX2-NEXT: vmv2r.v v22, v8 ; LMULMAX2-NEXT: call vector_arg_via_stack@plt ; LMULMAX2-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; LMULMAX2-NEXT: .cfi_restore ra ; LMULMAX2-NEXT: addi sp, sp, 144 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: pass_vector_arg_via_stack: @@ -1404,7 +1496,9 @@ ; LMULMAX1-NEXT: vmv1r.v v23, v8 ; LMULMAX1-NEXT: call vector_arg_via_stack@plt ; LMULMAX1-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; LMULMAX1-NEXT: .cfi_restore ra ; LMULMAX1-NEXT: addi sp, sp, 144 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %s = call <32 x i32> @vector_arg_via_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, i32 8) ret <32 x i32> %s @@ -1421,6 +1515,7 @@ ; CHECK-NEXT: addi a0, sp, 152 ; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret ret <4 x i1> %10 } @@ -1462,7 +1557,9 @@ ; LMULMAX8-NEXT: vmv8r.v v16, v8 ; LMULMAX8-NEXT: call vector_mask_arg_via_stack@plt ; LMULMAX8-NEXT: ld ra, 152(sp) # 8-byte Folded Reload +; LMULMAX8-NEXT: .cfi_restore ra ; LMULMAX8-NEXT: addi sp, sp, 160 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX4-LABEL: pass_vector_mask_arg_via_stack: @@ -1502,7 +1599,9 @@ ; LMULMAX4-NEXT: vmv4r.v v20, v8 ; LMULMAX4-NEXT: call vector_mask_arg_via_stack@plt ; LMULMAX4-NEXT: ld ra, 152(sp) # 8-byte Folded Reload +; LMULMAX4-NEXT: .cfi_restore ra ; LMULMAX4-NEXT: addi sp, sp, 160 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: pass_vector_mask_arg_via_stack: @@ -1550,7 +1649,9 @@ ; LMULMAX2-NEXT: vmv2r.v v22, v8 ; LMULMAX2-NEXT: call vector_mask_arg_via_stack@plt ; LMULMAX2-NEXT: ld ra, 152(sp) # 8-byte Folded Reload +; LMULMAX2-NEXT: .cfi_restore ra ; LMULMAX2-NEXT: addi sp, sp, 160 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: pass_vector_mask_arg_via_stack: @@ -1614,7 +1715,9 @@ ; LMULMAX1-NEXT: vmv1r.v v23, v8 ; LMULMAX1-NEXT: call vector_mask_arg_via_stack@plt ; LMULMAX1-NEXT: ld ra, 152(sp) # 8-byte Folded Reload +; LMULMAX1-NEXT: .cfi_restore ra ; LMULMAX1-NEXT: addi sp, sp, 160 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %r = call <4 x i1> @vector_mask_arg_via_stack(i32 0, i32 0, i32 0, i32 0, i32 0, i32 5, i32 6, i32 7, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, i32 8, <4 x i1> %v, <4 x i1> %v) ret <4 x i1> %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll @@ -472,6 +472,7 @@ ; LMULMAX2-RV32-NEXT: vle8.v v25, (a1) ; LMULMAX2-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v16i8: @@ -995,6 +996,7 @@ ; LMULMAX2-RV64-NEXT: vle8.v v25, (a1) ; LMULMAX2-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v16i8: @@ -1464,6 +1466,7 @@ ; LMULMAX1-RV32-NEXT: vle8.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v16i8: @@ -1987,6 +1990,7 @@ ; LMULMAX1-RV64-NEXT: vle8.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -2242,6 +2246,7 @@ ; LMULMAX2-RV32-NEXT: vle16.v v25, (a1) ; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v8i16: @@ -2527,6 +2532,7 @@ ; LMULMAX2-RV64-NEXT: vle16.v v25, (a1) ; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v8i16: @@ -2774,6 +2780,7 @@ ; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v8i16: @@ -3059,6 +3066,7 @@ ; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -3192,6 +3200,7 @@ ; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) ; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v4i32: @@ -3359,6 +3368,7 @@ ; LMULMAX2-RV64-NEXT: vle32.v v25, (a1) ; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v4i32: @@ -3484,6 +3494,7 @@ ; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v4i32: @@ -3651,6 +3662,7 @@ ; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -3798,6 +3810,7 @@ ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v2i64: @@ -3893,6 +3906,7 @@ ; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v2i64: @@ -4032,6 +4046,7 @@ ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v2i64: @@ -4127,6 +4142,7 @@ ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -5061,8 +5077,12 @@ ; LMULMAX2-RV32-NEXT: vse8.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v32i8: @@ -6075,8 +6095,12 @@ ; LMULMAX2-RV64-NEXT: vse8.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v32i8: @@ -6998,6 +7022,7 @@ ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v32i8: @@ -8005,6 +8030,7 @@ ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -8492,8 +8518,12 @@ ; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v16i16: @@ -9027,8 +9057,12 @@ ; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v16i16: @@ -9504,6 +9538,7 @@ ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v16i16: @@ -10033,6 +10068,7 @@ ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -10278,8 +10314,12 @@ ; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v8i32: @@ -10579,8 +10619,12 @@ ; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v8i32: @@ -10814,6 +10858,7 @@ ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v8i32: @@ -11109,6 +11154,7 @@ ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -11380,8 +11426,12 @@ ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v4i64: @@ -11545,8 +11595,12 @@ ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v4i64: @@ -11806,6 +11860,7 @@ ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v4i64: @@ -11962,6 +12017,7 @@ ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1 ; LMULMAX1-RV64-NEXT: vse64.v v27, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a6) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll @@ -22,6 +22,7 @@ ; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vand.vi v25, v25, 15 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -56,6 +57,7 @@ ; LMULMAX2-RV32-NEXT: vmul.vx v25, v25, a1 ; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 8 ; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v8i16: @@ -82,6 +84,7 @@ ; LMULMAX2-RV64-NEXT: vmul.vx v25, v25, a1 ; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 8 ; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v8i16: @@ -108,6 +111,7 @@ ; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a1 ; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 8 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v8i16: @@ -134,6 +138,7 @@ ; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a1 ; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 8 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -169,6 +174,7 @@ ; LMULMAX2-RV32-NEXT: vmul.vx v25, v25, a1 ; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 24 ; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v4i32: @@ -196,6 +202,7 @@ ; LMULMAX2-RV64-NEXT: vmul.vx v25, v25, a1 ; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 24 ; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v4i32: @@ -223,6 +230,7 @@ ; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a1 ; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 24 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v4i32: @@ -250,6 +258,7 @@ ; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a1 ; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 24 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -298,6 +307,7 @@ ; LMULMAX2-RV32-NEXT: addi a1, zero, 56 ; LMULMAX2-RV32-NEXT: vsrl.vx v25, v25, a1 ; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v2i64: @@ -348,6 +358,7 @@ ; LMULMAX2-RV64-NEXT: addi a1, zero, 56 ; LMULMAX2-RV64-NEXT: vsrl.vx v25, v25, a1 ; LMULMAX2-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v2i64: @@ -388,6 +399,7 @@ ; LMULMAX1-RV32-NEXT: addi a1, zero, 56 ; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a1 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v2i64: @@ -438,6 +450,7 @@ ; LMULMAX1-RV64-NEXT: addi a1, zero, 56 ; LMULMAX1-RV64-NEXT: vsrl.vx v25, v25, a1 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -466,6 +479,7 @@ ; LMULMAX2-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vand.vi v26, v26, 15 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ctpop_v32i8: @@ -498,6 +512,7 @@ ; LMULMAX1-NEXT: vand.vi v26, v26, 15 ; LMULMAX1-NEXT: vse8.v v26, (a0) ; LMULMAX1-NEXT: vse8.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -532,6 +547,7 @@ ; LMULMAX2-RV32-NEXT: vmul.vx v26, v26, a1 ; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 8 ; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v16i16: @@ -558,6 +574,7 @@ ; LMULMAX2-RV64-NEXT: vmul.vx v26, v26, a1 ; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 8 ; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v16i16: @@ -599,6 +616,7 @@ ; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 8 ; LMULMAX1-RV32-NEXT: vse16.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v16i16: @@ -640,6 +658,7 @@ ; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 8 ; LMULMAX1-RV64-NEXT: vse16.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -675,6 +694,7 @@ ; LMULMAX2-RV32-NEXT: vmul.vx v26, v26, a1 ; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 24 ; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v8i32: @@ -702,6 +722,7 @@ ; LMULMAX2-RV64-NEXT: vmul.vx v26, v26, a1 ; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 24 ; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v8i32: @@ -744,6 +765,7 @@ ; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 24 ; LMULMAX1-RV32-NEXT: vse32.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v8i32: @@ -786,6 +808,7 @@ ; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 24 ; LMULMAX1-RV64-NEXT: vse32.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -834,6 +857,7 @@ ; LMULMAX2-RV32-NEXT: addi a1, zero, 56 ; LMULMAX2-RV32-NEXT: vsrl.vx v26, v26, a1 ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v4i64: @@ -884,6 +908,7 @@ ; LMULMAX2-RV64-NEXT: addi a1, zero, 56 ; LMULMAX2-RV64-NEXT: vsrl.vx v26, v26, a1 ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v4i64: @@ -939,6 +964,7 @@ ; LMULMAX1-RV32-NEXT: vsrl.vx v26, v26, a2 ; LMULMAX1-RV32-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v25, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v4i64: @@ -1004,6 +1030,7 @@ ; LMULMAX1-RV64-NEXT: vsrl.vx v26, v26, a1 ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v25, (a6) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll @@ -328,6 +328,7 @@ ; LMULMAX2-RV32-NEXT: vle8.v v25, (a1) ; LMULMAX2-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v16i8: @@ -675,6 +676,7 @@ ; LMULMAX2-RV64-NEXT: vle8.v v25, (a1) ; LMULMAX2-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v16i8: @@ -1000,6 +1002,7 @@ ; LMULMAX1-RV32-NEXT: vle8.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v16i8: @@ -1347,6 +1350,7 @@ ; LMULMAX1-RV64-NEXT: vle8.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1529,6 +1533,7 @@ ; LMULMAX2-RV32-NEXT: vle16.v v25, (a1) ; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v8i16: @@ -1725,6 +1730,7 @@ ; LMULMAX2-RV64-NEXT: vle16.v v25, (a1) ; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v8i16: @@ -1899,6 +1905,7 @@ ; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v8i16: @@ -2095,6 +2102,7 @@ ; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -2196,6 +2204,7 @@ ; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) ; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v4i32: @@ -2317,6 +2326,7 @@ ; LMULMAX2-RV64-NEXT: vle32.v v25, (a1) ; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v4i32: @@ -2410,6 +2420,7 @@ ; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v4i32: @@ -2531,6 +2542,7 @@ ; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -2647,6 +2659,7 @@ ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v2i64: @@ -2722,6 +2735,7 @@ ; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v2i64: @@ -2830,6 +2844,7 @@ ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v2i64: @@ -2905,6 +2920,7 @@ ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -3551,8 +3567,12 @@ ; LMULMAX2-RV32-NEXT: vse8.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v32i8: @@ -4213,8 +4233,12 @@ ; LMULMAX2-RV64-NEXT: vse8.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v32i8: @@ -4848,6 +4872,7 @@ ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v32i8: @@ -5503,6 +5528,7 @@ ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -5845,8 +5871,12 @@ ; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v16i16: @@ -6203,8 +6233,12 @@ ; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v16i16: @@ -6535,6 +6569,7 @@ ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v16i16: @@ -6887,6 +6922,7 @@ ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -7068,8 +7104,12 @@ ; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v8i32: @@ -7275,8 +7315,12 @@ ; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v8i32: @@ -7446,6 +7490,7 @@ ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v8i32: @@ -7647,6 +7692,7 @@ ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -7855,8 +7901,12 @@ ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload +; LMULMAX2-RV32-NEXT: .cfi_restore ra +; LMULMAX2-RV32-NEXT: .cfi_restore s0 ; LMULMAX2-RV32-NEXT: addi sp, sp, 96 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v4i64: @@ -7980,8 +8030,12 @@ ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi sp, s0, -96 ; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_def_cfa sp, 96 ; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload +; LMULMAX2-RV64-NEXT: .cfi_restore ra +; LMULMAX2-RV64-NEXT: .cfi_restore s0 ; LMULMAX2-RV64-NEXT: addi sp, sp, 96 +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v4i64: @@ -8178,6 +8232,7 @@ ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a7) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v4i64: @@ -8294,6 +8349,7 @@ ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v27, (a6) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll @@ -14,6 +14,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -46,6 +47,7 @@ ; RV32-NEXT: sw a5, 0(a0) ; RV32-NEXT: sw a1, 12(a0) ; RV32-NEXT: sw a3, 4(a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: add_v2i64: @@ -58,6 +60,7 @@ ; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: sd a1, 8(a0) ; RV64-NEXT: sd a3, 0(a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -75,6 +78,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load <2 x i32>, <2 x i32>* %y @@ -97,6 +101,7 @@ ; RV32-NEXT: add a2, a3, a2 ; RV32-NEXT: sw a1, 0(a0) ; RV32-NEXT: sw a2, 4(a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: add_v1i64: @@ -105,6 +110,7 @@ ; RV64-NEXT: ld a1, 0(a1) ; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: sd a1, 0(a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <1 x i64>, <1 x i64>* %x %b = load <1 x i64>, <1 x i64>* %y @@ -122,6 +128,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfadd.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -142,6 +149,7 @@ ; CHECK-NEXT: fadd.d ft0, ft0, ft3 ; CHECK-NEXT: fsd ft0, 8(a0) ; CHECK-NEXT: fsd ft1, 0(a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -159,6 +167,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfadd.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %b = load <2 x float>, <2 x float>* %y @@ -175,6 +184,7 @@ ; CHECK-NEXT: fld ft1, 0(a1) ; CHECK-NEXT: fadd.d ft0, ft0, ft1 ; CHECK-NEXT: fsd ft0, 0(a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <1 x double>, <1 x double>* %x %b = load <1 x double>, <1 x double>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll @@ -12,6 +12,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i1>, <2 x i1>* %x %z = sext <2 x i1> %y to <2 x i16> @@ -25,6 +26,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = sext <2 x i8> %y to <2 x i16> @@ -38,6 +40,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = zext <2 x i8> %y to <2 x i16> @@ -51,6 +54,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = sext <2 x i8> %y to <2 x i32> @@ -64,6 +68,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = zext <2 x i8> %y to <2 x i32> @@ -77,6 +82,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = sext <2 x i8> %y to <2 x i64> @@ -90,6 +96,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = zext <2 x i8> %y to <2 x i64> @@ -103,6 +110,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = sext <4 x i8> %y to <4 x i16> @@ -116,6 +124,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = zext <4 x i8> %y to <4 x i16> @@ -129,6 +138,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = sext <4 x i8> %y to <4 x i32> @@ -142,6 +152,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = zext <4 x i8> %y to <4 x i32> @@ -158,6 +169,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf8 v9, v26 ; LMULMAX1-NEXT: vsext.vf8 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v4i8_v4i64: @@ -166,6 +178,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; LMULMAX4-NEXT: vsext.vf8 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = sext <4 x i8> %y to <4 x i64> @@ -182,6 +195,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf8 v9, v26 ; LMULMAX1-NEXT: vzext.vf8 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v4i8_v4i64: @@ -190,6 +204,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; LMULMAX4-NEXT: vzext.vf8 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = zext <4 x i8> %y to <4 x i64> @@ -203,6 +218,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = sext <8 x i8> %y to <8 x i16> @@ -216,6 +232,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = zext <8 x i8> %y to <8 x i16> @@ -232,6 +249,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf4 v9, v26 ; LMULMAX1-NEXT: vsext.vf4 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i8_v8i32: @@ -240,6 +258,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vsext.vf4 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = sext <8 x i8> %y to <8 x i32> @@ -256,6 +275,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf4 v9, v26 ; LMULMAX1-NEXT: vzext.vf4 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i8_v8i32: @@ -264,6 +284,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vzext.vf4 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = zext <8 x i8> %y to <8 x i32> @@ -288,6 +309,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf8 v11, v26 ; LMULMAX1-NEXT: vsext.vf8 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i8_v8i64: @@ -296,6 +318,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf8 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = sext <8 x i8> %y to <8 x i64> @@ -320,6 +343,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf8 v11, v26 ; LMULMAX1-NEXT: vzext.vf8 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i8_v8i64: @@ -328,6 +352,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf8 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = zext <8 x i8> %y to <8 x i64> @@ -344,6 +369,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf2 v9, v26 ; LMULMAX1-NEXT: vsext.vf2 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i8_v16i16: @@ -352,6 +378,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; LMULMAX4-NEXT: vsext.vf2 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = sext <16 x i8> %y to <16 x i16> @@ -368,6 +395,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf2 v9, v26 ; LMULMAX1-NEXT: vzext.vf2 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i8_v16i16: @@ -376,6 +404,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; LMULMAX4-NEXT: vzext.vf2 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = zext <16 x i8> %y to <16 x i16> @@ -400,6 +429,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf4 v11, v26 ; LMULMAX1-NEXT: vsext.vf4 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i8_v16i32: @@ -408,6 +438,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf4 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = sext <16 x i8> %y to <16 x i32> @@ -432,6 +463,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf4 v11, v26 ; LMULMAX1-NEXT: vzext.vf4 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i8_v16i32: @@ -440,6 +472,7 @@ ; LMULMAX4-NEXT: vle8.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf4 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = zext <16 x i8> %y to <16 x i32> @@ -480,6 +513,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf8 v15, v26 ; LMULMAX1-NEXT: vsext.vf8 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i8_v16i64: @@ -491,6 +525,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf8 v12, v26 ; LMULMAX4-NEXT: vsext.vf8 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = sext <16 x i8> %y to <16 x i64> @@ -531,6 +566,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf8 v15, v26 ; LMULMAX1-NEXT: vzext.vf8 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i8_v16i64: @@ -542,6 +578,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf8 v12, v26 ; LMULMAX4-NEXT: vzext.vf8 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = zext <16 x i8> %y to <16 x i64> @@ -563,6 +600,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <2 x i8> %x to <2 x i1> store <2 x i1> %y, <2 x i1>* %z @@ -575,6 +613,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <2 x i16> %x to <2 x i8> store <2 x i8> %y, <2 x i8>* %z @@ -588,6 +627,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i16>, <2 x i16>* %x %z = sext <2 x i16> %y to <2 x i32> @@ -601,6 +641,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i16>, <2 x i16>* %x %z = zext <2 x i16> %y to <2 x i32> @@ -614,6 +655,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i16>, <2 x i16>* %x %z = sext <2 x i16> %y to <2 x i64> @@ -627,6 +669,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i16>, <2 x i16>* %x %z = zext <2 x i16> %y to <2 x i64> @@ -639,6 +682,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <4 x i16> %x to <4 x i8> store <4 x i8> %y, <4 x i8>* %z @@ -652,6 +696,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <4 x i16>, <4 x i16>* %x %z = sext <4 x i16> %y to <4 x i32> @@ -665,6 +710,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <4 x i16>, <4 x i16>* %x %z = zext <4 x i16> %y to <4 x i32> @@ -681,6 +727,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf4 v9, v26 ; LMULMAX1-NEXT: vsext.vf4 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v4i16_v4i64: @@ -689,6 +736,7 @@ ; LMULMAX4-NEXT: vle16.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; LMULMAX4-NEXT: vsext.vf4 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <4 x i16>, <4 x i16>* %x %z = sext <4 x i16> %y to <4 x i64> @@ -705,6 +753,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf4 v9, v26 ; LMULMAX1-NEXT: vzext.vf4 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v4i16_v4i64: @@ -713,6 +762,7 @@ ; LMULMAX4-NEXT: vle16.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; LMULMAX4-NEXT: vzext.vf4 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <4 x i16>, <4 x i16>* %x %z = zext <4 x i16> %y to <4 x i64> @@ -725,6 +775,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <8 x i16> %x to <8 x i8> store <8 x i8> %y, <8 x i8>* %z @@ -741,6 +792,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf2 v9, v26 ; LMULMAX1-NEXT: vsext.vf2 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i16_v8i32: @@ -749,6 +801,7 @@ ; LMULMAX4-NEXT: vle16.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vsext.vf2 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i16>, <8 x i16>* %x %z = sext <8 x i16> %y to <8 x i32> @@ -765,6 +818,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf2 v9, v26 ; LMULMAX1-NEXT: vzext.vf2 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i16_v8i32: @@ -773,6 +827,7 @@ ; LMULMAX4-NEXT: vle16.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vzext.vf2 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i16>, <8 x i16>* %x %z = zext <8 x i16> %y to <8 x i32> @@ -797,6 +852,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf4 v11, v26 ; LMULMAX1-NEXT: vsext.vf4 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i16_v8i64: @@ -805,6 +861,7 @@ ; LMULMAX4-NEXT: vle16.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf4 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i16>, <8 x i16>* %x %z = sext <8 x i16> %y to <8 x i64> @@ -829,6 +886,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf4 v11, v26 ; LMULMAX1-NEXT: vzext.vf4 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i16_v8i64: @@ -837,6 +895,7 @@ ; LMULMAX4-NEXT: vle16.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf4 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i16>, <8 x i16>* %x %z = zext <8 x i16> %y to <8 x i64> @@ -857,6 +916,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 8 ; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i16_v16i8: @@ -864,6 +924,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 ; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <16 x i16> %x to <16 x i8> store <16 x i8> %y, <16 x i8>* %z @@ -887,6 +948,7 @@ ; LMULMAX1-NEXT: vsext.vf2 v11, v27 ; LMULMAX1-NEXT: vsext.vf2 v8, v25 ; LMULMAX1-NEXT: vsext.vf2 v10, v26 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i16_v16i32: @@ -895,6 +957,7 @@ ; LMULMAX4-NEXT: vle16.v v26, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf2 v8, v26 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i16>, <16 x i16>* %x %z = sext <16 x i16> %y to <16 x i32> @@ -918,6 +981,7 @@ ; LMULMAX1-NEXT: vzext.vf2 v11, v27 ; LMULMAX1-NEXT: vzext.vf2 v8, v25 ; LMULMAX1-NEXT: vzext.vf2 v10, v26 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i16_v16i32: @@ -926,6 +990,7 @@ ; LMULMAX4-NEXT: vle16.v v26, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf2 v8, v26 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i16>, <16 x i16>* %x %z = zext <16 x i16> %y to <16 x i32> @@ -965,6 +1030,7 @@ ; LMULMAX1-NEXT: vsext.vf4 v15, v27 ; LMULMAX1-NEXT: vsext.vf4 v8, v25 ; LMULMAX1-NEXT: vsext.vf4 v12, v26 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i16_v16i64: @@ -976,6 +1042,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf4 v12, v28 ; LMULMAX4-NEXT: vsext.vf4 v8, v26 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i16>, <16 x i16>* %x %z = sext <16 x i16> %y to <16 x i64> @@ -1015,6 +1082,7 @@ ; LMULMAX1-NEXT: vzext.vf4 v15, v27 ; LMULMAX1-NEXT: vzext.vf4 v8, v25 ; LMULMAX1-NEXT: vzext.vf4 v12, v26 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i16_v16i64: @@ -1026,6 +1094,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf4 v12, v28 ; LMULMAX4-NEXT: vzext.vf4 v8, v26 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i16>, <16 x i16>* %x %z = zext <16 x i16> %y to <16 x i64> @@ -1040,6 +1109,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <2 x i32> %x to <2 x i8> store <2 x i8> %y, <2 x i8>* %z @@ -1052,6 +1122,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <2 x i32> %x to <2 x i16> store <2 x i16> %y, <2 x i16>* %z @@ -1065,6 +1136,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i32>, <2 x i32>* %x %z = sext <2 x i32> %y to <2 x i64> @@ -1078,6 +1150,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load <2 x i32>, <2 x i32>* %x %z = zext <2 x i32> %y to <2 x i64> @@ -1092,6 +1165,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <4 x i32> %x to <4 x i8> store <4 x i8> %y, <4 x i8>* %z @@ -1104,6 +1178,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <4 x i32> %x to <4 x i16> store <4 x i16> %y, <4 x i16>* %z @@ -1120,6 +1195,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsext.vf2 v9, v26 ; LMULMAX1-NEXT: vsext.vf2 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v4i32_v4i64: @@ -1128,6 +1204,7 @@ ; LMULMAX4-NEXT: vle32.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; LMULMAX4-NEXT: vsext.vf2 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <4 x i32>, <4 x i32>* %x %z = sext <4 x i32> %y to <4 x i64> @@ -1144,6 +1221,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vzext.vf2 v9, v26 ; LMULMAX1-NEXT: vzext.vf2 v8, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v4i32_v4i64: @@ -1152,6 +1230,7 @@ ; LMULMAX4-NEXT: vle32.v v25, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; LMULMAX4-NEXT: vzext.vf2 v8, v25 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <4 x i32>, <4 x i32>* %x %z = zext <4 x i32> %y to <4 x i64> @@ -1176,6 +1255,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 ; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i32_v8i8: @@ -1185,6 +1265,7 @@ ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 ; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <8 x i32> %x to <8 x i8> store <8 x i8> %y, <8 x i8>* %z @@ -1205,6 +1286,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 ; LMULMAX1-NEXT: vse16.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i32_v8i16: @@ -1212,6 +1294,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 ; LMULMAX4-NEXT: vse16.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <8 x i32> %x to <8 x i16> store <8 x i16> %y, <8 x i16>* %z @@ -1235,6 +1318,7 @@ ; LMULMAX1-NEXT: vsext.vf2 v11, v27 ; LMULMAX1-NEXT: vsext.vf2 v8, v25 ; LMULMAX1-NEXT: vsext.vf2 v10, v26 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i32_v8i64: @@ -1243,6 +1327,7 @@ ; LMULMAX4-NEXT: vle32.v v26, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf2 v8, v26 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i32>, <8 x i32>* %x %z = sext <8 x i32> %y to <8 x i64> @@ -1266,6 +1351,7 @@ ; LMULMAX1-NEXT: vzext.vf2 v11, v27 ; LMULMAX1-NEXT: vzext.vf2 v8, v25 ; LMULMAX1-NEXT: vzext.vf2 v10, v26 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i32_v8i64: @@ -1274,6 +1360,7 @@ ; LMULMAX4-NEXT: vle32.v v26, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf2 v8, v26 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <8 x i32>, <8 x i32>* %x %z = zext <8 x i32> %y to <8 x i64> @@ -1310,6 +1397,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 12 ; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i32_v16i8: @@ -1319,6 +1407,7 @@ ; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0 ; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <16 x i32> %x to <16 x i8> store <16 x i8> %y, <16 x i8>* %z @@ -1350,6 +1439,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse16.v v26, (a1) ; LMULMAX1-NEXT: vse16.v v27, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i32_v16i16: @@ -1357,6 +1447,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 ; LMULMAX4-NEXT: vse16.v v26, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <16 x i32> %x to <16 x i16> store <16 x i16> %y, <16 x i16>* %z @@ -1394,6 +1485,7 @@ ; LMULMAX1-NEXT: vsext.vf2 v10, v28 ; LMULMAX1-NEXT: vsext.vf2 v12, v26 ; LMULMAX1-NEXT: vsext.vf2 v14, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i32_v16i64: @@ -1405,6 +1497,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf2 v12, v8 ; LMULMAX4-NEXT: vsext.vf2 v8, v28 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i32>, <16 x i32>* %x %z = sext <16 x i32> %y to <16 x i64> @@ -1442,6 +1535,7 @@ ; LMULMAX1-NEXT: vzext.vf2 v10, v28 ; LMULMAX1-NEXT: vzext.vf2 v12, v26 ; LMULMAX1-NEXT: vzext.vf2 v14, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i32_v16i64: @@ -1453,6 +1547,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf2 v12, v8 ; LMULMAX4-NEXT: vzext.vf2 v8, v28 +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = load <16 x i32>, <16 x i32>* %x %z = zext <16 x i32> %y to <16 x i64> @@ -1469,6 +1564,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <2 x i64> %x to <2 x i8> store <2 x i8> %y, <2 x i8>* %z @@ -1483,6 +1579,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <2 x i64> %x to <2 x i16> store <2 x i16> %y, <2 x i16>* %z @@ -1495,6 +1592,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = trunc <2 x i64> %x to <2 x i32> store <2 x i32> %y, <2 x i32>* %z @@ -1523,6 +1621,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 ; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v4i64_v4i8: @@ -1534,6 +1633,7 @@ ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 ; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <4 x i64> %x to <4 x i8> store <4 x i8> %y, <4 x i8>* %z @@ -1558,6 +1658,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 ; LMULMAX1-NEXT: vse16.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v4i64_v4i16: @@ -1567,6 +1668,7 @@ ; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 ; LMULMAX4-NEXT: vse16.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <4 x i64> %x to <4 x i16> store <4 x i16> %y, <4 x i16>* %z @@ -1587,6 +1689,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 ; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v4i64_v4i32: @@ -1594,6 +1697,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 ; LMULMAX4-NEXT: vse32.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <4 x i64> %x to <4 x i32> store <4 x i32> %y, <4 x i32>* %z @@ -1638,6 +1742,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 6 ; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i64_v8i8: @@ -1649,6 +1754,7 @@ ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 ; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <8 x i64> %x to <8 x i8> store <8 x i8> %y, <8 x i8>* %z @@ -1685,6 +1791,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 6 ; LMULMAX1-NEXT: vse16.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i64_v8i16: @@ -1694,6 +1801,7 @@ ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0 ; LMULMAX4-NEXT: vse16.v v25, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <8 x i64> %x to <8 x i16> store <8 x i16> %y, <8 x i16>* %z @@ -1725,6 +1833,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse32.v v26, (a1) ; LMULMAX1-NEXT: vse32.v v27, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i64_v8i32: @@ -1732,6 +1841,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 ; LMULMAX4-NEXT: vse32.v v26, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <8 x i64> %x to <8 x i32> store <8 x i32> %y, <8 x i32>* %z @@ -1808,6 +1918,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v25, v26, 14 ; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i64_v16i8: @@ -1831,6 +1942,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX4-NEXT: vslideup.vi v26, v25, 8 ; LMULMAX4-NEXT: vse8.v v26, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <16 x i64> %x to <16 x i8> store <16 x i8> %y, <16 x i8>* %z @@ -1894,6 +2006,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse16.v v26, (a1) ; LMULMAX1-NEXT: vse16.v v27, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i64_v16i16: @@ -1913,6 +2026,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, tu, mu ; LMULMAX4-NEXT: vslideup.vi v26, v28, 8 ; LMULMAX4-NEXT: vse16.v v26, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <16 x i64> %x to <16 x i16> store <16 x i16> %y, <16 x i16>* %z @@ -1966,6 +2080,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse32.v v28, (a1) ; LMULMAX1-NEXT: vse32.v v27, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i64_v16i32: @@ -1980,6 +2095,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX4-NEXT: vslideup.vi v8, v28, 8 ; LMULMAX4-NEXT: vse32.v v8, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret %y = trunc <16 x i64> %x to <16 x i32> store <16 x i32> %y, <16 x i32>* %z @@ -1992,6 +2108,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2006,6 +2123,7 @@ ; CHECK-NEXT: vfwcvt.f.f.v v26, v25 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2018,6 +2136,7 @@ ; CHECK-NEXT: vl1re16.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2032,6 +2151,7 @@ ; CHECK-NEXT: vfwcvt.f.f.v v26, v25 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2044,6 +2164,7 @@ ; CHECK-NEXT: vl2re16.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2058,6 +2179,7 @@ ; CHECK-NEXT: vfwcvt.f.f.v v28, v26 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2070,6 +2192,7 @@ ; CHECK-NEXT: vl4re16.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2088,6 +2211,7 @@ ; CHECK-NEXT: vfwcvt.f.f.v v24, v30 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v16, v24 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2100,6 +2224,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v8 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2112,6 +2237,7 @@ ; CHECK-NEXT: vl1re32.v v25, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2124,6 +2250,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v8 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2136,6 +2263,7 @@ ; CHECK-NEXT: vl2re32.v v26, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2148,6 +2276,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v8 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2160,6 +2289,7 @@ ; CHECK-NEXT: vl4re32.v v28, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2172,6 +2302,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v28, v8 ; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2185,6 +2316,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v24 ; CHECK-NEXT: vfwcvt.f.f.v v16, v28 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2199,6 +2331,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v25 ; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2211,6 +2344,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v8 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2225,6 +2359,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v26 ; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2237,6 +2372,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v8 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2251,6 +2387,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v28 ; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2263,6 +2400,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v28, v8 ; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2281,6 +2419,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v10, v28 ; CHECK-NEXT: vs4r.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z @@ -2294,6 +2433,7 @@ ; CHECK-NEXT: vfncvt.f.f.w v24, v8 ; CHECK-NEXT: vfncvt.f.f.w v28, v16 ; CHECK-NEXT: vs8r.v v24, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = fptrunc %x to store %y, * %z diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll @@ -9,6 +9,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 0) @@ -25,6 +26,7 @@ ; CHECK-NEXT: vslidedown.vi v25, v25, 2 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 2) @@ -39,6 +41,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 0) @@ -55,6 +58,7 @@ ; CHECK-NEXT: vslidedown.vi v25, v25, 6 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 6) @@ -69,6 +73,7 @@ ; LMULMAX2-NEXT: vle32.v v26, (a0) ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vse32.v v26, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i32_v8i32_0: @@ -77,6 +82,7 @@ ; LMULMAX1-NEXT: vle32.v v25, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0) @@ -93,6 +99,7 @@ ; LMULMAX2-NEXT: vslidedown.vi v26, v26, 2 ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vse32.v v26, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i32_v8i32_2: @@ -103,6 +110,7 @@ ; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2) @@ -119,6 +127,7 @@ ; LMULMAX2-NEXT: vslidedown.vi v26, v26, 6 ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vse32.v v26, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i32_v8i32_6: @@ -130,6 +139,7 @@ ; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6) @@ -142,6 +152,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.nxv16i32( %x, i64 0) store <2 x i32> %c, <2 x i32>* %y @@ -155,6 +166,7 @@ ; CHECK-NEXT: vslidedown.vi v8, v8, 6 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.nxv16i32( %x, i64 6) store <2 x i32> %c, <2 x i32>* %y @@ -166,6 +178,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8( %x, i64 0) store <2 x i8> %c, <2 x i8>* %y @@ -179,6 +192,7 @@ ; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8( %x, i64 2) store <2 x i8> %c, <2 x i8>* %y @@ -192,6 +206,7 @@ ; LMULMAX2-NEXT: vslidedown.vi v8, v8, 8 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vse32.v v8, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v8i32_nxv16i32_8: @@ -203,6 +218,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: vse32.v v16, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %c = call <8 x i32> @llvm.experimental.vector.extract.v8i32.nxv16i32( %x, i64 8) store <8 x i32> %c, <8 x i32>* %y @@ -217,6 +233,7 @@ ; LMULMAX2-NEXT: vlm.v v25, (a0) ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v8i1_v64i1_0: @@ -225,6 +242,7 @@ ; LMULMAX1-NEXT: vlm.v v25, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0) @@ -242,6 +260,7 @@ ; LMULMAX2-NEXT: vslidedown.vi v25, v25, 1 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v8i1_v64i1_8: @@ -252,6 +271,7 @@ ; LMULMAX1-NEXT: vslidedown.vi v25, v25, 1 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8) @@ -270,6 +290,7 @@ ; LMULMAX2-NEXT: vslidedown.vi v25, v25, 2 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v8i1_v64i1_48: @@ -279,6 +300,7 @@ ; LMULMAX1-NEXT: vlm.v v25, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48) @@ -291,6 +313,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsm.v v0, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv2i1( %x, i64 0) store <8 x i1> %c, <8 x i1>* %y @@ -302,6 +325,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsm.v v0, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1( %x, i64 0) store <8 x i1> %c, <8 x i1>* %y @@ -315,6 +339,7 @@ ; CHECK-NEXT: vslidedown.vi v25, v0, 1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1( %x, i64 8) store <8 x i1> %c, <8 x i1>* %y @@ -328,6 +353,7 @@ ; CHECK-NEXT: vslidedown.vi v25, v0, 6 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1( %x, i64 48) store <8 x i1> %c, <8 x i1>* %y @@ -351,6 +377,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i1_v64i1_0: @@ -367,6 +394,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0) @@ -395,6 +423,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i1_v64i1_2: @@ -416,6 +445,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2) @@ -445,6 +475,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i1_v64i1_42: @@ -467,6 +498,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42) @@ -487,6 +519,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1( %x, i64 0) store <2 x i1> %c, <2 x i1>* %y @@ -512,6 +545,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1( %x, i64 2) store <2 x i1> %c, <2 x i1>* %y @@ -531,6 +565,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1( %x, i64 0) store <2 x i1> %c, <2 x i1>* %y @@ -556,6 +591,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1( %x, i64 2) store <2 x i1> %c, <2 x i1>* %y @@ -582,6 +618,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1( %x, i64 42) store <2 x i1> %c, <2 x i1>* %y @@ -607,6 +644,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1( %x, i64 26) store <2 x i1> %c, <2 x i1>* %y @@ -620,6 +658,7 @@ ; CHECK-NEXT: vslidedown.vi v25, v0, 2 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv32i1( %x, i64 16) store <8 x i1> %c, <8 x i1>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll @@ -7,6 +7,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <1 x half> %a to i16 ret i16 %b @@ -18,6 +19,7 @@ ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fmv.x.h a0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <1 x half> %a to half ret half %b @@ -28,6 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <2 x half> %a to i32 ret i32 %b @@ -38,6 +41,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast <1 x float> %a to i32 ret i32 %b @@ -48,6 +52,7 @@ ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; RV32-FP-NEXT: vmv.x.s a0, v8 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_v2f16_f32: @@ -55,6 +60,7 @@ ; RV64-FP-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; RV64-FP-NEXT: vfmv.f.s ft0, v8 ; RV64-FP-NEXT: fmv.x.w a0, ft0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast <2 x half> %a to float ret float %b @@ -65,6 +71,7 @@ ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; RV32-FP-NEXT: vmv.x.s a0, v8 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_v1f32_f32: @@ -72,6 +79,7 @@ ; RV64-FP-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; RV64-FP-NEXT: vfmv.f.s ft0, v8 ; RV64-FP-NEXT: fmv.x.w a0, ft0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast <1 x float> %a to float ret float %b @@ -85,12 +93,14 @@ ; RV32-FP-NEXT: vsrl.vx v25, v8, a0 ; RV32-FP-NEXT: vmv.x.s a1, v25 ; RV32-FP-NEXT: vmv.x.s a0, v8 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_v4f16_i64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.x.s a0, v8 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast <4 x half> %a to i64 ret i64 %b @@ -104,12 +114,14 @@ ; RV32-FP-NEXT: vsrl.vx v25, v8, a0 ; RV32-FP-NEXT: vmv.x.s a1, v25 ; RV32-FP-NEXT: vmv.x.s a0, v8 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_v2f32_i64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.x.s a0, v8 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast <2 x float> %a to i64 ret i64 %b @@ -123,12 +135,14 @@ ; RV32-FP-NEXT: vsrl.vx v25, v8, a0 ; RV32-FP-NEXT: vmv.x.s a1, v25 ; RV32-FP-NEXT: vmv.x.s a0, v8 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_v1f64_i64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.x.s a0, v8 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast <1 x double> %a to i64 ret i64 %b @@ -145,12 +159,14 @@ ; RV32-FP-NEXT: lw a0, 8(sp) ; RV32-FP-NEXT: lw a1, 12(sp) ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_v4f16_f64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.x.s a0, v8 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast <4 x half> %a to double ret double %b @@ -167,12 +183,14 @@ ; RV32-FP-NEXT: lw a0, 8(sp) ; RV32-FP-NEXT: lw a1, 12(sp) ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_v2f32_f64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.x.s a0, v8 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast <2 x float> %a to double ret double %b @@ -189,12 +207,14 @@ ; RV32-FP-NEXT: lw a0, 8(sp) ; RV32-FP-NEXT: lw a1, 12(sp) ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_v1f64_f64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.x.s a0, v8 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast <1 x double> %a to double ret double %b @@ -205,6 +225,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast i16 %a to <1 x half> ret <1 x half> %b @@ -215,12 +236,14 @@ ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-FP-NEXT: vmv.s.x v8, a0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_i32_v2f16: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-FP-NEXT: vmv.v.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast i32 %a to <2 x half> ret <2 x half> %b @@ -231,12 +254,14 @@ ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-FP-NEXT: vmv.s.x v8, a0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_i32_v1f32: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-FP-NEXT: vmv.v.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast i32 %a to <1 x float> ret <1 x float> %b @@ -251,12 +276,14 @@ ; RV32-FP-NEXT: vslide1up.vx v25, v26, a0 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vslideup.vi v8, v25, 0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_i64_v4f16: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast i64 %a to <4 x half> ret <4 x half> %b @@ -271,12 +298,14 @@ ; RV32-FP-NEXT: vslide1up.vx v25, v26, a0 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vslideup.vi v8, v25, 0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_i64_v2f32: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast i64 %a to <2 x float> ret <2 x float> %b @@ -291,12 +320,14 @@ ; RV32-FP-NEXT: vslide1up.vx v25, v26, a0 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vslideup.vi v8, v25, 0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_i64_v1f64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast i64 %a to <1 x double> ret <1 x double> %b @@ -308,6 +339,7 @@ ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vfmv.s.f v8, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast half %a to <1 x i16> ret <1 x i16> %b @@ -319,6 +351,7 @@ ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vfmv.s.f v8, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %b = bitcast half %a to <1 x half> ret <1 x half> %b @@ -329,6 +362,7 @@ ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-FP-NEXT: vmv.s.x v8, a0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f32_v2i16: @@ -336,6 +370,7 @@ ; RV64-FP-NEXT: fmv.w.x ft0, a0 ; RV64-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-FP-NEXT: vfmv.s.f v8, ft0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast float %a to <2 x i16> ret <2 x i16> %b @@ -346,6 +381,7 @@ ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-FP-NEXT: vmv.s.x v8, a0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f32_v2f16: @@ -353,6 +389,7 @@ ; RV64-FP-NEXT: fmv.w.x ft0, a0 ; RV64-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-FP-NEXT: vfmv.s.f v8, ft0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast float %a to <2 x half> ret <2 x half> %b @@ -363,6 +400,7 @@ ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-FP-NEXT: vmv.s.x v8, a0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f32_v1i32: @@ -370,6 +408,7 @@ ; RV64-FP-NEXT: fmv.w.x ft0, a0 ; RV64-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-FP-NEXT: vfmv.s.f v8, ft0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast float %a to <1 x i32> ret <1 x i32> %b @@ -380,6 +419,7 @@ ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-FP-NEXT: vmv.s.x v8, a0 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f32_v1f32: @@ -387,6 +427,7 @@ ; RV64-FP-NEXT: fmv.w.x ft0, a0 ; RV64-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-FP-NEXT: vfmv.s.f v8, ft0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast float %a to <1 x float> ret <1 x float> %b @@ -403,12 +444,14 @@ ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vfmv.s.f v8, ft0 ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f64_v4i16: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast double %a to <4 x i16> ret <4 x i16> %b @@ -425,12 +468,14 @@ ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vfmv.s.f v8, ft0 ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f64_v4f16: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast double %a to <4 x half> ret <4 x half> %b @@ -447,12 +492,14 @@ ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vfmv.s.f v8, ft0 ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f64_v2i32: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast double %a to <2 x i32> ret <2 x i32> %b @@ -469,12 +516,14 @@ ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vfmv.s.f v8, ft0 ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f64_v2f32: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast double %a to <2 x float> ret <2 x float> %b @@ -491,12 +540,14 @@ ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vfmv.s.f v8, ft0 ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f64_v1i64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast double %a to <1 x i64> ret <1 x i64> %b @@ -513,12 +564,14 @@ ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-FP-NEXT: vfmv.s.f v8, ft0 ; RV32-FP-NEXT: addi sp, sp, 16 +; RV32-FP-NEXT: .cfi_def_cfa_offset 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_f64_v1f64: ; RV64-FP: # %bb.0: ; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-FP-NEXT: vmv.s.x v8, a0 +; RV64-FP-NEXT: .cfi_def_cfa_offset 0 ; RV64-FP-NEXT: ret %b = bitcast double %a to <1 x double> ret <1 x double> %b diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll @@ -15,6 +15,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vle32.v v25, (a1) ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x float> , <4 x float>* %x ret void @@ -53,6 +54,7 @@ ; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: addi sp, sp, 32 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: hang_when_merging_stores_after_legalization: @@ -74,6 +76,7 @@ ; LMULMAX2-NEXT: vmv.s.x v0, a0 ; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-NEXT: vmerge.vvm v8, v26, v25, v0 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> ret <4 x float> %z @@ -90,6 +93,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu ; CHECK-NEXT: vfmv.s.f v25, ft0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <2 x float> , <2 x float>* %x ret void @@ -106,6 +110,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a1) ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <2 x float> , <2 x float>* %x ret void @@ -124,6 +129,7 @@ ; CHECK-NEXT: vslideup.vi v25, v26, 2 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x float> , <4 x float>* %x ret void @@ -140,6 +146,7 @@ ; CHECK-NEXT: vslideup.vi v26, v25, 1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v0 = insertelement <4 x float> undef, float %f, i32 0 %v1 = insertelement <4 x float> %v0, float 0.0, i32 1 @@ -161,6 +168,7 @@ ; CHECK-NEXT: vslideup.vi v26, v25, 1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v0 = insertelement <4 x float> undef, float %f, i32 0 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll @@ -11,6 +11,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfwcvt.f.f.v v26, v25 ; CHECK-NEXT: vse32.v v26, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %d = fpext <2 x half> %a to <2 x float> @@ -27,6 +28,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v25, v26 ; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %d = fpext <2 x half> %a to <2 x double> @@ -41,6 +43,7 @@ ; LMULMAX8-NEXT: vle16.v v25, (a0) ; LMULMAX8-NEXT: vfwcvt.f.f.v v26, v25 ; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fpext_v8f16_v8f32: @@ -55,6 +58,7 @@ ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse32.v v27, (a0) ; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x half>, <8 x half>* %x %d = fpext <8 x half> %a to <8 x float> @@ -71,6 +75,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX8-NEXT: vfwcvt.f.f.v v28, v26 ; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fpext_v8f16_v8f64: @@ -106,6 +111,7 @@ ; LMULMAX1-NEXT: vse64.v v28, (a0) ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse64.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x half>, <8 x half>* %x %d = fpext <8 x half> %a to <8 x double> @@ -121,6 +127,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v26, v25 ; CHECK-NEXT: vse16.v v26, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptrunc <2 x float> %a to <2 x half> @@ -138,6 +145,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v26 ; CHECK-NEXT: vse16.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %d = fptrunc <2 x double> %a to <2 x half> @@ -153,6 +161,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX8-NEXT: vse16.v v25, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fpround_v8f32_v8f16: @@ -172,6 +181,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v25, v27, 4 ; LMULMAX1-NEXT: vse16.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptrunc <8 x float> %a to <8 x half> @@ -189,6 +199,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX8-NEXT: vse16.v v25, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fpround_v8f64_v8f16: @@ -228,6 +239,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 ; LMULMAX1-NEXT: vse16.v v29, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x double>, <8 x double>* %x %d = fptrunc <8 x double> %a to <8 x half> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll @@ -10,6 +10,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vmfeq.vv v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -26,6 +27,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vmfeq.vv v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -51,6 +53,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -76,6 +79,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -101,6 +105,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -126,6 +131,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -142,6 +148,7 @@ ; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: vmflt.vv v25, v26, v28 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -158,6 +165,7 @@ ; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: vmflt.vv v25, v26, v28 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -174,6 +182,7 @@ ; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: vmfle.vv v25, v28, v26 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -190,6 +199,7 @@ ; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: vmfle.vv v25, v28, v26 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -215,6 +225,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -240,6 +251,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -258,6 +270,7 @@ ; CHECK-NEXT: vmflt.vv v25, v8, v28 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = load <32 x half>, <32 x half>* %y @@ -275,6 +288,7 @@ ; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vmfle.vv v25, v28, v8 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = load <32 x half>, <32 x half>* %y @@ -292,6 +306,7 @@ ; CHECK-NEXT: vmflt.vv v25, v28, v8 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = load <16 x float>, <16 x float>* %y @@ -308,6 +323,7 @@ ; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vmfle.vv v25, v8, v28 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = load <16 x float>, <16 x float>* %y @@ -325,6 +341,7 @@ ; CHECK-NEXT: vmfle.vv v25, v8, v28 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = load <8 x double>, <8 x double>* %y @@ -341,6 +358,7 @@ ; CHECK-NEXT: vle64.v v8, (a1) ; CHECK-NEXT: vmflt.vv v25, v28, v8 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = load <8 x double>, <8 x double>* %y @@ -359,6 +377,7 @@ ; CHECK-NEXT: vmfle.vv v25, v8, v16 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = load <64 x half>, <64 x half>* %y @@ -376,6 +395,7 @@ ; CHECK-NEXT: vle16.v v16, (a1) ; CHECK-NEXT: vmflt.vv v25, v16, v8 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = load <64 x half>, <64 x half>* %y @@ -395,6 +415,7 @@ ; CHECK-NEXT: vmflt.vv v26, v16, v8 ; CHECK-NEXT: vmnor.mm v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = load <32 x float>, <32 x float>* %y @@ -412,6 +433,7 @@ ; CHECK-NEXT: vle32.v v16, (a1) ; CHECK-NEXT: vmfeq.vv v25, v8, v16 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = load <32 x float>, <32 x float>* %y @@ -430,6 +452,7 @@ ; CHECK-NEXT: vmflt.vv v26, v16, v8 ; CHECK-NEXT: vmor.mm v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = load <16 x double>, <16 x double>* %y @@ -446,6 +469,7 @@ ; CHECK-NEXT: vle64.v v16, (a1) ; CHECK-NEXT: vmfne.vv v25, v8, v16 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = load <16 x double>, <16 x double>* %y @@ -473,6 +497,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x half>, <4 x half>* %x %b = load <4 x half>, <4 x half>* %y @@ -500,6 +525,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %b = load <2 x half>, <2 x half>* %y @@ -515,6 +541,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmfeq.vf v25, v25, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -531,6 +558,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmfeq.vf v25, v25, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -556,6 +584,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -581,6 +610,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -606,6 +636,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -631,6 +662,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -647,6 +679,7 @@ ; CHECK-NEXT: vle16.v v26, (a0) ; CHECK-NEXT: vmflt.vf v25, v26, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = insertelement <16 x half> undef, half %y, i32 0 @@ -663,6 +696,7 @@ ; CHECK-NEXT: vle16.v v26, (a0) ; CHECK-NEXT: vmflt.vf v25, v26, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = insertelement <16 x half> undef, half %y, i32 0 @@ -679,6 +713,7 @@ ; CHECK-NEXT: vle32.v v26, (a0) ; CHECK-NEXT: vmfge.vf v25, v26, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> undef, float %y, i32 0 @@ -695,6 +730,7 @@ ; CHECK-NEXT: vle32.v v26, (a0) ; CHECK-NEXT: vmfge.vf v25, v26, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> undef, float %y, i32 0 @@ -720,6 +756,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = insertelement <4 x double> undef, double %y, i32 0 @@ -745,6 +782,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = insertelement <4 x double> undef, double %y, i32 0 @@ -763,6 +801,7 @@ ; CHECK-NEXT: vmfgt.vf v25, v28, fa0 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = insertelement <32 x half> undef, half %y, i32 0 @@ -780,6 +819,7 @@ ; CHECK-NEXT: vle16.v v28, (a0) ; CHECK-NEXT: vmfle.vf v25, v28, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = insertelement <32 x half> undef, half %y, i32 0 @@ -797,6 +837,7 @@ ; CHECK-NEXT: vmflt.vf v25, v28, fa0 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = insertelement <16 x float> undef, float %y, i32 0 @@ -813,6 +854,7 @@ ; CHECK-NEXT: vle32.v v28, (a0) ; CHECK-NEXT: vmfge.vf v25, v28, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = insertelement <16 x float> undef, float %y, i32 0 @@ -830,6 +872,7 @@ ; CHECK-NEXT: vmfge.vf v25, v28, fa0 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = insertelement <8 x double> undef, double %y, i32 0 @@ -846,6 +889,7 @@ ; CHECK-NEXT: vle64.v v28, (a0) ; CHECK-NEXT: vmflt.vf v25, v28, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = insertelement <8 x double> undef, double %y, i32 0 @@ -864,6 +908,7 @@ ; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = insertelement <64 x half> undef, half %y, i32 0 @@ -881,6 +926,7 @@ ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = insertelement <64 x half> undef, half %y, i32 0 @@ -900,6 +946,7 @@ ; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vmnor.mm v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = insertelement <32 x float> undef, float %y, i32 0 @@ -917,6 +964,7 @@ ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vmfeq.vf v25, v8, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = insertelement <32 x float> undef, float %y, i32 0 @@ -935,6 +983,7 @@ ; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vmor.mm v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = insertelement <16 x double> undef, double %y, i32 0 @@ -951,6 +1000,7 @@ ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vmfne.vf v25, v8, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = insertelement <16 x double> undef, double %y, i32 0 @@ -979,6 +1029,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x half>, <4 x half>* %x %b = insertelement <4 x half> undef, half %y, i32 0 @@ -1007,6 +1058,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %b = insertelement <2 x half> undef, half %y, i32 0 @@ -1023,6 +1075,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmfeq.vf v25, v25, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1039,6 +1092,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmfeq.vf v25, v25, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1064,6 +1118,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1089,6 +1144,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1114,6 +1170,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1139,6 +1196,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1155,6 +1213,7 @@ ; CHECK-NEXT: vle16.v v26, (a0) ; CHECK-NEXT: vmfgt.vf v25, v26, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = insertelement <16 x half> undef, half %y, i32 0 @@ -1171,6 +1230,7 @@ ; CHECK-NEXT: vle16.v v26, (a0) ; CHECK-NEXT: vmfgt.vf v25, v26, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = insertelement <16 x half> undef, half %y, i32 0 @@ -1187,6 +1247,7 @@ ; CHECK-NEXT: vle32.v v26, (a0) ; CHECK-NEXT: vmfle.vf v25, v26, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> undef, float %y, i32 0 @@ -1203,6 +1264,7 @@ ; CHECK-NEXT: vle32.v v26, (a0) ; CHECK-NEXT: vmfle.vf v25, v26, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> undef, float %y, i32 0 @@ -1228,6 +1290,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = insertelement <4 x double> undef, double %y, i32 0 @@ -1253,6 +1316,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = insertelement <4 x double> undef, double %y, i32 0 @@ -1271,6 +1335,7 @@ ; CHECK-NEXT: vmflt.vf v25, v28, fa0 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = insertelement <32 x half> undef, half %y, i32 0 @@ -1288,6 +1353,7 @@ ; CHECK-NEXT: vle16.v v28, (a0) ; CHECK-NEXT: vmfge.vf v25, v28, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = insertelement <32 x half> undef, half %y, i32 0 @@ -1305,6 +1371,7 @@ ; CHECK-NEXT: vmfgt.vf v25, v28, fa0 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = insertelement <16 x float> undef, float %y, i32 0 @@ -1321,6 +1388,7 @@ ; CHECK-NEXT: vle32.v v28, (a0) ; CHECK-NEXT: vmfle.vf v25, v28, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = insertelement <16 x float> undef, float %y, i32 0 @@ -1338,6 +1406,7 @@ ; CHECK-NEXT: vmfle.vf v25, v28, fa0 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = insertelement <8 x double> undef, double %y, i32 0 @@ -1354,6 +1423,7 @@ ; CHECK-NEXT: vle64.v v28, (a0) ; CHECK-NEXT: vmfgt.vf v25, v28, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = insertelement <8 x double> undef, double %y, i32 0 @@ -1372,6 +1442,7 @@ ; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = insertelement <64 x half> undef, half %y, i32 0 @@ -1389,6 +1460,7 @@ ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = insertelement <64 x half> undef, half %y, i32 0 @@ -1408,6 +1480,7 @@ ; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vmnor.mm v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = insertelement <32 x float> undef, float %y, i32 0 @@ -1425,6 +1498,7 @@ ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vmfeq.vf v25, v8, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = insertelement <32 x float> undef, float %y, i32 0 @@ -1443,6 +1517,7 @@ ; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vmor.mm v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = insertelement <16 x double> undef, double %y, i32 0 @@ -1459,6 +1534,7 @@ ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vmfne.vf v25, v8, fa0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = insertelement <16 x double> undef, double %y, i32 0 @@ -1487,6 +1563,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x half>, <4 x half>* %x %b = insertelement <4 x half> undef, half %y, i32 0 @@ -1515,6 +1592,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %b = insertelement <2 x half> undef, half %y, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll @@ -10,6 +10,7 @@ ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x half> %x, <4 x half> %y, <4 x i32> ret <4 x half> %s @@ -23,6 +24,7 @@ ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> ret <8 x float> %s @@ -38,6 +40,7 @@ ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: shuffle_fv_v4f64: @@ -49,6 +52,7 @@ ; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <4 x double> , <4 x double> %x, <4 x i32> ret <4 x double> %s @@ -64,6 +68,7 @@ ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: shuffle_vf_v4f64: @@ -75,6 +80,7 @@ ; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <4 x double> %x, <4 x double> , <4 x i32> ret <4 x double> %s @@ -90,6 +96,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32-NEXT: vrgatherei16.vv v26, v8, v25 ; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_permute_shuffle_vu_v4f64: @@ -100,6 +107,7 @@ ; RV64-NEXT: vle64.v v28, (a0) ; RV64-NEXT: vrgather.vv v26, v8, v28 ; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <4 x double> %x, <4 x double> undef, <4 x i32> ret <4 x double> %s @@ -115,6 +123,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32-NEXT: vrgatherei16.vv v26, v8, v25 ; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_permute_shuffle_uv_v4f64: @@ -125,6 +134,7 @@ ; RV64-NEXT: vle64.v v28, (a0) ; RV64-NEXT: vrgather.vv v26, v8, v28 ; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <4 x double> undef, <4 x double> %x, <4 x i32> ret <4 x double> %s @@ -145,6 +155,7 @@ ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vrgather.vi v26, v10, 1, v0.t ; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_vv_v4f64: @@ -160,6 +171,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vrgather.vi v26, v10, 1, v0.t ; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> ret <4 x double> %s @@ -180,6 +192,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32-NEXT: vrgatherei16.vv v26, v8, v25, v0.t ; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_xv_v4f64: @@ -195,6 +208,7 @@ ; RV64-NEXT: vrsub.vi v28, v28, 4 ; RV64-NEXT: vrgather.vv v26, v8, v28, v0.t ; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <4 x double> , <4 x double> %x, <4 x i32> ret <4 x double> %s @@ -215,6 +229,7 @@ ; RV32-NEXT: vlse64.v v26, (a0), zero ; RV32-NEXT: vrgatherei16.vv v26, v8, v25, v0.t ; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_vx_v4f64: @@ -231,6 +246,7 @@ ; RV64-NEXT: vlse64.v v26, (a0), zero ; RV64-NEXT: vrgather.vv v26, v8, v28, v0.t ; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <4 x double> %x, <4 x double> , <4 x i32> ret <4 x double> %s diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll @@ -10,6 +10,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <8 x half> undef, half %y, i32 0 %b = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> zeroinitializer @@ -23,6 +24,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <4 x float> undef, float %y, i32 0 %b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer @@ -36,6 +38,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <2 x double> undef, double %y, i32 0 %b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer @@ -49,6 +52,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-NEXT: vfmv.v.f v26, fa0 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_16f16: @@ -58,6 +62,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse16.v v25, (a1) ; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <16 x half> undef, half %y, i32 0 %b = shufflevector <16 x half> %a, <16 x half> undef, <16 x i32> zeroinitializer @@ -71,6 +76,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vfmv.v.f v26, fa0 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v8f32: @@ -80,6 +86,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse32.v v25, (a1) ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <8 x float> undef, float %y, i32 0 %b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer @@ -93,6 +100,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-NEXT: vfmv.v.f v26, fa0 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v4f64: @@ -102,6 +110,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse64.v v25, (a1) ; LMULMAX1-NEXT: vse64.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <4 x double> undef, double %y, i32 0 %b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer @@ -115,6 +124,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <8 x half> undef, half 0.0, i32 0 %b = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> zeroinitializer @@ -128,6 +138,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <4 x float> undef, float 0.0, i32 0 %b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer @@ -141,6 +152,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <2 x double> undef, double 0.0, i32 0 %b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer @@ -154,6 +166,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_16f16: @@ -163,6 +176,7 @@ ; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <16 x half> undef, half 0.0, i32 0 %b = shufflevector <16 x half> %a, <16 x half> undef, <16 x i32> zeroinitializer @@ -176,6 +190,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v8f32: @@ -185,6 +200,7 @@ ; LMULMAX1-NEXT: vse32.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <8 x float> undef, float 0.0, i32 0 %b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer @@ -198,6 +214,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v4f64: @@ -207,6 +224,7 @@ ; LMULMAX1-NEXT: vse64.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse64.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <4 x double> undef, double 0.0, i32 0 %b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll @@ -11,6 +11,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vlse16.v v25, (a1), zero ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = extractelement <8 x half> %a, i32 5 @@ -27,6 +28,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vlse32.v v25, (a1), zero ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = extractelement <4 x float> %a, i32 2 @@ -42,6 +44,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = extractelement <2 x double> %a, i32 0 @@ -59,6 +62,7 @@ ; LMULMAX8-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; LMULMAX8-NEXT: vlse16.v v8, (a1), zero ; LMULMAX8-NEXT: vse16.v v8, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v64f16: @@ -81,6 +85,7 @@ ; LMULMAX1-NEXT: vse16.v v25, (a7) ; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: vse16.v v25, (a6) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = extractelement <64 x half> %a, i32 47 @@ -98,6 +103,7 @@ ; LMULMAX8-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; LMULMAX8-NEXT: vlse32.v v8, (a1), zero ; LMULMAX8-NEXT: vse32.v v8, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v32f32: @@ -120,6 +126,7 @@ ; LMULMAX1-NEXT: vse32.v v25, (a7) ; LMULMAX1-NEXT: vse32.v v25, (a0) ; LMULMAX1-NEXT: vse32.v v25, (a6) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = extractelement <32 x float> %a, i32 17 @@ -136,6 +143,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; LMULMAX8-NEXT: vlse64.v v8, (a1), zero ; LMULMAX8-NEXT: vse64.v v8, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v16f64: @@ -157,6 +165,7 @@ ; LMULMAX1-NEXT: vse64.v v25, (a7) ; LMULMAX1-NEXT: vse64.v v25, (a0) ; LMULMAX1-NEXT: vse64.v v25, (a6) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = extractelement <16 x double> %a, i32 10 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll @@ -12,6 +12,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfadd.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -28,6 +29,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfadd.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -44,6 +46,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfadd.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -60,6 +63,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfsub.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -76,6 +80,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfsub.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -92,6 +97,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfsub.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -108,6 +114,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfmul.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -124,6 +131,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfmul.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -140,6 +148,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfmul.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -156,6 +165,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfdiv.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -172,6 +182,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfdiv.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -188,6 +199,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfdiv.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -203,6 +215,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfsgnjn.vv v25, v25, v25 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = fneg <8 x half> %a @@ -217,6 +230,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfsgnjn.vv v25, v25, v25 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = fneg <4 x float> %a @@ -231,6 +245,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfsgnjn.vv v25, v25, v25 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = fneg <2 x double> %a @@ -245,6 +260,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfsgnjx.vv v25, v25, v25 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = call <8 x half> @llvm.fabs.v8f16(<8 x half> %a) @@ -260,6 +276,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfsgnjx.vv v25, v25, v25 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) @@ -275,6 +292,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfsgnjx.vv v25, v25, v25 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = call <2 x double> @llvm.fabs.v2f64(<2 x double> %a) @@ -291,6 +309,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfsgnj.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -308,6 +327,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfsgnj.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -325,6 +345,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfsgnj.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -341,6 +362,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfsgnj.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -357,6 +379,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfsgnj.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -373,6 +396,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfsgnj.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -390,6 +414,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfsgnjn.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -407,6 +432,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfsgnjn.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -424,6 +450,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfsgnjn.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -442,6 +469,7 @@ ; CHECK-NEXT: vfncvt.f.f.w v27, v25 ; CHECK-NEXT: vfsgnjn.vv v25, v26, v27 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x half>, <4 x half>* %x %b = load <4 x float>, <4 x float>* %y @@ -464,6 +492,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnjn.vv v25, v26, v27 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x float>, <2 x float>* %y @@ -481,6 +510,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfsqrt.v v25, v25 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a) @@ -496,6 +526,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfsqrt.v v25, v25 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) @@ -511,6 +542,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfsqrt.v v25, v25 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a) @@ -528,6 +560,7 @@ ; CHECK-NEXT: vle16.v v27, (a2) ; CHECK-NEXT: vfmacc.vv v27, v25, v26 ; CHECK-NEXT: vse16.v v27, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -547,6 +580,7 @@ ; CHECK-NEXT: vle32.v v27, (a2) ; CHECK-NEXT: vfmacc.vv v27, v25, v26 ; CHECK-NEXT: vse32.v v27, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -566,6 +600,7 @@ ; CHECK-NEXT: vle64.v v27, (a2) ; CHECK-NEXT: vfmacc.vv v27, v25, v26 ; CHECK-NEXT: vse64.v v27, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -585,6 +620,7 @@ ; CHECK-NEXT: vle16.v v27, (a2) ; CHECK-NEXT: vfmsac.vv v27, v25, v26 ; CHECK-NEXT: vse16.v v27, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -604,6 +640,7 @@ ; CHECK-NEXT: vle32.v v27, (a2) ; CHECK-NEXT: vfnmsac.vv v27, v25, v26 ; CHECK-NEXT: vse32.v v27, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -623,6 +660,7 @@ ; CHECK-NEXT: vle64.v v27, (a2) ; CHECK-NEXT: vfnmacc.vv v27, v25, v26 ; CHECK-NEXT: vse64.v v27, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -642,6 +680,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vfadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fadd_v16f16: @@ -657,6 +696,7 @@ ; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fadd_v16f16: @@ -672,6 +712,7 @@ ; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -688,6 +729,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vfadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fadd_v8f32: @@ -703,6 +745,7 @@ ; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fadd_v8f32: @@ -718,6 +761,7 @@ ; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -734,6 +778,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vfadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fadd_v4f64: @@ -749,6 +794,7 @@ ; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fadd_v4f64: @@ -764,6 +810,7 @@ ; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -780,6 +827,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vfsub.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fsub_v16f16: @@ -795,6 +843,7 @@ ; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fsub_v16f16: @@ -810,6 +859,7 @@ ; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -826,6 +876,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vfsub.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fsub_v8f32: @@ -841,6 +892,7 @@ ; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fsub_v8f32: @@ -856,6 +908,7 @@ ; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -872,6 +925,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vfsub.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fsub_v4f64: @@ -887,6 +941,7 @@ ; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fsub_v4f64: @@ -902,6 +957,7 @@ ; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -918,6 +974,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vfmul.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fmul_v16f16: @@ -933,6 +990,7 @@ ; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fmul_v16f16: @@ -948,6 +1006,7 @@ ; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -964,6 +1023,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vfmul.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fmul_v8f32: @@ -979,6 +1039,7 @@ ; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fmul_v8f32: @@ -994,6 +1055,7 @@ ; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -1010,6 +1072,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vfmul.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fmul_v4f64: @@ -1025,6 +1088,7 @@ ; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fmul_v4f64: @@ -1040,6 +1104,7 @@ ; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -1056,6 +1121,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fdiv_v16f16: @@ -1071,6 +1137,7 @@ ; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fdiv_v16f16: @@ -1086,6 +1153,7 @@ ; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -1102,6 +1170,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fdiv_v8f32: @@ -1117,6 +1186,7 @@ ; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fdiv_v8f32: @@ -1132,6 +1202,7 @@ ; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -1148,6 +1219,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fdiv_v4f64: @@ -1163,6 +1235,7 @@ ; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fdiv_v4f64: @@ -1178,6 +1251,7 @@ ; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -1193,6 +1267,7 @@ ; LMULMAX2-NEXT: vle16.v v26, (a0) ; LMULMAX2-NEXT: vfsgnjn.vv v26, v26, v26 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fneg_v16f16: @@ -1205,6 +1280,7 @@ ; LMULMAX1-NEXT: vfsgnjn.vv v26, v26, v26 ; LMULMAX1-NEXT: vse16.v v26, (a0) ; LMULMAX1-NEXT: vse16.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = fneg <16 x half> %a @@ -1219,6 +1295,7 @@ ; LMULMAX2-NEXT: vle32.v v26, (a0) ; LMULMAX2-NEXT: vfsgnjn.vv v26, v26, v26 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fneg_v8f32: @@ -1231,6 +1308,7 @@ ; LMULMAX1-NEXT: vfsgnjn.vv v26, v26, v26 ; LMULMAX1-NEXT: vse32.v v26, (a0) ; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = fneg <8 x float> %a @@ -1245,6 +1323,7 @@ ; LMULMAX2-NEXT: vle64.v v26, (a0) ; LMULMAX2-NEXT: vfsgnjn.vv v26, v26, v26 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fneg_v4f64: @@ -1257,6 +1336,7 @@ ; LMULMAX1-NEXT: vfsgnjn.vv v26, v26, v26 ; LMULMAX1-NEXT: vse64.v v26, (a0) ; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = fneg <4 x double> %a @@ -1273,6 +1353,7 @@ ; LMULMAX2-NEXT: vle16.v v30, (a2) ; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28 ; LMULMAX2-NEXT: vse16.v v30, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fma_v16f16: @@ -1291,6 +1372,7 @@ ; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27 ; LMULMAX1-NEXT: vse16.v v30, (a0) ; LMULMAX1-NEXT: vse16.v v29, (a3) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -1310,6 +1392,7 @@ ; LMULMAX2-NEXT: vle32.v v30, (a2) ; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28 ; LMULMAX2-NEXT: vse32.v v30, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fma_v8f32: @@ -1328,6 +1411,7 @@ ; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27 ; LMULMAX1-NEXT: vse32.v v30, (a0) ; LMULMAX1-NEXT: vse32.v v29, (a3) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -1347,6 +1431,7 @@ ; LMULMAX2-NEXT: vle64.v v30, (a2) ; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28 ; LMULMAX2-NEXT: vse64.v v30, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fma_v4f64: @@ -1365,6 +1450,7 @@ ; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27 ; LMULMAX1-NEXT: vse64.v v30, (a0) ; LMULMAX1-NEXT: vse64.v v29, (a3) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -1382,6 +1468,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfadd.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1398,6 +1485,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfadd.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1414,6 +1502,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfadd.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1430,6 +1519,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfadd.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1446,6 +1536,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfadd.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1462,6 +1553,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfadd.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1478,6 +1570,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfsub.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1494,6 +1587,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfsub.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1510,6 +1604,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfsub.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1526,6 +1621,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfrsub.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1542,6 +1638,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfrsub.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1558,6 +1655,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfrsub.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1574,6 +1672,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfmul.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1590,6 +1689,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfmul.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1606,6 +1706,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfmul.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1622,6 +1723,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfmul.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1638,6 +1740,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfmul.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1654,6 +1757,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfmul.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1670,6 +1774,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfdiv.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1686,6 +1791,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfdiv.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1702,6 +1808,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfdiv.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1718,6 +1825,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfrdiv.vf v25, v25, fa0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1734,6 +1842,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfrdiv.vf v25, v25, fa0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1750,6 +1859,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfrdiv.vf v25, v25, fa0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1767,6 +1877,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfmacc.vf v26, fa0, v25 ; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -1785,6 +1896,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfmacc.vf v26, fa0, v25 ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -1803,6 +1915,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfmacc.vf v26, fa0, v25 ; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -1821,6 +1934,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfmacc.vf v26, fa0, v25 ; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -1839,6 +1953,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfmacc.vf v26, fa0, v25 ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -1857,6 +1972,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfmacc.vf v26, fa0, v25 ; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -1875,6 +1991,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vfmsac.vf v26, fa0, v25 ; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -1894,6 +2011,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfnmsac.vf v26, fa0, v25 ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -1913,6 +2031,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfnmacc.vf v26, fa0, v25 ; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -1933,6 +2052,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vfnmsac.vf v26, fa0, v25 ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -1952,6 +2072,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vfnmacc.vf v26, fa0, v25 ; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -11,6 +11,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfcvt.rtz.x.f.v v25, v25 ; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptosi <2 x float> %a to <2 x i32> @@ -25,6 +26,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfcvt.rtz.xu.f.v v25, v25 ; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptoui <2 x float> %a to <2 x i32> @@ -39,6 +41,7 @@ ; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = fptosi <2 x float> %x to <2 x i1> ret <2 x i1> %z @@ -51,6 +54,7 @@ ; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = fptoui <2 x float> %x to <2 x i1> ret <2 x i1> %z @@ -63,6 +67,7 @@ ; LMULMAX8-NEXT: vle32.v v26, (a0) ; LMULMAX8-NEXT: vfcvt.rtz.x.f.v v26, v26 ; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f32_v8i32: @@ -76,6 +81,7 @@ ; LMULMAX1-NEXT: vse32.v v26, (a1) ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptosi <8 x float> %a to <8 x i32> @@ -90,6 +96,7 @@ ; LMULMAX8-NEXT: vle32.v v26, (a0) ; LMULMAX8-NEXT: vfcvt.rtz.xu.f.v v26, v26 ; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f32_v8i32: @@ -103,6 +110,7 @@ ; LMULMAX1-NEXT: vse32.v v26, (a1) ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptoui <8 x float> %a to <8 x i32> @@ -117,6 +125,7 @@ ; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v25, v8 ; LMULMAX8-NEXT: vand.vi v25, v25, 1 ; LMULMAX8-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f32_v8i1: @@ -147,6 +156,7 @@ ; LMULMAX1-NEXT: vslideup.vi v25, v26, 4 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %z = fptosi <8 x float> %x to <8 x i1> ret <8 x i1> %z @@ -159,6 +169,7 @@ ; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v25, v8 ; LMULMAX8-NEXT: vand.vi v25, v25, 1 ; LMULMAX8-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f32_v8i1: @@ -189,6 +200,7 @@ ; LMULMAX1-NEXT: vslideup.vi v25, v26, 4 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %z = fptoui <8 x float> %x to <8 x i1> ret <8 x i1> %z @@ -201,6 +213,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v25 ; CHECK-NEXT: vse64.v v26, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptosi <2 x float> %a to <2 x i64> @@ -215,6 +228,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v25 ; CHECK-NEXT: vse64.v v26, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptoui <2 x float> %a to <2 x i64> @@ -229,6 +243,7 @@ ; LMULMAX8-NEXT: vle32.v v26, (a0) ; LMULMAX8-NEXT: vfwcvt.rtz.x.f.v v28, v26 ; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f32_v8i64: @@ -254,6 +269,7 @@ ; LMULMAX1-NEXT: vse64.v v28, (a0) ; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: vse64.v v27, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptosi <8 x float> %a to <8 x i64> @@ -268,6 +284,7 @@ ; LMULMAX8-NEXT: vle32.v v26, (a0) ; LMULMAX8-NEXT: vfwcvt.rtz.xu.f.v v28, v26 ; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f32_v8i64: @@ -293,6 +310,7 @@ ; LMULMAX1-NEXT: vse64.v v28, (a0) ; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: vse64.v v27, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptoui <8 x float> %a to <8 x i64> @@ -309,6 +327,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v26 ; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %d = fptosi <2 x half> %a to <2 x i64> @@ -325,6 +344,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v26 ; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %d = fptoui <2 x half> %a to <2 x i64> @@ -339,6 +359,7 @@ ; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = fptosi <2 x half> %x to <2 x i1> ret <2 x i1> %z @@ -351,6 +372,7 @@ ; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = fptoui <2 x half> %x to <2 x i1> ret <2 x i1> %z @@ -368,6 +390,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %d = fptosi <2 x double> %a to <2 x i8> @@ -387,6 +410,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %d = fptoui <2 x double> %a to <2 x i8> @@ -401,6 +425,7 @@ ; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = fptosi <2 x double> %x to <2 x i1> ret <2 x i1> %z @@ -413,6 +438,7 @@ ; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = fptoui <2 x double> %x to <2 x i1> ret <2 x i1> %z @@ -430,6 +456,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0 ; LMULMAX8-NEXT: vse8.v v25, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f64_v8i8: @@ -477,6 +504,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 ; LMULMAX1-NEXT: vse8.v v29, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x double>, <8 x double>* %x %d = fptosi <8 x double> %a to <8 x i8> @@ -496,6 +524,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0 ; LMULMAX8-NEXT: vse8.v v25, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f64_v8i8: @@ -543,6 +572,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 ; LMULMAX1-NEXT: vse8.v v29, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x double>, <8 x double>* %x %d = fptoui <8 x double> %a to <8 x i8> @@ -557,6 +587,7 @@ ; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v26, v8 ; LMULMAX8-NEXT: vand.vi v26, v26, 1 ; LMULMAX8-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f64_v8i1: @@ -609,6 +640,7 @@ ; LMULMAX1-NEXT: vslideup.vi v25, v26, 6 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %z = fptosi <8 x double> %x to <8 x i1> ret <8 x i1> %z @@ -621,6 +653,7 @@ ; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v26, v8 ; LMULMAX8-NEXT: vand.vi v26, v26, 1 ; LMULMAX8-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f64_v8i1: @@ -673,6 +706,7 @@ ; LMULMAX1-NEXT: vslideup.vi v25, v26, 6 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %z = fptoui <8 x double> %x to <8 x i1> ret <8 x i1> %z diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll @@ -11,6 +11,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfcvt.f.x.v v25, v25 ; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %d = sitofp <2 x i32> %a to <2 x float> @@ -25,6 +26,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfcvt.f.xu.v v25, v25 ; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %d = uitofp <2 x i32> %a to <2 x float> @@ -39,6 +41,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 ; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = sitofp <2 x i1> %x to <2 x float> ret <2 x float> %z @@ -51,6 +54,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = uitofp <2 x i1> %x to <2 x float> ret <2 x float> %z @@ -63,6 +67,7 @@ ; LMULMAX8-NEXT: vle32.v v26, (a0) ; LMULMAX8-NEXT: vfcvt.f.x.v v26, v26 ; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i32_v8f32: @@ -76,6 +81,7 @@ ; LMULMAX1-NEXT: vse32.v v26, (a1) ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %d = sitofp <8 x i32> %a to <8 x float> @@ -90,6 +96,7 @@ ; LMULMAX8-NEXT: vle32.v v26, (a0) ; LMULMAX8-NEXT: vfcvt.f.xu.v v26, v26 ; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i32_v8f32: @@ -103,6 +110,7 @@ ; LMULMAX1-NEXT: vse32.v v26, (a1) ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %d = uitofp <8 x i32> %a to <8 x float> @@ -117,6 +125,7 @@ ; LMULMAX8-NEXT: vmv.v.i v26, 0 ; LMULMAX8-NEXT: vmerge.vim v26, v26, -1, v0 ; LMULMAX8-NEXT: vfcvt.f.x.v v8, v26 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i1_v8f32: @@ -135,6 +144,7 @@ ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; LMULMAX1-NEXT: vmerge.vim v25, v25, -1, v0 ; LMULMAX1-NEXT: vfcvt.f.x.v v9, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %z = sitofp <8 x i1> %x to <8 x float> ret <8 x float> %z @@ -147,6 +157,7 @@ ; LMULMAX8-NEXT: vmv.v.i v26, 0 ; LMULMAX8-NEXT: vmerge.vim v26, v26, 1, v0 ; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v26 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i1_v8f32: @@ -165,6 +176,7 @@ ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 ; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %z = uitofp <8 x i1> %x to <8 x float> ret <8 x float> %z @@ -179,6 +191,7 @@ ; CHECK-NEXT: vsext.vf4 v26, v25 ; CHECK-NEXT: vfcvt.f.x.v v25, v26 ; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %d = sitofp <2 x i16> %a to <2 x double> @@ -195,6 +208,7 @@ ; CHECK-NEXT: vzext.vf4 v26, v25 ; CHECK-NEXT: vfcvt.f.xu.v v25, v26 ; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %d = uitofp <2 x i16> %a to <2 x double> @@ -211,6 +225,7 @@ ; LMULMAX8-NEXT: vsext.vf4 v28, v25 ; LMULMAX8-NEXT: vfcvt.f.x.v v28, v28 ; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i16_v8f64: @@ -240,6 +255,7 @@ ; LMULMAX1-NEXT: vse64.v v28, (a0) ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse64.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %d = sitofp <8 x i16> %a to <8 x double> @@ -256,6 +272,7 @@ ; LMULMAX8-NEXT: vzext.vf4 v28, v25 ; LMULMAX8-NEXT: vfcvt.f.xu.v v28, v28 ; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i16_v8f64: @@ -285,6 +302,7 @@ ; LMULMAX1-NEXT: vse64.v v28, (a0) ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse64.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %d = uitofp <8 x i16> %a to <8 x double> @@ -299,6 +317,7 @@ ; LMULMAX8-NEXT: vmv.v.i v28, 0 ; LMULMAX8-NEXT: vmerge.vim v28, v28, -1, v0 ; LMULMAX8-NEXT: vfcvt.f.x.v v8, v28 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i1_v8f64: @@ -338,6 +357,7 @@ ; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; LMULMAX1-NEXT: vmerge.vim v25, v26, -1, v0 ; LMULMAX1-NEXT: vfcvt.f.x.v v11, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %z = sitofp <8 x i1> %x to <8 x double> ret <8 x double> %z @@ -350,6 +370,7 @@ ; LMULMAX8-NEXT: vmv.v.i v28, 0 ; LMULMAX8-NEXT: vmerge.vim v28, v28, 1, v0 ; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v28 +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i1_v8f64: @@ -389,6 +410,7 @@ ; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; LMULMAX1-NEXT: vmerge.vim v25, v26, 1, v0 ; LMULMAX1-NEXT: vfcvt.f.xu.v v11, v25 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %z = uitofp <8 x i1> %x to <8 x double> ret <8 x double> %z @@ -404,6 +426,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v26 ; CHECK-NEXT: vse16.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %d = sitofp <2 x i64> %a to <2 x half> @@ -421,6 +444,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v25, v26 ; CHECK-NEXT: vse16.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %d = uitofp <2 x i64> %a to <2 x half> @@ -435,6 +459,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 ; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = sitofp <2 x i1> %x to <2 x half> ret <2 x half> %z @@ -447,6 +472,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = uitofp <2 x i1> %x to <2 x half> ret <2 x half> %z @@ -462,6 +488,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX8-NEXT: vse16.v v25, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i64_v8f16: @@ -501,6 +528,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 ; LMULMAX1-NEXT: vse16.v v29, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %d = sitofp <8 x i64> %a to <8 x half> @@ -518,6 +546,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 ; LMULMAX8-NEXT: vse16.v v25, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i64_v8f16: @@ -557,6 +586,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 ; LMULMAX1-NEXT: vse16.v v29, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %d = uitofp <8 x i64> %a to <8 x half> @@ -571,6 +601,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 ; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = sitofp <8 x i1> %x to <8 x half> ret <8 x half> %z @@ -583,6 +614,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %z = uitofp <8 x i1> %x to <8 x half> ret <8 x half> %z diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll @@ -11,6 +11,7 @@ ; CHECK-NEXT: vle32.v v28, (a0) ; CHECK-NEXT: vsetivli zero, 2, e32, m4, tu, mu ; CHECK-NEXT: vslideup.vi v8, v28, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call @llvm.experimental.vector.insert.v2i32.nxv8i32( %vec, <2 x i32> %sv, i64 0) @@ -24,6 +25,7 @@ ; CHECK-NEXT: vle32.v v28, (a0) ; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; CHECK-NEXT: vslideup.vi v8, v28, 2 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call @llvm.experimental.vector.insert.v2i32.nxv8i32( %vec, <2 x i32> %sv, i64 2) @@ -37,6 +39,7 @@ ; CHECK-NEXT: vle32.v v28, (a0) ; CHECK-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; CHECK-NEXT: vslideup.vi v8, v28, 6 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call @llvm.experimental.vector.insert.v2i32.nxv8i32( %vec, <2 x i32> %sv, i64 6) @@ -50,6 +53,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a0) ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; LMULMAX2-NEXT: vslideup.vi v8, v28, 0 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0: @@ -62,6 +66,7 @@ ; LMULMAX1-NEXT: vslideup.vi v8, v28, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; LMULMAX1-NEXT: vslideup.vi v8, v12, 4 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %sv = load <8 x i32>, <8 x i32>* %svp %v = call @llvm.experimental.vector.insert.v8i32.nxv8i32( %vec, <8 x i32> %sv, i64 0) @@ -75,6 +80,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a0) ; LMULMAX2-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX2-NEXT: vslideup.vi v8, v28, 8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_8: @@ -87,6 +93,7 @@ ; LMULMAX1-NEXT: vslideup.vi v8, v28, 8 ; LMULMAX1-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX1-NEXT: vslideup.vi v8, v12, 12 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %sv = load <8 x i32>, <8 x i32>* %svp %v = call @llvm.experimental.vector.insert.v8i32.nxv8i32( %vec, <8 x i32> %sv, i64 8) @@ -98,6 +105,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call @llvm.experimental.vector.insert.v2i32.nxv8i32( undef, <2 x i32> %sv, i64 0) @@ -115,6 +123,7 @@ ; CHECK-NEXT: vslideup.vi v26, v25, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <4 x i32>, <4 x i32>* %vp @@ -133,6 +142,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; CHECK-NEXT: vslideup.vi v26, v25, 2 ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <4 x i32>, <4 x i32>* %vp @@ -152,6 +162,7 @@ ; CHECK-NEXT: vslideup.vi v26, v25, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0) @@ -170,6 +181,7 @@ ; LMULMAX2-NEXT: vslideup.vi v28, v26, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v8i32_v2i32_0: @@ -182,6 +194,7 @@ ; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <8 x i32>, <8 x i32>* %vp @@ -201,6 +214,7 @@ ; LMULMAX2-NEXT: vslideup.vi v28, v26, 2 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v8i32_v2i32_2: @@ -212,6 +226,7 @@ ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 ; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <8 x i32>, <8 x i32>* %vp @@ -230,6 +245,7 @@ ; LMULMAX2-NEXT: vsetvli zero, zero, e32, m2, tu, mu ; LMULMAX2-NEXT: vslideup.vi v28, v26, 6 ; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v8i32_v2i32_6: @@ -242,6 +258,7 @@ ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 ; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <8 x i32>, <8 x i32>* %vp @@ -258,6 +275,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vslideup.vi v28, v26, 6 ; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v8i32_undef_v2i32_6: @@ -268,6 +286,7 @@ ; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> undef, <2 x i32> %sv, i64 6) @@ -286,6 +305,7 @@ ; CHECK-NEXT: vslideup.vi v25, v26, 0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %vp %sv = load <2 x i16>, <2 x i16>* %svp @@ -304,6 +324,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; CHECK-NEXT: vslideup.vi v25, v26, 2 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %vp %sv = load <2 x i16>, <2 x i16>* %svp @@ -324,6 +345,7 @@ ; LMULMAX2-NEXT: vslideup.vi v25, v26, 0 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v32i1_v8i1_0: @@ -336,6 +358,7 @@ ; LMULMAX1-NEXT: vslideup.vi v25, v26, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsm.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %v = load <32 x i1>, <32 x i1>* %vp %sv = load <8 x i1>, <8 x i1>* %svp @@ -356,6 +379,7 @@ ; LMULMAX2-NEXT: vslideup.vi v25, v26, 2 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v32i1_v8i1_16: @@ -369,6 +393,7 @@ ; LMULMAX1-NEXT: vslideup.vi v25, v26, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsm.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %v = load <32 x i1>, <32 x i1>* %vp %sv = load <8 x i1>, <8 x i1>* %svp @@ -396,6 +421,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i1>, <8 x i1>* %vp %sv = load <4 x i1>, <4 x i1>* %svp @@ -423,6 +449,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i1>, <8 x i1>* %vp %sv = load <4 x i1>, <4 x i1>* %svp @@ -438,6 +465,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu ; CHECK-NEXT: vslideup.vi v8, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i16>, <2 x i16>* %svp %c = call @llvm.experimental.vector.insert.v2i16.nxv2i16( %v, <2 x i16> %sv, i64 0) @@ -451,6 +479,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsetivli zero, 6, e16, mf2, tu, mu ; CHECK-NEXT: vslideup.vi v8, v25, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i16>, <2 x i16>* %svp %c = call @llvm.experimental.vector.insert.v2i16.nxv2i16( %v, <2 x i16> %sv, i64 4) @@ -473,6 +502,7 @@ ; CHECK-NEXT: vslideup.vi v26, v25, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <4 x i1>, <4 x i1>* %svp %c = call @llvm.experimental.vector.insert.v4i1.nxv2i1( %v, <4 x i1> %sv, i64 0) @@ -486,6 +516,7 @@ ; CHECK-NEXT: vlm.v v25, (a0) ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, mu ; CHECK-NEXT: vslideup.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <8 x i1>, <8 x i1>* %svp %c = call @llvm.experimental.vector.insert.v8i1.nxv8i1( %v, <8 x i1> %sv, i64 0) @@ -499,6 +530,7 @@ ; CHECK-NEXT: vlm.v v25, (a0) ; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu ; CHECK-NEXT: vslideup.vi v0, v25, 2 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <8 x i1>, <8 x i1>* %svp %c = call @llvm.experimental.vector.insert.v8i1.nxv8i1( %v, <8 x i1> %sv, i64 16) @@ -516,6 +548,7 @@ ; CHECK-NEXT: vsetivli zero, 6, e64, m8, tu, mu ; CHECK-NEXT: vslideup.vi v8, v16, 4 ; CHECK-NEXT: vs8r.v v8, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv0 = load <2 x i64>, <2 x i64>* %psv0 %sv1 = load <2 x i64>, <2 x i64>* %psv1 @@ -531,6 +564,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i64>, <2 x i64>* %psv %v = call @llvm.experimental.vector.insert.v2i64.nxv16i64( undef, <2 x i64> %sv, i64 0) @@ -546,6 +580,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e64, m8, ta, mu ; CHECK-NEXT: vslideup.vi v16, v8, 2 ; CHECK-NEXT: vs8r.v v16, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i64>, <2 x i64>* %psv %v = call @llvm.experimental.vector.insert.v2i64.nxv16i64( undef, <2 x i64> %sv, i64 2) @@ -581,6 +616,7 @@ ; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %sv = load <2 x i64>, <2 x i64>* %psv %v = call @llvm.experimental.vector.insert.v2i64.nxv16i64( undef, <2 x i64> %sv, i64 8) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll @@ -17,6 +17,7 @@ ; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu ; RV32-NEXT: vslideup.vi v26, v28, 3 ; RV32-NEXT: vse64.v v26, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v4i64: @@ -27,6 +28,7 @@ ; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; RV64-NEXT: vslideup.vi v26, v28, 3 ; RV64-NEXT: vse64.v v26, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = insertelement <4 x i64> %a, i64 %y, i32 3 @@ -65,11 +67,13 @@ ; RV32-NEXT: sw a2, 20(a0) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vse64.v v28, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v3i64: ; RV64: # %bb.0: ; RV64-NEXT: sd a1, 16(a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <3 x i64>, <3 x i64>* %x, align 8 %b = insertelement <3 x i64> %a, i64 %y, i32 2 @@ -87,6 +91,7 @@ ; CHECK-NEXT: vslideup.vi v25, v26, 14 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> %a, i8 %y, i32 14 @@ -106,6 +111,7 @@ ; RV32-NEXT: vslideup.vx v28, v8, a2 ; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; RV32-NEXT: vse16.v v28, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v32i16: @@ -120,6 +126,7 @@ ; RV64-NEXT: vslideup.vx v28, v8, a1 ; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; RV64-NEXT: vse16.v v28, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = insertelement <32 x i16> %a, i16 %y, i32 %idx @@ -138,6 +145,7 @@ ; RV32-NEXT: vslideup.vx v26, v28, a1 ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vse32.v v26, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v8f32: @@ -151,6 +159,7 @@ ; RV64-NEXT: vslideup.vx v26, v28, a1 ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vse32.v v26, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> %a, float %y, i32 %idx @@ -167,6 +176,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vmv.s.x v28, a1 ; CHECK-NEXT: vse64.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 -1, i32 0 @@ -186,6 +196,7 @@ ; RV32-NEXT: vslideup.vx v28, v8, a1 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vse64.v v28, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v8i64: @@ -200,6 +211,7 @@ ; RV64-NEXT: vslideup.vx v28, v8, a1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vse64.v v28, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 -1, i32 %idx @@ -216,6 +228,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vmv.s.x v28, a1 ; CHECK-NEXT: vse64.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 6, i32 0 @@ -235,6 +248,7 @@ ; RV32-NEXT: vslideup.vx v28, v8, a1 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vse64.v v28, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_c6_v8i64: @@ -249,6 +263,7 @@ ; RV64-NEXT: vslideup.vx v28, v8, a1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vse64.v v28, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 6, i32 %idx @@ -270,6 +285,7 @@ ; CHECK-NEXT: vle64.v v8, (a1) ; CHECK-NEXT: vadd.vv v28, v28, v8 ; CHECK-NEXT: vse64.v v28, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 6, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -8,6 +8,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vid.v v25 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -19,6 +20,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vid.v v25 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -33,6 +35,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vle8.v v25, (a1) ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -45,6 +48,7 @@ ; CHECK-NEXT: vid.v v25 ; CHECK-NEXT: vadd.vi v25, v25, 2 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -58,6 +62,7 @@ ; CHECK-NEXT: addi a1, zero, 3 ; CHECK-NEXT: vmul.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -73,6 +78,7 @@ ; CHECK-NEXT: vse8.v v25, (a1) ; CHECK-NEXT: vse8.v v25, (a2) ; CHECK-NEXT: vse8.v v25, (a3) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 store <4 x i8> , <4 x i8>* %z1 @@ -92,6 +98,7 @@ ; CHECK-NEXT: vse8.v v25, (a1) ; CHECK-NEXT: vse8.v v25, (a2) ; CHECK-NEXT: vse8.v v25, (a3) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 store <4 x i8> , <4 x i8>* %z1 @@ -113,6 +120,7 @@ ; CHECK-NEXT: vse8.v v25, (a1) ; CHECK-NEXT: vse8.v v25, (a2) ; CHECK-NEXT: vse8.v v25, (a3) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret i8>* %z2, <4 x i8>* %z3) { store <4 x i8> , <4 x i8>* %z0 @@ -133,6 +141,7 @@ ; CHECK-NEXT: vse8.v v25, (a1) ; CHECK-NEXT: vse8.v v25, (a2) ; CHECK-NEXT: vse8.v v25, (a3) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 store <4 x i8> , <4 x i8>* %z1 @@ -149,6 +158,7 @@ ; CHECK-NEXT: vadd.vv v25, v25, v25 ; CHECK-NEXT: vrsub.vi v25, v25, 3 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 ret void @@ -163,6 +173,7 @@ ; CHECK-NEXT: addi a1, zero, -3 ; CHECK-NEXT: vmadd.vx v26, a1, v25 ; CHECK-NEXT: vse8.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 ret void @@ -180,6 +191,7 @@ ; CHECK-NEXT: vse32.v v26, (a1) ; CHECK-NEXT: vse32.v v26, (a2) ; CHECK-NEXT: vse32.v v26, (a3) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i32> , <4 x i32>* %z0 store <4 x i32> , <4 x i32>* %z1 @@ -202,6 +214,7 @@ ; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0) ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vle32.v v9, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_vid_step1_add0_v4i64: @@ -209,6 +222,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vid.v v8 ; RV64-NEXT: vadd.vi v9, v8, 2 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ret <4 x i64> } @@ -226,6 +240,7 @@ ; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0) ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vle32.v v9, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_vid_step2_add0_v4i64: @@ -234,6 +249,7 @@ ; RV64-NEXT: vid.v v25 ; RV64-NEXT: vadd.vv v8, v25, v25 ; RV64-NEXT: vadd.vi v9, v8, 4 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ret <4 x i64> } @@ -267,6 +283,7 @@ ; RV32-NEXT: vmv.v.i v25, -2 ; RV32-NEXT: vse8.v v25, (a4) ; RV32-NEXT: vse8.v v26, (a5) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_no_vid_v4i8: @@ -297,6 +314,7 @@ ; RV64-NEXT: vmv.v.i v25, -2 ; RV64-NEXT: vse8.v v25, (a4) ; RV64-NEXT: vse8.v v26, (a5) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <4 x i8> , <4 x i8>* %z0 store <4 x i8> , <4 x i8>* %z1 @@ -317,6 +335,7 @@ ; CHECK-NEXT: vslideup.vi v26, v25, 3 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <8 x i16> , <8 x i16>* %x ret void @@ -328,6 +347,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, 8 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <8 x i16> , <8 x i16>* %x ret void @@ -336,6 +356,7 @@ define void @buildvec_dominant0_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: buildvec_dominant0_v2i8: ; CHECK: # %bb.0: +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <2 x i8> , <2 x i8>* %x ret void @@ -347,6 +368,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vmv.v.i v25, -1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <2 x i8> , <2 x i8>* %x ret void @@ -359,6 +381,7 @@ ; CHECK-NEXT: vid.v v25 ; CHECK-NEXT: vrsub.vi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <2 x i8> , <2 x i8>* %x ret void @@ -372,6 +395,7 @@ ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vle32.v v25, (a1) ; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_dominant0_v2i32: @@ -389,6 +413,7 @@ ; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV64-NEXT: vmv.s.x v25, a1 ; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <2 x i64> , <2 x i64>* %x ret void @@ -402,6 +427,7 @@ ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vle32.v v25, (a1) ; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_dominant1_optsize_v2i32: @@ -411,6 +437,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a1) ; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <2 x i64> , <2 x i64>* %x ret void @@ -424,6 +451,7 @@ ; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <8 x i8> , <8 x i8>* %x ret void @@ -438,6 +466,7 @@ ; RV32-NEXT: vmv.v.x v25, a1 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_seq_v8i8_v2i32: @@ -448,6 +477,7 @@ ; RV64-NEXT: vmv.v.x v25, a1 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <8 x i8> , <8 x i8>* %x ret void @@ -461,6 +491,7 @@ ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vle8.v v25, (a1) ; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_seq_v16i8_v2i64: @@ -475,6 +506,7 @@ ; RV64-NEXT: vmv.v.x v25, a1 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -489,6 +521,7 @@ ; RV32-NEXT: vmv.v.x v25, a1 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_seq2_v16i8_v2i64: @@ -499,6 +532,7 @@ ; RV64-NEXT: vmv.v.x v25, a1 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -521,6 +555,7 @@ ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vmerge.vim v25, v25, 3, v0 ; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_seq_v9i8: @@ -534,6 +569,7 @@ ; RV64-NEXT: slli a1, a1, 16 ; RV64-NEXT: addi a1, a1, 513 ; RV64-NEXT: sd a1, 0(a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <9 x i8> , <9 x i8>* %x ret void @@ -547,6 +583,7 @@ ; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i16> , <4 x i16>* %x ret void @@ -575,6 +612,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; CHECK-NEXT: vslideup.vi v26, v25, 3 ; CHECK-NEXT: vse32.v v26, (a6) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i32> , <4 x i32>* %z0 store <4 x i32> , <4 x i32>* %z1 @@ -613,6 +651,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, mu ; CHECK-NEXT: vslideup.vi v26, v25, 3 ; CHECK-NEXT: vse16.v v26, (a6) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i16> , <4 x i16>* %z0 store <4 x i16> , <4 x i16>* %z1 @@ -634,6 +673,7 @@ ; CHECK-NEXT: vsrl.vi v25, v25, 2 ; CHECK-NEXT: vrsub.vi v25, v25, -5 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <8 x i8> , <8 x i8>* %z0 ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll @@ -14,6 +14,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsext.vf4 v26, v25 ; CHECK-NEXT: vse32.v v26, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = sext <4 x i8> %a to <4 x i32> @@ -29,6 +30,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vzext.vf4 v26, v25 ; CHECK-NEXT: vse32.v v26, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = zext <4 x i8> %a to <4 x i32> @@ -44,6 +46,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX8-NEXT: vsext.vf4 v26, v25 ; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: sext_v8i8_v8i32: @@ -53,6 +56,7 @@ ; LMULMAX2-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX2-NEXT: vsext.vf4 v26, v25 ; LMULMAX2-NEXT: vse32.v v26, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: sext_v8i8_v8i32: @@ -67,6 +71,7 @@ ; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: vse32.v v27, (a0) ; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = sext <8 x i8> %a to <8 x i32> @@ -83,6 +88,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; LMULMAX8-NEXT: vsext.vf4 v8, v26 ; LMULMAX8-NEXT: vse32.v v8, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: sext_v32i8_v32i32: @@ -109,6 +115,7 @@ ; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: addi a0, a1, 32 ; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: sext_v32i8_v32i32: @@ -156,6 +163,7 @@ ; LMULMAX1-NEXT: vse32.v v30, (a0) ; LMULMAX1-NEXT: addi a0, a1, 80 ; LMULMAX1-NEXT: vse32.v v28, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = sext <32 x i8> %a to <32 x i32> @@ -173,6 +181,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vnsrl.wi v25, v25, 0 ; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = trunc <4 x i32> %a to <4 x i8> @@ -190,6 +199,7 @@ ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0 ; LMULMAX8-NEXT: vse8.v v25, (a1) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: trunc_v8i8_v8i32: @@ -201,6 +211,7 @@ ; LMULMAX2-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX2-NEXT: vnsrl.wi v25, v25, 0 ; LMULMAX2-NEXT: vse8.v v25, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: trunc_v8i8_v8i32: @@ -224,6 +235,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vslideup.vi v27, v25, 4 ; LMULMAX1-NEXT: vse8.v v27, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = trunc <8 x i32> %a to <8 x i8> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll @@ -16,6 +16,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -36,6 +37,7 @@ ; CHECK-NEXT: vmv.v.i v26, 0 ; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 ; CHECK-NEXT: vse8.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -54,6 +56,7 @@ ; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vmslt.vv v25, v8, v28 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = load <64 x i8>, <64 x i8>* %y @@ -71,6 +74,7 @@ ; CHECK-NEXT: vle8.v v16, (a1) ; CHECK-NEXT: vmslt.vv v25, v8, v16 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = load <128 x i8>, <128 x i8>* %y @@ -87,6 +91,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vmsle.vv v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load <8 x i8>, <8 x i8>* %y @@ -103,6 +108,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vmsle.vv v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -120,6 +126,7 @@ ; CHECK-NEXT: vle8.v v28, (a1) ; CHECK-NEXT: vmsltu.vv v25, v28, v26 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -137,6 +144,7 @@ ; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vmsltu.vv v25, v28, v8 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = load <64 x i8>, <64 x i8>* %y @@ -154,6 +162,7 @@ ; CHECK-NEXT: vle8.v v16, (a1) ; CHECK-NEXT: vmsleu.vv v25, v16, v8 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = load <128 x i8>, <128 x i8>* %y @@ -170,6 +179,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vmsleu.vv v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load <8 x i8>, <8 x i8>* %y @@ -185,6 +195,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmseq.vx v25, v25, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -202,6 +213,7 @@ ; CHECK-NEXT: vle8.v v26, (a0) ; CHECK-NEXT: vmsne.vx v25, v26, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -219,6 +231,7 @@ ; CHECK-NEXT: vle8.v v28, (a0) ; CHECK-NEXT: vmsgt.vx v25, v28, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -236,6 +249,7 @@ ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vmslt.vx v25, v8, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 %y, i32 0 @@ -253,6 +267,7 @@ ; CHECK-NEXT: vmv.v.x v26, a1 ; CHECK-NEXT: vmsle.vv v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -269,6 +284,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmsle.vx v25, v25, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -286,6 +302,7 @@ ; CHECK-NEXT: vle8.v v26, (a0) ; CHECK-NEXT: vmsgtu.vx v25, v26, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -303,6 +320,7 @@ ; CHECK-NEXT: vle8.v v28, (a0) ; CHECK-NEXT: vmsltu.vx v25, v28, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -321,6 +339,7 @@ ; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: vmsleu.vv v25, v16, v8 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 %y, i32 0 @@ -337,6 +356,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmsleu.vx v25, v25, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -353,6 +373,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmseq.vx v25, v25, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -370,6 +391,7 @@ ; CHECK-NEXT: vle8.v v26, (a0) ; CHECK-NEXT: vmsne.vx v25, v26, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -387,6 +409,7 @@ ; CHECK-NEXT: vle8.v v28, (a0) ; CHECK-NEXT: vmslt.vx v25, v28, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -404,6 +427,7 @@ ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vmsgt.vx v25, v8, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 %y, i32 0 @@ -420,6 +444,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmsle.vx v25, v25, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -437,6 +462,7 @@ ; CHECK-NEXT: vmv.v.x v26, a1 ; CHECK-NEXT: vmsle.vv v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -454,6 +480,7 @@ ; CHECK-NEXT: vle8.v v26, (a0) ; CHECK-NEXT: vmsltu.vx v25, v26, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -471,6 +498,7 @@ ; CHECK-NEXT: vle8.v v28, (a0) ; CHECK-NEXT: vmsgtu.vx v25, v28, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -488,6 +516,7 @@ ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vmsleu.vx v25, v8, a1 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 %y, i32 0 @@ -505,6 +534,7 @@ ; CHECK-NEXT: vmv.v.x v26, a1 ; CHECK-NEXT: vmsleu.vv v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -521,6 +551,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmseq.vi v25, v25, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 0, i32 0 @@ -538,6 +569,7 @@ ; CHECK-NEXT: vle8.v v26, (a0) ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 0, i32 0 @@ -555,6 +587,7 @@ ; CHECK-NEXT: vle8.v v28, (a0) ; CHECK-NEXT: vmsgt.vx v25, v28, zero ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 0, i32 0 @@ -572,6 +605,7 @@ ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vmsle.vi v25, v8, -1 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 0, i32 0 @@ -588,6 +622,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmsgt.vi v25, v25, -1 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 0, i32 0 @@ -604,6 +639,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmsle.vi v25, v25, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 0, i32 0 @@ -622,6 +658,7 @@ ; CHECK-NEXT: addi a0, zero, 5 ; CHECK-NEXT: vmsgtu.vx v25, v26, a0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 5, i32 0 @@ -639,6 +676,7 @@ ; CHECK-NEXT: vle8.v v28, (a0) ; CHECK-NEXT: vmsleu.vi v25, v28, 4 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 5, i32 0 @@ -656,6 +694,7 @@ ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vmsgtu.vi v25, v8, 4 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 5, i32 0 @@ -672,6 +711,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmsleu.vi v25, v25, 5 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 5, i32 0 @@ -691,6 +731,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -710,6 +751,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -729,6 +771,7 @@ ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -748,6 +791,7 @@ ; CHECK-NEXT: vmv.v.i v26, 0 ; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 ; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -767,6 +811,7 @@ ; CHECK-NEXT: vmv.v.i v26, 0 ; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 ; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -786,6 +831,7 @@ ; CHECK-NEXT: vmv.v.i v26, 0 ; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 ; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll @@ -10,6 +10,7 @@ ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> ret <4 x i16> %s @@ -23,6 +24,7 @@ ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> ret <8 x i32> %s @@ -36,6 +38,7 @@ ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vim v8, v8, 5, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> , <4 x i16> %x, <4 x i32> ret <4 x i16> %s @@ -49,6 +52,7 @@ ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vim v8, v8, 5, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> %x, <4 x i16> , <4 x i32> ret <4 x i16> %s @@ -63,6 +67,7 @@ ; CHECK-NEXT: vle16.v v26, (a0) ; CHECK-NEXT: vrgather.vv v25, v8, v26 ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> ret <4 x i16> %s @@ -77,6 +82,7 @@ ; CHECK-NEXT: vle16.v v26, (a0) ; CHECK-NEXT: vrgather.vv v25, v8, v26 ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> undef, <4 x i16> %x, <4 x i32> ret <4 x i16> %s @@ -96,6 +102,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vrgather.vi v25, v9, 1, v0.t ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> ret <4 x i16> %s @@ -113,6 +120,7 @@ ; CHECK-NEXT: vmv.v.i v25, 5 ; CHECK-NEXT: vrgather.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> , <4 x i16> %x, <4 x i32> ret <4 x i16> %s @@ -131,6 +139,7 @@ ; CHECK-NEXT: vmv.v.i v25, 5 ; CHECK-NEXT: vrgather.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> %x, <4 x i16> , <4 x i32> ret <4 x i16> %s @@ -146,6 +155,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vrgatherei16.vv v28, v8, v25 ; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_permute_shuffle_vu_v8i64: @@ -156,6 +166,7 @@ ; RV64-NEXT: vle64.v v12, (a0) ; RV64-NEXT: vrgather.vv v28, v8, v12 ; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <8 x i64> %x, <8 x i64> undef, <8 x i32> ret <8 x i64> %s @@ -171,6 +182,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vrgatherei16.vv v28, v8, v25 ; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_permute_shuffle_uv_v8i64: @@ -181,6 +193,7 @@ ; RV64-NEXT: vle64.v v12, (a0) ; RV64-NEXT: vrgather.vv v28, v8, v12 ; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <8 x i64> undef, <8 x i64> %x, <8 x i32> ret <8 x i64> %s @@ -207,6 +220,7 @@ ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vrgatherei16.vv v28, v12, v26, v0.t ; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_vv_v8i64: @@ -228,6 +242,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vrgather.vv v28, v12, v16, v0.t ; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> ret <8 x i64> %s @@ -253,6 +268,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vrgatherei16.vv v28, v8, v25, v0.t ; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_xv_v8i64: @@ -267,6 +283,7 @@ ; RV64-NEXT: vmv.v.i v28, -1 ; RV64-NEXT: vrgather.vv v28, v8, v12, v0.t ; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <8 x i64> , <8 x i64> %x, <8 x i32> ret <8 x i64> %s @@ -292,6 +309,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vmv.v.i v28, 5 ; RV32-NEXT: vrgatherei16.vv v8, v28, v25, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_vx_v8i64: @@ -306,6 +324,7 @@ ; RV64-NEXT: vmv.v.i v28, 5 ; RV64-NEXT: vrgather.vv v28, v8, v12, v0.t ; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %s = shufflevector <8 x i64> %x, <8 x i64> , <8 x i32> ret <8 x i64> %s @@ -326,6 +345,7 @@ ; CHECK-NEXT: vsrl.vi v26, v26, 1 ; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vrgather.vv v8, v25, v26, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %y = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> %z = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> @@ -339,6 +359,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vrgather.vi v25, v8, 4 ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuff @@ -355,6 +376,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vrgather.vv v25, v8, v26 ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuff @@ -372,6 +394,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vrgather.vv v25, v8, v26 ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuff @@ -387,6 +410,7 @@ ; CHECK-NEXT: vrgather.vi v25, v8, 2 ; CHECK-NEXT: vrgather.vi v25, v9, 0, v0.t ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -408,6 +432,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vrgather.vi v25, v9, 0, v0.t ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -426,6 +451,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -446,6 +472,7 @@ ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vrgather.vi v25, v9, 0, v0.t ; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: splat_ve2_we0_ins_i2ve4: @@ -462,6 +489,7 @@ ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vrgather.vi v25, v9, 0, v0.t ; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -483,6 +511,7 @@ ; CHECK-NEXT: vrgather.vi v25, v8, 2 ; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t ; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -509,6 +538,7 @@ ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vrgather.vv v25, v9, v26, v0.t ; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6: @@ -531,6 +561,7 @@ ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vrgather.vv v25, v9, v26, v0.t ; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -549,6 +580,7 @@ ; CHECK-NEXT: vslideup.vi v25, v26, 4 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vrgather.vi v8, v25, 3 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %shuf = shufflevector <4 x i8> %v, <4 x i8> undef, <8 x i32> ret <8 x i8> %shuf diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll @@ -12,6 +12,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <16 x i8> undef, i8 %y, i32 0 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer @@ -25,6 +26,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <8 x i16> undef, i16 %y, i32 0 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer @@ -38,6 +40,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <4 x i32> undef, i32 %y, i32 0 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer @@ -57,6 +60,7 @@ ; LMULMAX8-RV32-NEXT: vlse64.v v25, (a1), zero ; LMULMAX8-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX8-RV32-NEXT: addi sp, sp, 16 +; LMULMAX8-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-RV32-NEXT: ret ; ; LMULMAX2-RV32-LABEL: splat_v2i64: @@ -70,6 +74,7 @@ ; LMULMAX2-RV32-NEXT: vlse64.v v25, (a1), zero ; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 16 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_v2i64: @@ -83,6 +88,7 @@ ; LMULMAX1-RV32-NEXT: vlse64.v v25, (a1), zero ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 16 +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX8-RV64-LABEL: splat_v2i64: @@ -90,6 +96,7 @@ ; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX8-RV64-NEXT: vmv.v.x v25, a1 ; LMULMAX8-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX8-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-RV64-NEXT: ret ; ; LMULMAX2-RV64-LABEL: splat_v2i64: @@ -97,6 +104,7 @@ ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX2-RV64-NEXT: vmv.v.x v25, a1 ; LMULMAX2-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_v2i64: @@ -104,6 +112,7 @@ ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = insertelement <2 x i64> undef, i64 %y, i32 0 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer @@ -118,6 +127,7 @@ ; LMULMAX8-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.x v26, a1 ; LMULMAX8-NEXT: vse8.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_v32i8: @@ -126,6 +136,7 @@ ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.x v26, a1 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v32i8: @@ -135,6 +146,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse8.v v25, (a1) ; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <32 x i8> undef, i8 %y, i32 0 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer @@ -148,6 +160,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.x v26, a1 ; LMULMAX8-NEXT: vse16.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_v16i16: @@ -155,6 +168,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.x v26, a1 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v16i16: @@ -164,6 +178,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse16.v v25, (a1) ; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <16 x i16> undef, i16 %y, i32 0 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer @@ -177,6 +192,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.x v26, a1 ; LMULMAX8-NEXT: vse32.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_v8i32: @@ -184,6 +200,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.x v26, a1 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v8i32: @@ -193,6 +210,7 @@ ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse32.v v25, (a1) ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <8 x i32> undef, i32 %y, i32 0 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer @@ -212,6 +230,7 @@ ; LMULMAX8-RV32-NEXT: vlse64.v v26, (a1), zero ; LMULMAX8-RV32-NEXT: vse64.v v26, (a0) ; LMULMAX8-RV32-NEXT: addi sp, sp, 16 +; LMULMAX8-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-RV32-NEXT: ret ; ; LMULMAX2-RV32-LABEL: splat_v4i64: @@ -225,6 +244,7 @@ ; LMULMAX2-RV32-NEXT: vlse64.v v26, (a1), zero ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 16 +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_v4i64: @@ -238,6 +258,7 @@ ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX8-RV64-LABEL: splat_v4i64: @@ -245,6 +266,7 @@ ; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX8-RV64-NEXT: vmv.v.x v26, a1 ; LMULMAX8-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX8-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-RV64-NEXT: ret ; ; LMULMAX2-RV64-LABEL: splat_v4i64: @@ -252,6 +274,7 @@ ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1 ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_v4i64: @@ -261,6 +284,7 @@ ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a1) ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = insertelement <4 x i64> undef, i64 %y, i32 0 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer @@ -274,6 +298,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <16 x i8> undef, i8 0, i32 0 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer @@ -287,6 +312,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <8 x i16> undef, i16 0, i32 0 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer @@ -300,6 +326,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <4 x i32> undef, i32 0, i32 0 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer @@ -313,6 +340,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <2 x i64> undef, i64 0, i32 0 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer @@ -327,6 +355,7 @@ ; LMULMAX8-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.i v26, 0 ; LMULMAX8-NEXT: vse8.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_zero_v32i8: @@ -335,6 +364,7 @@ ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v32i8: @@ -344,6 +374,7 @@ ; LMULMAX1-NEXT: vse8.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <32 x i8> undef, i8 0, i32 0 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer @@ -357,6 +388,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.i v26, 0 ; LMULMAX8-NEXT: vse16.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_zero_v16i16: @@ -364,6 +396,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v16i16: @@ -373,6 +406,7 @@ ; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <16 x i16> undef, i16 0, i32 0 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer @@ -386,6 +420,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.i v26, 0 ; LMULMAX8-NEXT: vse32.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_zero_v8i32: @@ -393,6 +428,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v8i32: @@ -402,6 +438,7 @@ ; LMULMAX1-NEXT: vse32.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <8 x i32> undef, i32 0, i32 0 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer @@ -415,6 +452,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.i v26, 0 ; LMULMAX8-NEXT: vse64.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_zero_v4i64: @@ -422,6 +460,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_zero_v4i64: @@ -431,6 +470,7 @@ ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a0, 16 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_zero_v4i64: @@ -440,6 +480,7 @@ ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a0, 16 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = insertelement <4 x i64> undef, i64 0, i32 0 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer @@ -453,6 +494,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, -1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <16 x i8> undef, i8 -1, i32 0 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer @@ -466,6 +508,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, -1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <8 x i16> undef, i16 -1, i32 0 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer @@ -479,6 +522,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, -1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <4 x i32> undef, i32 -1, i32 0 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer @@ -492,6 +536,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vmv.v.i v25, -1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <2 x i64> undef, i64 -1, i32 0 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer @@ -506,6 +551,7 @@ ; LMULMAX8-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.i v26, -1 ; LMULMAX8-NEXT: vse8.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_v32i8: @@ -514,6 +560,7 @@ ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, -1 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_allones_v32i8: @@ -523,6 +570,7 @@ ; LMULMAX1-NEXT: vse8.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <32 x i8> undef, i8 -1, i32 0 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer @@ -536,6 +584,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.i v26, -1 ; LMULMAX8-NEXT: vse16.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_v16i16: @@ -543,6 +592,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, -1 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_allones_v16i16: @@ -552,6 +602,7 @@ ; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <16 x i16> undef, i16 -1, i32 0 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer @@ -565,6 +616,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.i v26, -1 ; LMULMAX8-NEXT: vse32.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_v8i32: @@ -572,6 +624,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, -1 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_allones_v8i32: @@ -581,6 +634,7 @@ ; LMULMAX1-NEXT: vse32.v v25, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = insertelement <8 x i32> undef, i32 -1, i32 0 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer @@ -594,6 +648,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX8-NEXT: vmv.v.i v26, -1 ; LMULMAX8-NEXT: vse64.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_v4i64: @@ -601,6 +656,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-NEXT: vmv.v.i v26, -1 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_allones_v4i64: @@ -610,6 +666,7 @@ ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a0, 16 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_allones_v4i64: @@ -619,6 +676,7 @@ ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a0, 16 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = insertelement <4 x i64> undef, i64 -1, i32 0 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer @@ -637,6 +695,7 @@ ; LMULMAX8-NEXT: vle64.v v26, (a0) ; LMULMAX8-NEXT: vadd.vi v26, v26, -1 ; LMULMAX8-NEXT: vse64.v v26, (a0) +; LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_with_use_v4i64: @@ -645,6 +704,7 @@ ; LMULMAX2-NEXT: vle64.v v26, (a0) ; LMULMAX2-NEXT: vadd.vi v26, v26, -1 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_allones_with_use_v4i64: @@ -660,6 +720,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_allones_with_use_v4i64: @@ -672,6 +733,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vi v26, v26, -1 ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = add <4 x i64> %a, @@ -697,6 +759,7 @@ ; LMULMAX8-RV32-NEXT: vadd.vv v8, v8, v16 ; LMULMAX8-RV32-NEXT: vse64.v v8, (a3) ; LMULMAX8-RV32-NEXT: addi sp, sp, 16 +; LMULMAX8-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-RV32-NEXT: ret ; ; LMULMAX2-RV32-LABEL: vadd_vx_v16i64: @@ -727,6 +790,7 @@ ; LMULMAX2-RV32-NEXT: vse64.v v30, (a3) ; LMULMAX2-RV32-NEXT: addi a0, a3, 32 ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX1-RV32-LABEL: vadd_vx_v16i64: @@ -777,6 +841,7 @@ ; LMULMAX1-RV32-NEXT: vse64.v v31, (a3) ; LMULMAX1-RV32-NEXT: addi a0, a3, 16 ; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX8-RV64-LABEL: vadd_vx_v16i64: @@ -785,6 +850,7 @@ ; LMULMAX8-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX8-RV64-NEXT: vadd.vx v8, v8, a1 ; LMULMAX8-RV64-NEXT: vse64.v v8, (a2) +; LMULMAX8-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX8-RV64-NEXT: ret ; ; LMULMAX2-RV64-LABEL: vadd_vx_v16i64: @@ -808,6 +874,7 @@ ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: addi a0, a2, 32 ; LMULMAX2-RV64-NEXT: vse64.v v28, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV64-LABEL: vadd_vx_v16i64: @@ -851,6 +918,7 @@ ; LMULMAX1-RV64-NEXT: vse64.v v29, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a2, 16 ; LMULMAX1-RV64-NEXT: vse64.v v30, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %va = load <16 x i64>, <16 x i64>* %a %head = insertelement <16 x i64> undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll @@ -11,6 +11,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vlse8.v v25, (a1), zero ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = extractelement <16 x i8> %a, i32 12 @@ -27,6 +28,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vlse16.v v25, (a1), zero ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = extractelement <8 x i16> %a, i32 5 @@ -43,6 +45,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vlse32.v v25, (a1), zero ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = extractelement <4 x i32> %a, i32 3 @@ -59,6 +62,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vlse64.v v25, (a1), zero ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = extractelement <2 x i64> %a, i32 1 @@ -76,6 +80,7 @@ ; LMULMAX4-NEXT: vsetvli zero, a2, e8, m4, ta, mu ; LMULMAX4-NEXT: vlse8.v v28, (a1), zero ; LMULMAX4-NEXT: vse8.v v28, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v64i8: @@ -89,6 +94,7 @@ ; LMULMAX1-NEXT: vse8.v v25, (a3) ; LMULMAX1-NEXT: vse8.v v25, (a0) ; LMULMAX1-NEXT: vse8.v v25, (a2) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = extractelement <64 x i8> %a, i32 32 @@ -106,6 +112,7 @@ ; LMULMAX4-NEXT: vsetvli zero, a2, e16, m4, ta, mu ; LMULMAX4-NEXT: vlse16.v v28, (a1), zero ; LMULMAX4-NEXT: vse16.v v28, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v16i16: @@ -120,6 +127,7 @@ ; LMULMAX1-NEXT: vse16.v v25, (a2) ; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: vse16.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = extractelement <32 x i16> %a, i32 25 @@ -136,6 +144,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: vlse32.v v28, (a1), zero ; LMULMAX4-NEXT: vse32.v v28, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v16i32: @@ -150,6 +159,7 @@ ; LMULMAX1-NEXT: vse32.v v25, (a2) ; LMULMAX1-NEXT: vse32.v v25, (a0) ; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = extractelement <16 x i32> %a, i32 9 @@ -166,6 +176,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vlse64.v v28, (a1), zero ; LMULMAX4-NEXT: vse64.v v28, (a0) +; LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX4-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v8i64: @@ -180,6 +191,7 @@ ; LMULMAX1-NEXT: vse64.v v25, (a2) ; LMULMAX1-NEXT: vse64.v v25, (a0) ; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = extractelement <8 x i64> %a, i32 3 @@ -196,6 +208,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vlse16.v v25, (a0), zero ; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load <4 x i16>, <4 x i16>* %y @@ -212,6 +225,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vlse16.v v25, (a0), zero ; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load <4 x i16>, <4 x i16>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll @@ -12,6 +12,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -28,6 +29,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -44,6 +46,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -60,6 +63,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -76,6 +80,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vsub.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -92,6 +97,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vsub.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -108,6 +114,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vsub.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -124,6 +131,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vsub.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -140,6 +148,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vmul.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -156,6 +165,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vmul.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -172,6 +182,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vmul.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -188,6 +199,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vmul.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -204,6 +216,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vand.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -220,6 +233,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vand.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -236,6 +250,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vand.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -252,6 +267,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vand.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -268,6 +284,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vor.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -284,6 +301,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vor.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -300,6 +318,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vor.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -316,6 +335,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vor.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -332,6 +352,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vxor.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -348,6 +369,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vxor.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -364,6 +386,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vxor.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -380,6 +403,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vxor.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -396,6 +420,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vsrl.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -412,6 +437,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vsrl.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -428,6 +454,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vsrl.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -444,6 +471,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vsrl.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -460,6 +488,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vsra.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -476,6 +505,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vsra.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -492,6 +522,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vsra.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -508,6 +539,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vsra.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -524,6 +556,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vsll.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -540,6 +573,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vsll.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -556,6 +590,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vsll.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -572,6 +607,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vsll.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -588,6 +624,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vdiv.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -604,6 +641,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vdiv.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -620,6 +658,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vdiv.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -636,6 +675,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vdiv.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -652,6 +692,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vrem.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -668,6 +709,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vrem.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -684,6 +726,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vrem.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -700,6 +743,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vrem.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -716,6 +760,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vdivu.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -732,6 +777,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vdivu.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -748,6 +794,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vdivu.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -764,6 +811,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vdivu.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -780,6 +828,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vremu.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -796,6 +845,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vremu.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -812,6 +862,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vremu.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -828,6 +879,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vremu.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -882,6 +934,7 @@ ; RV32-NEXT: vadd.vv v25, v25, v27 ; RV32-NEXT: vsrl.vv v25, v25, v26 ; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_v16i8: @@ -929,6 +982,7 @@ ; RV64-NEXT: vadd.vv v25, v25, v27 ; RV64-NEXT: vsrl.vv v25, v25, v26 ; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = udiv <16 x i8> %a, @@ -970,6 +1024,7 @@ ; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vsrl.vv v25, v25, v27 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = udiv <8 x i16> %a, @@ -1003,6 +1058,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsrl.vv v25, v25, v27 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = udiv <4 x i32> %a, @@ -1028,6 +1084,7 @@ ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsrl.vv v25, v25, v26 ; RV32-NEXT: vse64.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_v2i64: @@ -1059,6 +1116,7 @@ ; RV64-NEXT: vadd.vi v26, v26, 1 ; RV64-NEXT: vsrl.vv v25, v25, v26 ; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = udiv <2 x i64> %a, @@ -1085,6 +1143,7 @@ ; RV32-NEXT: vmulhu.vv v25, v25, v27 ; RV32-NEXT: vsrl.vv v25, v25, v26 ; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_v16i8: @@ -1105,6 +1164,7 @@ ; RV64-NEXT: vmulhu.vv v25, v25, v27 ; RV64-NEXT: vsrl.vv v25, v25, v26 ; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = udiv <16 x i8> %a, @@ -1132,6 +1192,7 @@ ; RV32-NEXT: vsrl.vi v26, v25, 15 ; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vse16.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_v8i16: @@ -1153,6 +1214,7 @@ ; RV64-NEXT: vsrl.vi v26, v25, 15 ; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vse16.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = sdiv <8 x i16> %a, @@ -1180,6 +1242,7 @@ ; RV32-NEXT: vsra.vi v25, v25, 1 ; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_v4i32: @@ -1202,6 +1265,7 @@ ; RV64-NEXT: vsrl.vi v26, v25, 31 ; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vse32.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = sdiv <4 x i32> %a, @@ -1241,6 +1305,7 @@ ; RV32-NEXT: vsrl.vx v26, v27, a1 ; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vse64.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_v2i64: @@ -1269,6 +1334,7 @@ ; RV64-NEXT: vsra.vv v26, v28, v27 ; RV64-NEXT: vadd.vv v25, v26, v25 ; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = sdiv <2 x i64> %a, @@ -1284,6 +1350,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vmin.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1301,6 +1368,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vmin.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -1318,6 +1386,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vmin.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -1335,6 +1404,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vmin.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -1352,6 +1422,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vmax.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1369,6 +1440,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vmax.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -1386,6 +1458,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vmax.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -1403,6 +1476,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vmax.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -1420,6 +1494,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vminu.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1437,6 +1512,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vminu.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -1454,6 +1530,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vminu.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -1471,6 +1548,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vminu.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -1488,6 +1566,7 @@ ; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vmaxu.vv v25, v25, v26 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1505,6 +1584,7 @@ ; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vmaxu.vv v25, v25, v26 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -1522,6 +1602,7 @@ ; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vmaxu.vv v25, v25, v26 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -1539,6 +1620,7 @@ ; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vmaxu.vv v25, v25, v26 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -1557,6 +1639,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: add_v32i8: @@ -1572,6 +1655,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: add_v32i8: @@ -1587,6 +1671,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -1603,6 +1688,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: add_v16i16: @@ -1618,6 +1704,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: add_v16i16: @@ -1633,6 +1720,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -1649,6 +1737,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: add_v8i32: @@ -1664,6 +1753,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: add_v8i32: @@ -1679,6 +1769,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -1695,6 +1786,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: add_v4i64: @@ -1710,6 +1802,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: add_v4i64: @@ -1725,6 +1818,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -1742,6 +1836,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vsub.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sub_v32i8: @@ -1757,6 +1852,7 @@ ; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sub_v32i8: @@ -1772,6 +1868,7 @@ ; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -1788,6 +1885,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vsub.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sub_v16i16: @@ -1803,6 +1901,7 @@ ; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sub_v16i16: @@ -1818,6 +1917,7 @@ ; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -1834,6 +1934,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vsub.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sub_v8i32: @@ -1849,6 +1950,7 @@ ; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sub_v8i32: @@ -1864,6 +1966,7 @@ ; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -1880,6 +1983,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vsub.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sub_v4i64: @@ -1895,6 +1999,7 @@ ; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sub_v4i64: @@ -1910,6 +2015,7 @@ ; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -1927,6 +2033,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vmul.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mul_v32i8: @@ -1942,6 +2049,7 @@ ; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mul_v32i8: @@ -1957,6 +2065,7 @@ ; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -1973,6 +2082,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vmul.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mul_v16i16: @@ -1988,6 +2098,7 @@ ; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mul_v16i16: @@ -2003,6 +2114,7 @@ ; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2019,6 +2131,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vmul.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mul_v8i32: @@ -2034,6 +2147,7 @@ ; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mul_v8i32: @@ -2049,6 +2163,7 @@ ; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2065,6 +2180,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vmul.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mul_v4i64: @@ -2080,6 +2196,7 @@ ; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mul_v4i64: @@ -2095,6 +2212,7 @@ ; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2112,6 +2230,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vand.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: and_v32i8: @@ -2127,6 +2246,7 @@ ; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: and_v32i8: @@ -2142,6 +2262,7 @@ ; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2158,6 +2279,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vand.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: and_v16i16: @@ -2173,6 +2295,7 @@ ; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: and_v16i16: @@ -2188,6 +2311,7 @@ ; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2204,6 +2328,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vand.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: and_v8i32: @@ -2219,6 +2344,7 @@ ; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: and_v8i32: @@ -2234,6 +2360,7 @@ ; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2250,6 +2377,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vand.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: and_v4i64: @@ -2265,6 +2393,7 @@ ; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: and_v4i64: @@ -2280,6 +2409,7 @@ ; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2297,6 +2427,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vor.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: or_v32i8: @@ -2312,6 +2443,7 @@ ; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: or_v32i8: @@ -2327,6 +2459,7 @@ ; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2343,6 +2476,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vor.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: or_v16i16: @@ -2358,6 +2492,7 @@ ; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: or_v16i16: @@ -2373,6 +2508,7 @@ ; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2389,6 +2525,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vor.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: or_v8i32: @@ -2404,6 +2541,7 @@ ; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: or_v8i32: @@ -2419,6 +2557,7 @@ ; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2435,6 +2574,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vor.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: or_v4i64: @@ -2450,6 +2590,7 @@ ; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: or_v4i64: @@ -2465,6 +2606,7 @@ ; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2482,6 +2624,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vxor.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: xor_v32i8: @@ -2497,6 +2640,7 @@ ; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: xor_v32i8: @@ -2512,6 +2656,7 @@ ; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2528,6 +2673,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vxor.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: xor_v16i16: @@ -2543,6 +2689,7 @@ ; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: xor_v16i16: @@ -2558,6 +2705,7 @@ ; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2574,6 +2722,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vxor.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: xor_v8i32: @@ -2589,6 +2738,7 @@ ; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: xor_v8i32: @@ -2604,6 +2754,7 @@ ; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2620,6 +2771,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vxor.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: xor_v4i64: @@ -2635,6 +2787,7 @@ ; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: xor_v4i64: @@ -2650,6 +2803,7 @@ ; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2667,6 +2821,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: lshr_v32i8: @@ -2682,6 +2837,7 @@ ; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: lshr_v32i8: @@ -2697,6 +2853,7 @@ ; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2713,6 +2870,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: lshr_v16i16: @@ -2728,6 +2886,7 @@ ; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: lshr_v16i16: @@ -2743,6 +2902,7 @@ ; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2759,6 +2919,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: lshr_v8i32: @@ -2774,6 +2935,7 @@ ; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: lshr_v8i32: @@ -2789,6 +2951,7 @@ ; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2805,6 +2968,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: lshr_v4i64: @@ -2820,6 +2984,7 @@ ; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: lshr_v4i64: @@ -2835,6 +3000,7 @@ ; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2852,6 +3018,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vsra.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ashr_v32i8: @@ -2867,6 +3034,7 @@ ; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ashr_v32i8: @@ -2882,6 +3050,7 @@ ; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2898,6 +3067,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vsra.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ashr_v16i16: @@ -2913,6 +3083,7 @@ ; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ashr_v16i16: @@ -2928,6 +3099,7 @@ ; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2944,6 +3116,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vsra.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ashr_v8i32: @@ -2959,6 +3132,7 @@ ; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ashr_v8i32: @@ -2974,6 +3148,7 @@ ; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2990,6 +3165,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vsra.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ashr_v4i64: @@ -3005,6 +3181,7 @@ ; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ashr_v4i64: @@ -3020,6 +3197,7 @@ ; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3037,6 +3215,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vsll.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: shl_v32i8: @@ -3052,6 +3231,7 @@ ; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: shl_v32i8: @@ -3067,6 +3247,7 @@ ; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3083,6 +3264,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vsll.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: shl_v16i16: @@ -3098,6 +3280,7 @@ ; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: shl_v16i16: @@ -3113,6 +3296,7 @@ ; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3129,6 +3313,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vsll.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: shl_v8i32: @@ -3144,6 +3329,7 @@ ; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: shl_v8i32: @@ -3159,6 +3345,7 @@ ; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3175,6 +3362,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vsll.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: shl_v4i64: @@ -3190,6 +3378,7 @@ ; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: shl_v4i64: @@ -3205,6 +3394,7 @@ ; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3222,6 +3412,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vdiv.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sdiv_v32i8: @@ -3237,6 +3428,7 @@ ; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sdiv_v32i8: @@ -3252,6 +3444,7 @@ ; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3268,6 +3461,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vdiv.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sdiv_v16i16: @@ -3283,6 +3477,7 @@ ; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sdiv_v16i16: @@ -3298,6 +3493,7 @@ ; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3314,6 +3510,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vdiv.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sdiv_v8i32: @@ -3329,6 +3526,7 @@ ; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sdiv_v8i32: @@ -3344,6 +3542,7 @@ ; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3360,6 +3559,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vdiv.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sdiv_v4i64: @@ -3375,6 +3575,7 @@ ; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sdiv_v4i64: @@ -3390,6 +3591,7 @@ ; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3407,6 +3609,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vrem.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: srem_v32i8: @@ -3422,6 +3625,7 @@ ; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: srem_v32i8: @@ -3437,6 +3641,7 @@ ; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3453,6 +3658,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vrem.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: srem_v16i16: @@ -3468,6 +3674,7 @@ ; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: srem_v16i16: @@ -3483,6 +3690,7 @@ ; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3499,6 +3707,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vrem.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: srem_v8i32: @@ -3514,6 +3723,7 @@ ; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: srem_v8i32: @@ -3529,6 +3739,7 @@ ; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3545,6 +3756,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vrem.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: srem_v4i64: @@ -3560,6 +3772,7 @@ ; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: srem_v4i64: @@ -3575,6 +3788,7 @@ ; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3592,6 +3806,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vdivu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: udiv_v32i8: @@ -3607,6 +3822,7 @@ ; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: udiv_v32i8: @@ -3622,6 +3838,7 @@ ; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3638,6 +3855,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vdivu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: udiv_v16i16: @@ -3653,6 +3871,7 @@ ; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: udiv_v16i16: @@ -3668,6 +3887,7 @@ ; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3684,6 +3904,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vdivu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: udiv_v8i32: @@ -3699,6 +3920,7 @@ ; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: udiv_v8i32: @@ -3714,6 +3936,7 @@ ; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3730,6 +3953,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vdivu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: udiv_v4i64: @@ -3745,6 +3969,7 @@ ; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: udiv_v4i64: @@ -3760,6 +3985,7 @@ ; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3777,6 +4003,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vremu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: urem_v32i8: @@ -3792,6 +4019,7 @@ ; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: urem_v32i8: @@ -3807,6 +4035,7 @@ ; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3823,6 +4052,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vremu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: urem_v16i16: @@ -3838,6 +4068,7 @@ ; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: urem_v16i16: @@ -3853,6 +4084,7 @@ ; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3869,6 +4101,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vremu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: urem_v8i32: @@ -3884,6 +4117,7 @@ ; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: urem_v8i32: @@ -3899,6 +4133,7 @@ ; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3915,6 +4150,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vremu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: urem_v4i64: @@ -3930,6 +4166,7 @@ ; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: urem_v4i64: @@ -3945,6 +4182,7 @@ ; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3961,6 +4199,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v4i64: @@ -3976,6 +4215,7 @@ ; LMULMAX1-NEXT: vadd.vv v25, v25, v27 ; LMULMAX1-NEXT: vse64.v v25, (a0) ; LMULMAX1-NEXT: vse64.v v26, (a2) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -4035,6 +4275,7 @@ ; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 2, v0 ; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhu_v32i8: @@ -4085,6 +4326,7 @@ ; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 2, v0 ; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-RV64-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-LABEL: mulhu_v32i8: @@ -4100,6 +4342,7 @@ ; LMULMAX1-NEXT: vdivu.vv v26, v27, v26 ; LMULMAX1-NEXT: vse8.v v26, (a0) ; LMULMAX1-NEXT: vse8.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = udiv <32 x i8> %a, @@ -4145,6 +4388,7 @@ ; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v30 ; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhu_v16i16: @@ -4184,6 +4428,7 @@ ; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v30 ; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-LABEL: mulhu_v16i16: @@ -4199,6 +4444,7 @@ ; LMULMAX1-NEXT: vdivu.vv v26, v27, v26 ; LMULMAX1-NEXT: vse16.v v26, (a0) ; LMULMAX1-NEXT: vse16.v v25, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = udiv <16 x i16> %a, @@ -4233,6 +4479,7 @@ ; LMULMAX2-NEXT: vmerge.vim v28, v28, 1, v0 ; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhu_v8i32: @@ -4268,6 +4515,7 @@ ; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v30 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhu_v8i32: @@ -4283,6 +4531,7 @@ ; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26 ; LMULMAX1-RV64-NEXT: vse32.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = udiv <8 x i32> %a, @@ -4318,6 +4567,7 @@ ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhu_v4i64: @@ -4343,6 +4593,7 @@ ; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v8 ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhu_v4i64: @@ -4365,6 +4616,7 @@ ; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhu_v4i64: @@ -4431,6 +4683,7 @@ ; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = udiv <4 x i64> %a, @@ -4458,6 +4711,7 @@ ; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0 ; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhs_v32i8: @@ -4479,6 +4733,7 @@ ; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 1, v0 ; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-RV64-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhs_v32i8: @@ -4498,6 +4753,7 @@ ; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhs_v32i8: @@ -4517,6 +4773,7 @@ ; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v27 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = udiv <32 x i8> %a, @@ -4545,6 +4802,7 @@ ; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 15 ; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhs_v16i16: @@ -4567,6 +4825,7 @@ ; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 15 ; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-LABEL: mulhs_v16i16: @@ -4585,6 +4844,7 @@ ; LMULMAX1-NEXT: vdiv.vv v25, v25, v27 ; LMULMAX1-NEXT: vse16.v v25, (a0) ; LMULMAX1-NEXT: vse16.v v26, (a1) +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = sdiv <16 x i16> %a, @@ -4612,6 +4872,7 @@ ; LMULMAX2-RV32-NEXT: vsra.vi v26, v26, 1 ; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhs_v8i32: @@ -4634,6 +4895,7 @@ ; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 31 ; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhs_v8i32: @@ -4662,6 +4924,7 @@ ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhs_v8i32: @@ -4680,6 +4943,7 @@ ; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v27 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = sdiv <8 x i32> %a, @@ -4723,6 +4987,7 @@ ; LMULMAX2-RV32-NEXT: vsra.vv v28, v30, v28 ; LMULMAX2-RV32-NEXT: vadd.vv v26, v28, v26 ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhs_v4i64: @@ -4755,6 +5020,7 @@ ; LMULMAX2-RV64-NEXT: vsra.vv v28, v30, v28 ; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26 ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhs_v4i64: @@ -4772,6 +5038,7 @@ ; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v27 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhs_v4i64: @@ -4808,6 +5075,7 @@ ; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = sdiv <4 x i64> %a, @@ -4824,6 +5092,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vmin.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smin_v32i8: @@ -4839,6 +5108,7 @@ ; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smin_v32i8: @@ -4854,6 +5124,7 @@ ; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -4871,6 +5142,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vmin.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smin_v16i16: @@ -4886,6 +5158,7 @@ ; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smin_v16i16: @@ -4901,6 +5174,7 @@ ; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -4918,6 +5192,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vmin.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smin_v8i32: @@ -4933,6 +5208,7 @@ ; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smin_v8i32: @@ -4948,6 +5224,7 @@ ; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -4965,6 +5242,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vmin.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smin_v4i64: @@ -4980,6 +5258,7 @@ ; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smin_v4i64: @@ -4995,6 +5274,7 @@ ; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -5013,6 +5293,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vmax.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smax_v32i8: @@ -5028,6 +5309,7 @@ ; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smax_v32i8: @@ -5043,6 +5325,7 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -5060,6 +5343,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vmax.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smax_v16i16: @@ -5075,6 +5359,7 @@ ; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smax_v16i16: @@ -5090,6 +5375,7 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -5107,6 +5393,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vmax.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smax_v8i32: @@ -5122,6 +5409,7 @@ ; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smax_v8i32: @@ -5137,6 +5425,7 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -5154,6 +5443,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vmax.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smax_v4i64: @@ -5169,6 +5459,7 @@ ; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smax_v4i64: @@ -5184,6 +5475,7 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -5202,6 +5494,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vminu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umin_v32i8: @@ -5217,6 +5510,7 @@ ; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umin_v32i8: @@ -5232,6 +5526,7 @@ ; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -5249,6 +5544,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vminu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umin_v16i16: @@ -5264,6 +5560,7 @@ ; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umin_v16i16: @@ -5279,6 +5576,7 @@ ; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -5296,6 +5594,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vminu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umin_v8i32: @@ -5311,6 +5610,7 @@ ; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umin_v8i32: @@ -5326,6 +5626,7 @@ ; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -5343,6 +5644,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vminu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umin_v4i64: @@ -5358,6 +5660,7 @@ ; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umin_v4i64: @@ -5373,6 +5676,7 @@ ; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -5391,6 +5695,7 @@ ; LMULMAX2-NEXT: vle8.v v28, (a1) ; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umax_v32i8: @@ -5406,6 +5711,7 @@ ; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umax_v32i8: @@ -5421,6 +5727,7 @@ ; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -5438,6 +5745,7 @@ ; LMULMAX2-NEXT: vle16.v v28, (a1) ; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umax_v16i16: @@ -5453,6 +5761,7 @@ ; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umax_v16i16: @@ -5468,6 +5777,7 @@ ; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -5485,6 +5795,7 @@ ; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umax_v8i32: @@ -5500,6 +5811,7 @@ ; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umax_v8i32: @@ -5515,6 +5827,7 @@ ; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -5532,6 +5845,7 @@ ; LMULMAX2-NEXT: vle64.v v28, (a1) ; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28 ; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umax_v4i64: @@ -5547,6 +5861,7 @@ ; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umax_v4i64: @@ -5562,6 +5877,7 @@ ; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -5578,6 +5894,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vadd.vi v25, v25, -1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -1, i32 0 @@ -5594,6 +5911,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vadd.vi v25, v25, -1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -1, i32 0 @@ -5610,6 +5928,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vadd.vi v25, v25, -1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -1, i32 0 @@ -5626,6 +5945,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vadd.vi v25, v25, -1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -1, i32 0 @@ -5642,6 +5962,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vadd.vi v25, v25, 1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -5658,6 +5979,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vadd.vi v25, v25, 1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -5674,6 +5996,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vadd.vi v25, v25, 1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -5690,6 +6013,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vadd.vi v25, v25, 1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -5706,6 +6030,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vadd.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -5722,6 +6047,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vadd.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -5738,6 +6064,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vadd.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -5754,6 +6081,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vadd.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -5770,6 +6098,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vadd.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -5786,6 +6115,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vadd.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -5803,6 +6133,7 @@ ; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: vsub.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -1, i32 0 @@ -5820,6 +6151,7 @@ ; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: vsub.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -1, i32 0 @@ -5837,6 +6169,7 @@ ; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: vsub.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -1, i32 0 @@ -5854,6 +6187,7 @@ ; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: vsub.vx v25, v25, a1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -1, i32 0 @@ -5870,6 +6204,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vrsub.vi v25, v25, 1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -5886,6 +6221,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vrsub.vi v25, v25, 1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -5902,6 +6238,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vrsub.vi v25, v25, 1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -5918,6 +6255,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vrsub.vi v25, v25, 1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -5934,6 +6272,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsub.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -5950,6 +6289,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsub.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -5966,6 +6306,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsub.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -5982,6 +6323,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vrsub.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -5998,6 +6340,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vrsub.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6014,6 +6357,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vrsub.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6030,6 +6374,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmul.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6046,6 +6391,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmul.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6062,6 +6408,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmul.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6078,6 +6425,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmul.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6094,6 +6442,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmul.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6110,6 +6459,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmul.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6126,6 +6476,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vand.vi v25, v25, -2 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -2, i32 0 @@ -6142,6 +6493,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vand.vi v25, v25, -2 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -2, i32 0 @@ -6158,6 +6510,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vand.vi v25, v25, -2 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -2, i32 0 @@ -6174,6 +6527,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vand.vi v25, v25, -2 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -2, i32 0 @@ -6190,6 +6544,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -6206,6 +6561,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -6222,6 +6578,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -6238,6 +6595,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -6254,6 +6612,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vand.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6270,6 +6629,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vand.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6286,6 +6646,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vand.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6302,6 +6663,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vand.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6318,6 +6680,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vand.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6334,6 +6697,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vand.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6350,6 +6714,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vor.vi v25, v25, -2 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -2, i32 0 @@ -6366,6 +6731,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vor.vi v25, v25, -2 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -2, i32 0 @@ -6382,6 +6748,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vor.vi v25, v25, -2 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -2, i32 0 @@ -6398,6 +6765,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vor.vi v25, v25, -2 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -2, i32 0 @@ -6414,6 +6782,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vor.vi v25, v25, 1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -6430,6 +6799,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vor.vi v25, v25, 1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -6446,6 +6816,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vor.vi v25, v25, 1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -6462,6 +6833,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vor.vi v25, v25, 1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -6478,6 +6850,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vor.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6494,6 +6867,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vor.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6510,6 +6884,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vor.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6526,6 +6901,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vor.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6542,6 +6918,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vor.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6558,6 +6935,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vor.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6574,6 +6952,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vxor.vi v25, v25, -1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -1, i32 0 @@ -6590,6 +6969,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vxor.vi v25, v25, -1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -1, i32 0 @@ -6606,6 +6986,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vxor.vi v25, v25, -1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -1, i32 0 @@ -6622,6 +7003,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vxor.vi v25, v25, -1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -1, i32 0 @@ -6638,6 +7020,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vxor.vi v25, v25, 1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -6654,6 +7037,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vxor.vi v25, v25, 1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -6670,6 +7054,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vxor.vi v25, v25, 1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -6686,6 +7071,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vxor.vi v25, v25, 1 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -6702,6 +7088,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vxor.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6718,6 +7105,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vxor.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6734,6 +7122,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vxor.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6750,6 +7139,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vxor.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6766,6 +7156,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vxor.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6782,6 +7173,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vxor.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6798,6 +7190,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsrl.vi v25, v25, 7 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 7, i32 0 @@ -6814,6 +7207,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsrl.vi v25, v25, 15 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 15, i32 0 @@ -6830,6 +7224,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsrl.vi v25, v25, 31 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 31, i32 0 @@ -6846,6 +7241,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vsrl.vi v25, v25, 31 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 31, i32 0 @@ -6862,6 +7258,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6878,6 +7275,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6894,6 +7292,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6910,6 +7309,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsra.vi v25, v25, 7 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 7, i32 0 @@ -6926,6 +7326,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsra.vi v25, v25, 15 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 15, i32 0 @@ -6942,6 +7343,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsra.vi v25, v25, 31 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 31, i32 0 @@ -6958,6 +7360,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vsra.vi v25, v25, 31 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 31, i32 0 @@ -6974,6 +7377,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsra.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6990,6 +7394,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsra.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7006,6 +7411,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsra.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7022,6 +7428,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsll.vi v25, v25, 7 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 7, i32 0 @@ -7038,6 +7445,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsll.vi v25, v25, 15 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 15, i32 0 @@ -7054,6 +7462,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsll.vi v25, v25, 31 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 31, i32 0 @@ -7070,6 +7479,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vsll.vi v25, v25, 31 ; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 31, i32 0 @@ -7086,6 +7496,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vsll.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7102,6 +7513,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vsll.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7118,6 +7530,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vsll.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7134,6 +7547,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vdiv.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7150,6 +7564,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vdiv.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7166,6 +7581,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vdiv.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7182,6 +7598,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vrem.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7198,6 +7615,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vrem.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7214,6 +7632,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vrem.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7230,6 +7649,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vdivu.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7246,6 +7666,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vdivu.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7262,6 +7683,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vdivu.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7278,6 +7700,7 @@ ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vremu.vx v25, v25, a1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7294,6 +7717,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vremu.vx v25, v25, a1 ; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7310,6 +7734,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vremu.vx v25, v25, a1 ; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7328,6 +7753,7 @@ ; CHECK-NEXT: vmulhu.vx v25, v25, a1 ; CHECK-NEXT: vsrl.vi v25, v25, 1 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = udiv <16 x i8> %a, @@ -7348,6 +7774,7 @@ ; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vsrl.vi v25, v25, 2 ; RV32-NEXT: vse16.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_vx_v8i16: @@ -7362,6 +7789,7 @@ ; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vsrl.vi v25, v25, 2 ; RV64-NEXT: vse16.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = udiv <8 x i16> %a, @@ -7379,6 +7807,7 @@ ; RV32-NEXT: vmulhu.vx v25, v25, a1 ; RV32-NEXT: vsrl.vi v25, v25, 2 ; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_vx_v4i32: @@ -7390,6 +7819,7 @@ ; RV64-NEXT: vmulhu.vx v25, v25, a1 ; RV64-NEXT: vsrl.vi v25, v25, 2 ; RV64-NEXT: vse32.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = udiv <4 x i32> %a, @@ -7415,6 +7845,7 @@ ; RV32-NEXT: vsrl.vi v25, v25, 1 ; RV32-NEXT: vse64.v v25, (a0) ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_vx_v2i64: @@ -7432,6 +7863,7 @@ ; RV64-NEXT: vmulhu.vx v25, v25, a1 ; RV64-NEXT: vsrl.vi v25, v25, 1 ; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = udiv <2 x i64> %a, @@ -7448,6 +7880,7 @@ ; CHECK-NEXT: vmulhu.vx v25, v25, a1 ; CHECK-NEXT: vsrl.vi v25, v25, 7 ; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = udiv <16 x i8> %a, @@ -7467,6 +7900,7 @@ ; RV32-NEXT: vsrl.vi v26, v25, 15 ; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vse16.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_vx_v8i16: @@ -7480,6 +7914,7 @@ ; RV64-NEXT: vsrl.vi v26, v25, 15 ; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vse16.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = sdiv <8 x i16> %a, @@ -7499,6 +7934,7 @@ ; RV32-NEXT: vsra.vi v25, v25, 1 ; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_vx_v4i32: @@ -7512,6 +7948,7 @@ ; RV64-NEXT: vsrl.vi v26, v25, 31 ; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vse32.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = sdiv <4 x i32> %a, @@ -7539,6 +7976,7 @@ ; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vse64.v v25, (a0) ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_vx_v2i64: @@ -7558,6 +7996,7 @@ ; RV64-NEXT: vsrl.vx v26, v25, a1 ; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = sdiv <2 x i64> %a, diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll @@ -15,6 +15,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <1 x i1> undef, i1 %x, i32 0 ret <1 x i1> %1 @@ -27,6 +28,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <1 x i1> undef, i1 %x, i32 0 ret <1 x i1> %1 @@ -42,6 +44,7 @@ ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <2 x i1> undef, i1 %x, i32 0 %2 = insertelement <2 x i1> %1, i1 %y, i32 1 @@ -62,6 +65,7 @@ ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <2 x i1> undef, i1 %x, i32 0 %2 = insertelement <2 x i1> %1, i1 %y, i32 1 @@ -74,6 +78,7 @@ ; CHECK-NEXT: addi a0, zero, 2 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret ret <3 x i1> } @@ -84,6 +89,7 @@ ; CHECK-NEXT: addi a0, zero, 2 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret ret <3 x i1> } @@ -94,6 +100,7 @@ ; CHECK-NEXT: addi a0, zero, 6 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret ret <4 x i1> } @@ -109,6 +116,7 @@ ; CHECK-NEXT: vmerge.vxm v25, v25, a0, v0 ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <4 x i1> undef, i1 %x, i32 0 %2 = insertelement <4 x i1> %1, i1 %x, i32 1 @@ -133,6 +141,7 @@ ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <4 x i1> undef, i1 %x, i32 0 %2 = insertelement <4 x i1> %1, i1 %x, i32 1 @@ -157,6 +166,7 @@ ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <4 x i1> undef, i1 0, i32 0 %2 = insertelement <4 x i1> %1, i1 %x, i32 1 @@ -171,6 +181,7 @@ ; CHECK-NEXT: addi a0, zero, 182 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret ret <8 x i1> } @@ -186,6 +197,7 @@ ; CHECK-NEXT: vmerge.vxm v25, v25, a0, v0 ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <8 x i1> undef, i1 %x, i32 0 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 @@ -218,6 +230,7 @@ ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <8 x i1> undef, i1 %x, i32 0 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 @@ -250,6 +263,7 @@ ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <8 x i1> undef, i1 %x, i32 0 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 @@ -281,6 +295,7 @@ ; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %1 = insertelement <8 x i1> undef, i1 %x, i32 0 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 @@ -299,6 +314,7 @@ ; CHECK-NEXT: addi a0, zero, 949 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret ret <10 x i1> } @@ -310,6 +326,7 @@ ; CHECK-RV32-NEXT: addi a0, a0, 1718 ; CHECK-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-RV32-NEXT: vmv.s.x v0, a0 +; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 ; CHECK-RV32-NEXT: ret ; ; CHECK-RV64-LABEL: buildvec_mask_v16i1: @@ -318,6 +335,7 @@ ; CHECK-RV64-NEXT: addiw a0, a0, 1718 ; CHECK-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-RV64-NEXT: vmv.s.x v0, a0 +; CHECK-RV64-NEXT: .cfi_def_cfa_offset 0 ; CHECK-RV64-NEXT: ret ret <16 x i1> } @@ -328,6 +346,7 @@ ; CHECK-NEXT: addi a0, zero, 1722 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret ret <16 x i1> } @@ -341,6 +360,7 @@ ; RV32-LMULMAX1-NEXT: lui a0, 11 ; RV32-LMULMAX1-NEXT: addi a0, a0, 1718 ; RV32-LMULMAX1-NEXT: vmv.s.x v8, a0 +; RV32-LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX1-NEXT: ret ; ; RV64-LMULMAX1-LABEL: buildvec_mask_v32i1: @@ -351,6 +371,7 @@ ; RV64-LMULMAX1-NEXT: lui a0, 11 ; RV64-LMULMAX1-NEXT: addiw a0, a0, 1718 ; RV64-LMULMAX1-NEXT: vmv.s.x v8, a0 +; RV64-LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX1-NEXT: ret ; ; RV32-LMULMAX2-LABEL: buildvec_mask_v32i1: @@ -359,6 +380,7 @@ ; RV32-LMULMAX2-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-LMULMAX2-NEXT: vmv.s.x v0, a0 +; RV32-LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX2-NEXT: ret ; ; RV64-LMULMAX2-LABEL: buildvec_mask_v32i1: @@ -367,6 +389,7 @@ ; RV64-LMULMAX2-NEXT: addiw a0, a0, 1776 ; RV64-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-LMULMAX2-NEXT: vmv.s.x v0, a0 +; RV64-LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX2-NEXT: ret ; ; RV32-LMULMAX4-LABEL: buildvec_mask_v32i1: @@ -375,6 +398,7 @@ ; RV32-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX4-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0 +; RV32-LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX4-NEXT: ret ; ; RV64-LMULMAX4-LABEL: buildvec_mask_v32i1: @@ -383,6 +407,7 @@ ; RV64-LMULMAX4-NEXT: addiw a0, a0, 1776 ; RV64-LMULMAX4-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0 +; RV64-LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX4-NEXT: ret ; ; RV32-LMULMAX8-LABEL: buildvec_mask_v32i1: @@ -391,6 +416,7 @@ ; RV32-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX8-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0 +; RV32-LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX8-NEXT: ret ; ; RV64-LMULMAX8-LABEL: buildvec_mask_v32i1: @@ -399,6 +425,7 @@ ; RV64-LMULMAX8-NEXT: addiw a0, a0, 1776 ; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0 +; RV64-LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX8-NEXT: ret ret <32 x i1> } @@ -416,6 +443,7 @@ ; RV32-LMULMAX1-NEXT: addi a0, a0, 1718 ; RV32-LMULMAX1-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX1-NEXT: vmv1r.v v10, v8 +; RV32-LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX1-NEXT: ret ; ; RV64-LMULMAX1-LABEL: buildvec_mask_v64i1: @@ -430,6 +458,7 @@ ; RV64-LMULMAX1-NEXT: addiw a0, a0, 1718 ; RV64-LMULMAX1-NEXT: vmv.s.x v8, a0 ; RV64-LMULMAX1-NEXT: vmv1r.v v10, v8 +; RV64-LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX1-NEXT: ret ; ; RV32-LMULMAX2-LABEL: buildvec_mask_v64i1: @@ -441,6 +470,7 @@ ; RV32-LMULMAX2-NEXT: lui a0, 748388 ; RV32-LMULMAX2-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX2-NEXT: vmv.s.x v8, a0 +; RV32-LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX2-NEXT: ret ; ; RV64-LMULMAX2-LABEL: buildvec_mask_v64i1: @@ -452,6 +482,7 @@ ; RV64-LMULMAX2-NEXT: lui a0, 748388 ; RV64-LMULMAX2-NEXT: addiw a0, a0, -1793 ; RV64-LMULMAX2-NEXT: vmv.s.x v8, a0 +; RV64-LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX2-NEXT: ret ; ; RV32-LMULMAX4-LABEL: buildvec_mask_v64i1: @@ -465,6 +496,7 @@ ; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu ; RV32-LMULMAX4-NEXT: vslideup.vi v0, v25, 1 +; RV32-LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX4-NEXT: ret ; ; RV64-LMULMAX4-LABEL: buildvec_mask_v64i1: @@ -479,6 +511,7 @@ ; RV64-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV64-LMULMAX4-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0 +; RV64-LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX4-NEXT: ret ; ; RV32-LMULMAX8-LABEL: buildvec_mask_v64i1: @@ -492,6 +525,7 @@ ; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, mf2, tu, mu ; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 1 +; RV32-LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX8-NEXT: ret ; ; RV64-LMULMAX8-LABEL: buildvec_mask_v64i1: @@ -506,6 +540,7 @@ ; RV64-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0 +; RV64-LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX8-NEXT: ret ret <64 x i1> } @@ -531,6 +566,7 @@ ; RV32-LMULMAX1-NEXT: vmv1r.v v10, v8 ; RV32-LMULMAX1-NEXT: vmv1r.v v11, v0 ; RV32-LMULMAX1-NEXT: vmv1r.v v13, v9 +; RV32-LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX1-NEXT: ret ; ; RV64-LMULMAX1-LABEL: buildvec_mask_v128i1: @@ -553,6 +589,7 @@ ; RV64-LMULMAX1-NEXT: vmv1r.v v10, v8 ; RV64-LMULMAX1-NEXT: vmv1r.v v11, v0 ; RV64-LMULMAX1-NEXT: vmv1r.v v13, v9 +; RV64-LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX1-NEXT: ret ; ; RV32-LMULMAX2-LABEL: buildvec_mask_v128i1: @@ -570,6 +607,7 @@ ; RV32-LMULMAX2-NEXT: lui a0, 945060 ; RV32-LMULMAX2-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX2-NEXT: vmv.s.x v10, a0 +; RV32-LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX2-NEXT: ret ; ; RV64-LMULMAX2-LABEL: buildvec_mask_v128i1: @@ -587,6 +625,7 @@ ; RV64-LMULMAX2-NEXT: lui a0, 945060 ; RV64-LMULMAX2-NEXT: addiw a0, a0, -1793 ; RV64-LMULMAX2-NEXT: vmv.s.x v10, a0 +; RV64-LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX2-NEXT: ret ; ; RV32-LMULMAX4-LABEL: buildvec_mask_v128i1: @@ -609,6 +648,7 @@ ; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu ; RV32-LMULMAX4-NEXT: vslideup.vi v8, v25, 1 +; RV32-LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX4-NEXT: ret ; ; RV64-LMULMAX4-LABEL: buildvec_mask_v128i1: @@ -630,6 +670,7 @@ ; RV64-LMULMAX4-NEXT: slli a0, a0, 17 ; RV64-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0 +; RV64-LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX4-NEXT: ret ; ; RV32-LMULMAX8-LABEL: buildvec_mask_v128i1: @@ -655,6 +696,7 @@ ; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0 ; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 3 +; RV32-LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX8-NEXT: ret ; ; RV64-LMULMAX8-LABEL: buildvec_mask_v128i1: @@ -678,6 +720,7 @@ ; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV64-LMULMAX8-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV64-LMULMAX8-NEXT: vslideup.vi v0, v25, 1 +; RV64-LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX8-NEXT: ret ret <128 x i1> } @@ -703,6 +746,7 @@ ; RV32-LMULMAX1-NEXT: vmv1r.v v10, v8 ; RV32-LMULMAX1-NEXT: vmv1r.v v11, v0 ; RV32-LMULMAX1-NEXT: vmv1r.v v13, v9 +; RV32-LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX1-NEXT: ret ; ; RV64-LMULMAX1-LABEL: buildvec_mask_optsize_v128i1: @@ -725,6 +769,7 @@ ; RV64-LMULMAX1-NEXT: vmv1r.v v10, v8 ; RV64-LMULMAX1-NEXT: vmv1r.v v11, v0 ; RV64-LMULMAX1-NEXT: vmv1r.v v13, v9 +; RV64-LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX1-NEXT: ret ; ; RV32-LMULMAX2-LABEL: buildvec_mask_optsize_v128i1: @@ -742,6 +787,7 @@ ; RV32-LMULMAX2-NEXT: lui a0, 945060 ; RV32-LMULMAX2-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX2-NEXT: vmv.s.x v10, a0 +; RV32-LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX2-NEXT: ret ; ; RV64-LMULMAX2-LABEL: buildvec_mask_optsize_v128i1: @@ -759,6 +805,7 @@ ; RV64-LMULMAX2-NEXT: lui a0, 945060 ; RV64-LMULMAX2-NEXT: addiw a0, a0, -1793 ; RV64-LMULMAX2-NEXT: vmv.s.x v10, a0 +; RV64-LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX2-NEXT: ret ; ; RV32-LMULMAX4-LABEL: buildvec_mask_optsize_v128i1: @@ -771,6 +818,7 @@ ; RV32-LMULMAX4-NEXT: lui a0, %hi(.LCPI21_1) ; RV32-LMULMAX4-NEXT: addi a0, a0, %lo(.LCPI21_1) ; RV32-LMULMAX4-NEXT: vlm.v v8, (a0) +; RV32-LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX4-NEXT: ret ; ; RV64-LMULMAX4-LABEL: buildvec_mask_optsize_v128i1: @@ -792,6 +840,7 @@ ; RV64-LMULMAX4-NEXT: slli a0, a0, 17 ; RV64-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0 +; RV64-LMULMAX4-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX4-NEXT: ret ; ; RV32-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1: @@ -801,6 +850,7 @@ ; RV32-LMULMAX8-NEXT: addi a1, zero, 128 ; RV32-LMULMAX8-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; RV32-LMULMAX8-NEXT: vlm.v v0, (a0) +; RV32-LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; RV32-LMULMAX8-NEXT: ret ; ; RV64-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1: @@ -810,6 +860,7 @@ ; RV64-LMULMAX8-NEXT: addi a1, zero, 128 ; RV64-LMULMAX8-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; RV64-LMULMAX8-NEXT: vlm.v v0, (a0) +; RV64-LMULMAX8-NEXT: .cfi_def_cfa_offset 0 ; RV64-LMULMAX8-NEXT: ret ret <128 x i1> } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll @@ -18,6 +18,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <1 x i1>, <1 x i1>* %x store <1 x i1> %a, <1 x i1>* %y @@ -38,6 +39,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <2 x i1>, <2 x i1>* %x store <2 x i1> %a, <2 x i1>* %y @@ -58,6 +60,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <4 x i1>, <4 x i1>* %x store <4 x i1> %a, <4 x i1>* %y @@ -70,6 +73,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vlm.v v25, (a0) ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i1>, <8 x i1>* %x store <8 x i1> %a, <8 x i1>* %y @@ -82,6 +86,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vlm.v v25, (a0) ; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i1>, <16 x i1>* %x store <16 x i1> %a, <16 x i1>* %y @@ -95,18 +100,21 @@ ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vlm.v v25, (a0) ; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: load_store_v32i1: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: lw a0, 0(a0) ; LMULMAX1-RV32-NEXT: sw a0, 0(a1) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: load_store_v32i1: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: lw a0, 0(a0) ; LMULMAX1-RV64-NEXT: sw a0, 0(a1) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i1>, <32 x i1>* %x store <32 x i1> %a, <32 x i1>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll @@ -12,6 +12,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmand.mm v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i1>, <8 x i1>* %x %b = load <8 x i1>, <8 x i1>* %y @@ -28,6 +29,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmor.mm v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i1>, <16 x i1>* %x %b = load <16 x i1>, <16 x i1>* %y @@ -45,6 +47,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmxor.mm v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i1>, <32 x i1>* %x %b = load <32 x i1>, <32 x i1>* %y @@ -61,6 +64,7 @@ ; CHECK-NEXT: vlm.v v25, (a0) ; CHECK-NEXT: vmnand.mm v25, v25, v25 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %b = load <64 x i1>, <64 x i1>* %y @@ -77,6 +81,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmandnot.mm v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i1>, <8 x i1>* %x %b = load <8 x i1>, <8 x i1>* %y @@ -94,6 +99,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmornot.mm v25, v26, v25 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i1>, <16 x i1>* %x %b = load <16 x i1>, <16 x i1>* %y @@ -112,6 +118,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmxnor.mm v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i1>, <32 x i1>* %x %b = load <32 x i1>, <32 x i1>* %y @@ -129,6 +136,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmnand.mm v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <8 x i1>, <8 x i1>* %x %b = load <8 x i1>, <8 x i1>* %y @@ -146,6 +154,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmnor.mm v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <16 x i1>, <16 x i1>* %x %b = load <16 x i1>, <16 x i1>* %y @@ -164,6 +173,7 @@ ; CHECK-NEXT: vlm.v v26, (a1) ; CHECK-NEXT: vmxnor.mm v25, v25, v26 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = load <32 x i1>, <32 x i1>* %x %b = load <32 x i1>, <32 x i1>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll @@ -18,6 +18,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <1 x i1> , <1 x i1>* %x ret void @@ -37,6 +38,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <2 x i1> zeroinitializer, <2 x i1>* %x ret void @@ -58,6 +60,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <1 x i1> undef, i1 %y, i32 0 %b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer @@ -82,6 +85,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %c = icmp eq i32 %y, %z %a = insertelement <1 x i1> undef, i1 %c, i32 0 @@ -104,6 +108,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <4 x i1> , <4 x i1>* %x ret void @@ -125,6 +130,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmsne.vi v25, v26, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <4 x i1> undef, i1 %y, i32 0 %b = shufflevector <4 x i1> %a, <4 x i1> undef, <4 x i32> zeroinitializer @@ -138,6 +144,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vmclr.m v25 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <8 x i1> zeroinitializer, <8 x i1>* %x ret void @@ -151,6 +158,7 @@ ; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vmsne.vi v25, v25, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <8 x i1> undef, i1 %y, i32 0 %b = shufflevector <8 x i1> %a, <8 x i1> undef, <8 x i32> zeroinitializer @@ -164,6 +172,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vmset.m v25 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret store <16 x i1> , <16 x i1>* %x ret void @@ -177,6 +186,7 @@ ; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vmsne.vi v25, v25, 0 ; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %a = insertelement <16 x i1> undef, i1 %y, i32 0 %b = shufflevector <16 x i1> %a, <16 x i1> undef, <16 x i32> zeroinitializer @@ -191,6 +201,7 @@ ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX2-NEXT: vmclr.m v25 ; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_zeros_v32i1: @@ -200,6 +211,7 @@ ; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a0, 2 ; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_zeros_v32i1: @@ -209,6 +221,7 @@ ; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a0, 2 ; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret store <32 x i1> zeroinitializer, <32 x i1>* %x ret void @@ -223,6 +236,7 @@ ; LMULMAX2-NEXT: vmv.v.x v26, a1 ; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_v32i1: @@ -234,6 +248,7 @@ ; LMULMAX1-RV32-NEXT: addi a1, a0, 2 ; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) ; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_v32i1: @@ -245,6 +260,7 @@ ; LMULMAX1-RV64-NEXT: addi a1, a0, 2 ; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) ; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = insertelement <32 x i1> undef, i1 %y, i32 0 %b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> zeroinitializer @@ -261,6 +277,7 @@ ; LMULMAX2-NEXT: vmset.m v25 ; LMULMAX2-NEXT: vsm.v v25, (a1) ; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_ones_v64i1: @@ -274,6 +291,7 @@ ; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) ; LMULMAX1-RV32-NEXT: addi a0, a0, 2 ; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_ones_v64i1: @@ -287,6 +305,7 @@ ; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) ; LMULMAX1-RV64-NEXT: addi a0, a0, 2 ; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret store <64 x i1> , <64 x i1>* %x ret void @@ -303,6 +322,7 @@ ; LMULMAX2-NEXT: addi a1, a0, 4 ; LMULMAX2-NEXT: vsm.v v25, (a1) ; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_v64i1: @@ -318,6 +338,7 @@ ; LMULMAX1-RV32-NEXT: addi a1, a0, 2 ; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) ; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_v64i1: @@ -333,6 +354,7 @@ ; LMULMAX1-RV64-NEXT: addi a1, a0, 2 ; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) ; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-RV64-NEXT: ret %a = insertelement <64 x i1> undef, i1 %y, i32 0 %b = shufflevector <64 x i1> %a, <64 x i1> undef, <64 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -12,6 +12,7 @@ ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v1i8: @@ -19,6 +20,7 @@ ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <1 x i8> @llvm.masked.gather.v1i8.v1p0i8(<1 x i8*> %ptrs, i32 1, <1 x i1> %m, <1 x i8> %passthru) ret <1 x i8> %v @@ -32,6 +34,7 @@ ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i8: @@ -39,6 +42,7 @@ ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) ret <2 x i8> %v @@ -51,6 +55,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vsext.vf2 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i8_sextload_v2i16: @@ -59,6 +64,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vsext.vf2 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) %ev = sext <2 x i8> %v to <2 x i16> @@ -72,6 +78,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vzext.vf2 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i8_zextload_v2i16: @@ -80,6 +87,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vzext.vf2 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) %ev = zext <2 x i8> %v to <2 x i16> @@ -93,6 +101,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32-NEXT: vsext.vf4 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i8_sextload_v2i32: @@ -101,6 +110,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64-NEXT: vsext.vf4 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) %ev = sext <2 x i8> %v to <2 x i32> @@ -114,6 +124,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32-NEXT: vzext.vf4 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i8_zextload_v2i32: @@ -122,6 +133,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64-NEXT: vzext.vf4 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) %ev = zext <2 x i8> %v to <2 x i32> @@ -135,6 +147,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vsext.vf8 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i8_sextload_v2i64: @@ -143,6 +156,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vsext.vf8 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) %ev = sext <2 x i8> %v to <2 x i64> @@ -156,6 +170,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vzext.vf8 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i8_zextload_v2i64: @@ -164,6 +179,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vzext.vf8 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) %ev = zext <2 x i8> %v to <2 x i64> @@ -178,6 +194,7 @@ ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v4i8: @@ -185,6 +202,7 @@ ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> %m, <4 x i8> %passthru) ret <4 x i8> %v @@ -196,6 +214,7 @@ ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV32-NEXT: vluxei32.v v25, (zero), v8 ; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4i8: @@ -203,6 +222,7 @@ ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV64-NEXT: vluxei64.v v25, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -214,11 +234,13 @@ ; RV32-LABEL: mgather_falsemask_v4i8: ; RV32: # %bb.0: ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_falsemask_v4i8: ; RV64: # %bb.0: ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> zeroinitializer, <4 x i8> %passthru) ret <4 x i8> %v @@ -232,6 +254,7 @@ ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v8i8: @@ -239,6 +262,7 @@ ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> %ptrs, i32 1, <8 x i1> %m, <8 x i8> %passthru) ret <8 x i8> %v @@ -252,6 +276,7 @@ ; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8: @@ -261,6 +286,7 @@ ; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs %v = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> %ptrs, i32 1, <8 x i1> %m, <8 x i8> %passthru) @@ -275,6 +301,7 @@ ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v1i16: @@ -282,6 +309,7 @@ ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <1 x i16> @llvm.masked.gather.v1i16.v1p0i16(<1 x i16*> %ptrs, i32 2, <1 x i1> %m, <1 x i16> %passthru) ret <1 x i16> %v @@ -295,6 +323,7 @@ ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i16: @@ -302,6 +331,7 @@ ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru) ret <2 x i16> %v @@ -314,6 +344,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32-NEXT: vsext.vf2 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i16_sextload_v2i32: @@ -322,6 +353,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64-NEXT: vsext.vf2 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru) %ev = sext <2 x i16> %v to <2 x i32> @@ -335,6 +367,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32-NEXT: vzext.vf2 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i16_zextload_v2i32: @@ -343,6 +376,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64-NEXT: vzext.vf2 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru) %ev = zext <2 x i16> %v to <2 x i32> @@ -356,6 +390,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vsext.vf4 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i16_sextload_v2i64: @@ -364,6 +399,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vsext.vf4 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru) %ev = sext <2 x i16> %v to <2 x i64> @@ -377,6 +413,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vzext.vf4 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i16_zextload_v2i64: @@ -385,6 +422,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vzext.vf4 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru) %ev = zext <2 x i16> %v to <2 x i64> @@ -399,6 +437,7 @@ ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v4i16: @@ -406,6 +445,7 @@ ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> %m, <4 x i16> %passthru) ret <4 x i16> %v @@ -417,6 +457,7 @@ ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vluxei32.v v25, (zero), v8 ; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4i16: @@ -424,6 +465,7 @@ ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vluxei64.v v25, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -435,11 +477,13 @@ ; RV32-LABEL: mgather_falsemask_v4i16: ; RV32: # %bb.0: ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_falsemask_v4i16: ; RV64: # %bb.0: ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> zeroinitializer, <4 x i16> %passthru) ret <4 x i16> %v @@ -453,6 +497,7 @@ ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v8i16: @@ -460,6 +505,7 @@ ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru) ret <8 x i16> %v @@ -474,6 +520,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8i16: @@ -484,6 +531,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru) @@ -499,6 +547,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i16: @@ -509,6 +558,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -525,6 +575,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i16: @@ -535,6 +586,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -551,6 +603,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16: @@ -561,6 +614,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru) @@ -575,6 +629,7 @@ ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v1i32: @@ -582,6 +637,7 @@ ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <1 x i32> @llvm.masked.gather.v1i32.v1p0i32(<1 x i32*> %ptrs, i32 4, <1 x i1> %m, <1 x i32> %passthru) ret <1 x i32> %v @@ -595,6 +651,7 @@ ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i32: @@ -602,6 +659,7 @@ ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru) ret <2 x i32> %v @@ -614,6 +672,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vsext.vf2 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i32_sextload_v2i64: @@ -622,6 +681,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vsext.vf2 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru) %ev = sext <2 x i32> %v to <2 x i64> @@ -635,6 +695,7 @@ ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vzext.vf2 v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i32_zextload_v2i64: @@ -643,6 +704,7 @@ ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vzext.vf2 v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru) %ev = zext <2 x i32> %v to <2 x i64> @@ -657,6 +719,7 @@ ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v4i32: @@ -664,6 +727,7 @@ ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %m, <4 x i32> %passthru) ret <4 x i32> %v @@ -674,6 +738,7 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vluxei32.v v8, (zero), v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4i32: @@ -681,6 +746,7 @@ ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vluxei64.v v25, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -692,11 +758,13 @@ ; RV32-LABEL: mgather_falsemask_v4i32: ; RV32: # %bb.0: ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_falsemask_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> zeroinitializer, <4 x i32> %passthru) ret <4 x i32> %v @@ -710,6 +778,7 @@ ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v8i32: @@ -717,6 +786,7 @@ ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t ; RV64-NEXT: vmv2r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru) ret <8 x i32> %v @@ -730,6 +800,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8i32: @@ -740,6 +811,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru) @@ -754,6 +826,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i32: @@ -764,6 +837,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -779,6 +853,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i32: @@ -789,6 +864,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -804,6 +880,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16_v8i32: @@ -814,6 +891,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru) @@ -828,6 +906,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8i32: @@ -838,6 +917,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -853,6 +933,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8i32: @@ -863,6 +944,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -877,6 +959,7 @@ ; RV32-NEXT: vsll.vi v26, v8, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i32: @@ -887,6 +970,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru) @@ -901,6 +985,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v1i64: @@ -908,6 +993,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> %ptrs, i32 8, <1 x i1> %m, <1 x i64> %passthru) ret <1 x i64> %v @@ -921,6 +1007,7 @@ ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i64: @@ -928,6 +1015,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> %ptrs, i32 8, <2 x i1> %m, <2 x i64> %passthru) ret <2 x i64> %v @@ -941,6 +1029,7 @@ ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v4i64: @@ -948,6 +1037,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> %ptrs, i32 8, <4 x i1> %m, <4 x i64> %passthru) ret <4 x i64> %v @@ -959,12 +1049,14 @@ ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vluxei32.v v26, (zero), v8 ; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vluxei64.v v8, (zero), v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -976,11 +1068,13 @@ ; RV32-LABEL: mgather_falsemask_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_falsemask_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> %ptrs, i32 8, <4 x i1> zeroinitializer, <4 x i64> %passthru) ret <4 x i64> %v @@ -994,6 +1088,7 @@ ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v8i64: @@ -1001,6 +1096,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru) ret <8 x i64> %v @@ -1015,6 +1111,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8i64: @@ -1024,6 +1121,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru) @@ -1038,6 +1136,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i64: @@ -1047,6 +1146,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1062,6 +1162,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i64: @@ -1071,6 +1172,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1087,6 +1189,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16_v8i64: @@ -1096,6 +1199,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru) @@ -1110,6 +1214,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8i64: @@ -1119,6 +1224,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1134,6 +1240,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8i64: @@ -1143,6 +1250,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1158,6 +1266,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i32_v8i64: @@ -1167,6 +1276,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru) @@ -1181,6 +1291,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i32_v8i64: @@ -1190,6 +1301,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1205,6 +1317,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i32_v8i64: @@ -1214,6 +1327,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1228,6 +1342,7 @@ ; RV32-NEXT: vsll.vi v28, v8, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i64: @@ -1236,6 +1351,7 @@ ; RV64-NEXT: vsll.vi v28, v8, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru) @@ -1250,6 +1366,7 @@ ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v1f16: @@ -1257,6 +1374,7 @@ ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <1 x half> @llvm.masked.gather.v1f16.v1p0f16(<1 x half*> %ptrs, i32 2, <1 x i1> %m, <1 x half> %passthru) ret <1 x half> %v @@ -1270,6 +1388,7 @@ ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2f16: @@ -1277,6 +1396,7 @@ ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x half> @llvm.masked.gather.v2f16.v2p0f16(<2 x half*> %ptrs, i32 2, <2 x i1> %m, <2 x half> %passthru) ret <2 x half> %v @@ -1290,6 +1410,7 @@ ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v4f16: @@ -1297,6 +1418,7 @@ ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*> %ptrs, i32 2, <4 x i1> %m, <4 x half> %passthru) ret <4 x half> %v @@ -1308,6 +1430,7 @@ ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vluxei32.v v25, (zero), v8 ; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4f16: @@ -1315,6 +1438,7 @@ ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vluxei64.v v25, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1326,11 +1450,13 @@ ; RV32-LABEL: mgather_falsemask_v4f16: ; RV32: # %bb.0: ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_falsemask_v4f16: ; RV64: # %bb.0: ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*> %ptrs, i32 2, <4 x i1> zeroinitializer, <4 x half> %passthru) ret <4 x half> %v @@ -1344,6 +1470,7 @@ ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v8f16: @@ -1351,6 +1478,7 @@ ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru) ret <8 x half> %v @@ -1365,6 +1493,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8f16: @@ -1375,6 +1504,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru) @@ -1390,6 +1520,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f16: @@ -1400,6 +1531,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1416,6 +1548,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f16: @@ -1426,6 +1559,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1442,6 +1576,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8f16: @@ -1452,6 +1587,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru) @@ -1466,6 +1602,7 @@ ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v1f32: @@ -1473,6 +1610,7 @@ ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <1 x float> @llvm.masked.gather.v1f32.v1p0f32(<1 x float*> %ptrs, i32 4, <1 x i1> %m, <1 x float> %passthru) ret <1 x float> %v @@ -1486,6 +1624,7 @@ ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2f32: @@ -1493,6 +1632,7 @@ ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> %ptrs, i32 4, <2 x i1> %m, <2 x float> %passthru) ret <2 x float> %v @@ -1506,6 +1646,7 @@ ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v4f32: @@ -1513,6 +1654,7 @@ ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> %m, <4 x float> %passthru) ret <4 x float> %v @@ -1523,6 +1665,7 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vluxei32.v v8, (zero), v8 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4f32: @@ -1530,6 +1673,7 @@ ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vluxei64.v v25, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1541,11 +1685,13 @@ ; RV32-LABEL: mgather_falsemask_v4f32: ; RV32: # %bb.0: ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_falsemask_v4f32: ; RV64: # %bb.0: ; RV64-NEXT: vmv1r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> zeroinitializer, <4 x float> %passthru) ret <4 x float> %v @@ -1559,6 +1705,7 @@ ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v8f32: @@ -1566,6 +1713,7 @@ ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t ; RV64-NEXT: vmv2r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru) ret <8 x float> %v @@ -1579,6 +1727,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8f32: @@ -1589,6 +1738,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru) @@ -1603,6 +1753,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f32: @@ -1613,6 +1764,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1628,6 +1780,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f32: @@ -1638,6 +1791,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1653,6 +1807,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16_v8f32: @@ -1663,6 +1818,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru) @@ -1677,6 +1833,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8f32: @@ -1687,6 +1844,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1702,6 +1860,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8f32: @@ -1712,6 +1871,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1726,6 +1886,7 @@ ; RV32-NEXT: vsll.vi v26, v8, 2 ; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8f32: @@ -1736,6 +1897,7 @@ ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru) @@ -1750,6 +1912,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v1f64: @@ -1757,6 +1920,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> %ptrs, i32 8, <1 x i1> %m, <1 x double> %passthru) ret <1 x double> %v @@ -1770,6 +1934,7 @@ ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2f64: @@ -1777,6 +1942,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 8, <2 x i1> %m, <2 x double> %passthru) ret <2 x double> %v @@ -1790,6 +1956,7 @@ ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v4f64: @@ -1797,6 +1964,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> %ptrs, i32 8, <4 x i1> %m, <4 x double> %passthru) ret <4 x double> %v @@ -1808,12 +1976,14 @@ ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vluxei32.v v26, (zero), v8 ; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vluxei64.v v8, (zero), v8 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1825,11 +1995,13 @@ ; RV32-LABEL: mgather_falsemask_v4f64: ; RV32: # %bb.0: ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_falsemask_v4f64: ; RV64: # %bb.0: ; RV64-NEXT: vmv2r.v v8, v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> %ptrs, i32 8, <4 x i1> zeroinitializer, <4 x double> %passthru) ret <4 x double> %v @@ -1843,6 +2015,7 @@ ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v8f64: @@ -1850,6 +2023,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru) ret <8 x double> %v @@ -1864,6 +2038,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8f64: @@ -1873,6 +2048,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru) @@ -1887,6 +2063,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f64: @@ -1896,6 +2073,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1911,6 +2089,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f64: @@ -1920,6 +2099,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1936,6 +2116,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16_v8f64: @@ -1945,6 +2126,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru) @@ -1959,6 +2141,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8f64: @@ -1968,6 +2151,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1983,6 +2167,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8f64: @@ -1992,6 +2177,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -2007,6 +2193,7 @@ ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i32_v8f64: @@ -2016,6 +2203,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru) @@ -2030,6 +2218,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i32_v8f64: @@ -2039,6 +2228,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -2054,6 +2244,7 @@ ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i32_v8f64: @@ -2063,6 +2254,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -2077,6 +2269,7 @@ ; RV32-NEXT: vsll.vi v28, v8, 3 ; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV32-NEXT: vmv4r.v v8, v12 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8f64: @@ -2085,6 +2278,7 @@ ; RV64-NEXT: vsll.vi v28, v8, 3 ; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t ; RV64-NEXT: vmv4r.v v8, v12 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru) @@ -2101,6 +2295,7 @@ ; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (a0), v28, v0.t ; RV32-NEXT: vmv1r.v v8, v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v16i8: @@ -2110,6 +2305,7 @@ ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vluxei64.v v9, (a0), v16, v0.t ; RV64-NEXT: vmv1r.v v8, v9 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <16 x i8> %idxs %v = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> %ptrs, i32 2, <16 x i1> %m, <16 x i8> %passthru) @@ -2127,6 +2323,7 @@ ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t ; RV32-NEXT: vmv2r.v v8, v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v32i8: @@ -2153,6 +2350,7 @@ ; RV64-NEXT: vslideup.vi v8, v10, 0 ; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; RV64-NEXT: vslideup.vi v8, v26, 16 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs %v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll @@ -11,12 +11,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v1i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v1i8.v1p0i8(<1 x i8> %val, <1 x i8*> %ptrs, i32 1, <1 x i1> %m) ret void @@ -29,12 +31,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %val, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) ret void @@ -46,6 +50,7 @@ ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vnsrl.wi v25, v8, 0 ; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i16_truncstore_v2i8: @@ -53,6 +58,7 @@ ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vnsrl.wi v25, v8, 0 ; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %tval = trunc <2 x i16> %val to <2 x i8> call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) @@ -67,6 +73,7 @@ ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32-NEXT: vnsrl.wi v25, v25, 0 ; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i32_truncstore_v2i8: @@ -76,6 +83,7 @@ ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64-NEXT: vnsrl.wi v25, v25, 0 ; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %tval = trunc <2 x i32> %val to <2 x i8> call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) @@ -92,6 +100,7 @@ ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32-NEXT: vnsrl.wi v25, v25, 0 ; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i64_truncstore_v2i8: @@ -103,6 +112,7 @@ ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64-NEXT: vnsrl.wi v25, v25, 0 ; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i8> call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) @@ -116,12 +126,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v4i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8> %val, <4 x i8*> %ptrs, i32 1, <4 x i1> %m) ret void @@ -132,12 +144,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_truemask_v4i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -148,10 +162,12 @@ define void @mscatter_falsemask_v4i8(<4 x i8> %val, <4 x i8*> %ptrs) { ; RV32-LABEL: mscatter_falsemask_v4i8: ; RV32: # %bb.0: +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_falsemask_v4i8: ; RV64: # %bb.0: +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8> %val, <4 x i8*> %ptrs, i32 1, <4 x i1> zeroinitializer) ret void @@ -164,12 +180,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v8i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v12, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> %val, <8 x i8*> %ptrs, i32 1, <8 x i1> %m) ret void @@ -182,6 +200,7 @@ ; RV32-NEXT: vsext.vf4 v26, v9 ; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8: @@ -190,6 +209,7 @@ ; RV64-NEXT: vsext.vf8 v28, v9 ; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> %val, <8 x i8*> %ptrs, i32 1, <8 x i1> %m) @@ -203,12 +223,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v1i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v1i16.v1p0i16(<1 x i16> %val, <1 x i16*> %ptrs, i32 2, <1 x i1> %m) ret void @@ -221,12 +243,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %val, <2 x i16*> %ptrs, i32 2, <2 x i1> %m) ret void @@ -238,6 +262,7 @@ ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vnsrl.wi v25, v8, 0 ; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i32_truncstore_v2i16: @@ -245,6 +270,7 @@ ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vnsrl.wi v25, v8, 0 ; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %tval = trunc <2 x i32> %val to <2 x i16> call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m) @@ -259,6 +285,7 @@ ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vnsrl.wi v25, v25, 0 ; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i64_truncstore_v2i16: @@ -268,6 +295,7 @@ ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vnsrl.wi v25, v25, 0 ; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i16> call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m) @@ -281,12 +309,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> %val, <4 x i16*> %ptrs, i32 2, <4 x i1> %m) ret void @@ -297,12 +327,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_truemask_v4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -313,10 +345,12 @@ define void @mscatter_falsemask_v4i16(<4 x i16> %val, <4 x i16*> %ptrs) { ; RV32-LABEL: mscatter_falsemask_v4i16: ; RV32: # %bb.0: +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_falsemask_v4i16: ; RV64: # %bb.0: +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> %val, <4 x i16*> %ptrs, i32 2, <4 x i1> zeroinitializer) ret void @@ -329,12 +363,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v12, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m) ret void @@ -348,6 +384,7 @@ ; RV32-NEXT: vadd.vv v26, v26, v26 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8i16: @@ -357,6 +394,7 @@ ; RV64-NEXT: vadd.vv v28, v28, v28 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m) @@ -371,6 +409,7 @@ ; RV32-NEXT: vadd.vv v26, v26, v26 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i16: @@ -380,6 +419,7 @@ ; RV64-NEXT: vadd.vv v28, v28, v28 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -395,6 +435,7 @@ ; RV32-NEXT: vadd.vv v26, v26, v26 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i16: @@ -404,6 +445,7 @@ ; RV64-NEXT: vadd.vv v28, v28, v28 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -419,6 +461,7 @@ ; RV32-NEXT: vadd.vv v26, v26, v26 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16: @@ -428,6 +471,7 @@ ; RV64-NEXT: vadd.vv v28, v28, v28 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m) @@ -441,12 +485,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v1i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v1i32.v1p0i32(<1 x i32> %val, <1 x i32*> %ptrs, i32 4, <1 x i1> %m) ret void @@ -459,12 +505,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %val, <2 x i32*> %ptrs, i32 4, <2 x i1> %m) ret void @@ -476,6 +524,7 @@ ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vnsrl.wi v25, v8, 0 ; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i64_truncstore_v2i32: @@ -483,6 +532,7 @@ ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vnsrl.wi v25, v8, 0 ; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i32> call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, i32 4, <2 x i1> %m) @@ -496,12 +546,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %val, <4 x i32*> %ptrs, i32 4, <4 x i1> %m) ret void @@ -512,12 +564,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_truemask_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -528,10 +582,12 @@ define void @mscatter_falsemask_v4i32(<4 x i32> %val, <4 x i32*> %ptrs) { ; RV32-LABEL: mscatter_falsemask_v4i32: ; RV32: # %bb.0: +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_falsemask_v4i32: ; RV64: # %bb.0: +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %val, <4 x i32*> %ptrs, i32 4, <4 x i1> zeroinitializer) ret void @@ -544,12 +600,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v12, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m) ret void @@ -562,6 +620,7 @@ ; RV32-NEXT: vsext.vf4 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8i32: @@ -571,6 +630,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m) @@ -584,6 +644,7 @@ ; RV32-NEXT: vsext.vf4 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i32: @@ -593,6 +654,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -607,6 +669,7 @@ ; RV32-NEXT: vzext.vf4 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i32: @@ -616,6 +679,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -630,6 +694,7 @@ ; RV32-NEXT: vsext.vf2 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16_v8i32: @@ -639,6 +704,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m) @@ -652,6 +718,7 @@ ; RV32-NEXT: vsext.vf2 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i32: @@ -661,6 +728,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -675,6 +743,7 @@ ; RV32-NEXT: vzext.vf2 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i32: @@ -684,6 +753,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -697,6 +767,7 @@ ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vsll.vi v26, v10, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i32: @@ -706,6 +777,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m) @@ -719,12 +791,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v1i64.v1p0i64(<1 x i64> %val, <1 x i64*> %ptrs, i32 8, <1 x i1> %m) ret void @@ -737,12 +811,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> %val, <2 x i64*> %ptrs, i32 8, <2 x i1> %m) ret void @@ -755,12 +831,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> %val, <4 x i64*> %ptrs, i32 8, <4 x i1> %m) ret void @@ -771,12 +849,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_truemask_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -787,10 +867,12 @@ define void @mscatter_falsemask_v4i64(<4 x i64> %val, <4 x i64*> %ptrs) { ; RV32-LABEL: mscatter_falsemask_v4i64: ; RV32: # %bb.0: +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_falsemask_v4i64: ; RV64: # %bb.0: +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> %val, <4 x i64*> %ptrs, i32 8, <4 x i1> zeroinitializer) ret void @@ -803,12 +885,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v12, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v12, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) ret void @@ -822,6 +906,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8i64: @@ -830,6 +915,7 @@ ; RV64-NEXT: vsext.vf8 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) @@ -843,6 +929,7 @@ ; RV32-NEXT: vsext.vf8 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i64: @@ -851,6 +938,7 @@ ; RV64-NEXT: vsext.vf8 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -865,6 +953,7 @@ ; RV32-NEXT: vzext.vf8 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i64: @@ -873,6 +962,7 @@ ; RV64-NEXT: vzext.vf8 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -888,6 +978,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16_v8i64: @@ -896,6 +987,7 @@ ; RV64-NEXT: vsext.vf4 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) @@ -909,6 +1001,7 @@ ; RV32-NEXT: vsext.vf4 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i64: @@ -917,6 +1010,7 @@ ; RV64-NEXT: vsext.vf4 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -931,6 +1025,7 @@ ; RV32-NEXT: vzext.vf4 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i64: @@ -939,6 +1034,7 @@ ; RV64-NEXT: vzext.vf4 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -953,6 +1049,7 @@ ; RV32-NEXT: vsll.vi v26, v12, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i32_v8i64: @@ -961,6 +1058,7 @@ ; RV64-NEXT: vsext.vf2 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) @@ -974,6 +1072,7 @@ ; RV32-NEXT: vsext.vf2 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8i64: @@ -982,6 +1081,7 @@ ; RV64-NEXT: vsext.vf2 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -996,6 +1096,7 @@ ; RV32-NEXT: vzext.vf2 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8i64: @@ -1004,6 +1105,7 @@ ; RV64-NEXT: vzext.vf2 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1017,6 +1119,7 @@ ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsll.vi v28, v12, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i64: @@ -1024,6 +1127,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsll.vi v28, v12, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) @@ -1037,12 +1141,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v1f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v1f16.v1p0f16(<1 x half> %val, <1 x half*> %ptrs, i32 2, <1 x i1> %m) ret void @@ -1055,12 +1161,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v2f16.v2p0f16(<2 x half> %val, <2 x half*> %ptrs, i32 2, <2 x i1> %m) ret void @@ -1073,12 +1181,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4f16.v4p0f16(<4 x half> %val, <4 x half*> %ptrs, i32 2, <4 x i1> %m) ret void @@ -1089,12 +1199,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_truemask_v4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1105,10 +1217,12 @@ define void @mscatter_falsemask_v4f16(<4 x half> %val, <4 x half*> %ptrs) { ; RV32-LABEL: mscatter_falsemask_v4f16: ; RV32: # %bb.0: +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_falsemask_v4f16: ; RV64: # %bb.0: +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4f16.v4p0f16(<4 x half> %val, <4 x half*> %ptrs, i32 2, <4 x i1> zeroinitializer) ret void @@ -1121,12 +1235,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v12, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m) ret void @@ -1140,6 +1256,7 @@ ; RV32-NEXT: vadd.vv v26, v26, v26 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8f16: @@ -1149,6 +1266,7 @@ ; RV64-NEXT: vadd.vv v28, v28, v28 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m) @@ -1163,6 +1281,7 @@ ; RV32-NEXT: vadd.vv v26, v26, v26 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f16: @@ -1172,6 +1291,7 @@ ; RV64-NEXT: vadd.vv v28, v28, v28 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1187,6 +1307,7 @@ ; RV32-NEXT: vadd.vv v26, v26, v26 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f16: @@ -1196,6 +1317,7 @@ ; RV64-NEXT: vadd.vv v28, v28, v28 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1211,6 +1333,7 @@ ; RV32-NEXT: vadd.vv v26, v26, v26 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8f16: @@ -1220,6 +1343,7 @@ ; RV64-NEXT: vadd.vv v28, v28, v28 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m) @@ -1233,12 +1357,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v1f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v1f32.v1p0f32(<1 x float> %val, <1 x float*> %ptrs, i32 4, <1 x i1> %m) ret void @@ -1251,12 +1377,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> %val, <2 x float*> %ptrs, i32 4, <2 x i1> %m) ret void @@ -1269,12 +1397,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> %val, <4 x float*> %ptrs, i32 4, <4 x i1> %m) ret void @@ -1285,12 +1415,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_truemask_v4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1301,10 +1433,12 @@ define void @mscatter_falsemask_v4f32(<4 x float> %val, <4 x float*> %ptrs) { ; RV32-LABEL: mscatter_falsemask_v4f32: ; RV32: # %bb.0: +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_falsemask_v4f32: ; RV64: # %bb.0: +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> %val, <4 x float*> %ptrs, i32 4, <4 x i1> zeroinitializer) ret void @@ -1317,12 +1451,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v12, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m) ret void @@ -1335,6 +1471,7 @@ ; RV32-NEXT: vsext.vf4 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8f32: @@ -1344,6 +1481,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m) @@ -1357,6 +1495,7 @@ ; RV32-NEXT: vsext.vf4 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f32: @@ -1366,6 +1505,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1380,6 +1520,7 @@ ; RV32-NEXT: vzext.vf4 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f32: @@ -1389,6 +1530,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1403,6 +1545,7 @@ ; RV32-NEXT: vsext.vf2 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16_v8f32: @@ -1412,6 +1555,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m) @@ -1425,6 +1569,7 @@ ; RV32-NEXT: vsext.vf2 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f32: @@ -1434,6 +1579,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1448,6 +1594,7 @@ ; RV32-NEXT: vzext.vf2 v26, v10 ; RV32-NEXT: vsll.vi v26, v26, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f32: @@ -1457,6 +1604,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1470,6 +1618,7 @@ ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vsll.vi v26, v10, 2 ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8f32: @@ -1479,6 +1628,7 @@ ; RV64-NEXT: vsll.vi v28, v28, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m) @@ -1492,12 +1642,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v1f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v1f64.v1p0f64(<1 x double> %val, <1 x double*> %ptrs, i32 8, <1 x i1> %m) ret void @@ -1510,12 +1662,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> %val, <2 x double*> %ptrs, i32 8, <2 x i1> %m) ret void @@ -1528,12 +1682,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v4f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> %val, <4 x double*> %ptrs, i32 8, <4 x i1> %m) ret void @@ -1544,12 +1700,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v10 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_truemask_v4f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v10 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1560,10 +1718,12 @@ define void @mscatter_falsemask_v4f64(<4 x double> %val, <4 x double*> %ptrs) { ; RV32-LABEL: mscatter_falsemask_v4f64: ; RV32: # %bb.0: +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_falsemask_v4f64: ; RV64: # %bb.0: +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> %val, <4 x double*> %ptrs, i32 8, <4 x i1> zeroinitializer) ret void @@ -1576,12 +1736,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (zero), v12, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsoxei64.v v8, (zero), v12, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) ret void @@ -1595,6 +1757,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8f64: @@ -1603,6 +1766,7 @@ ; RV64-NEXT: vsext.vf8 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) @@ -1616,6 +1780,7 @@ ; RV32-NEXT: vsext.vf8 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f64: @@ -1624,6 +1789,7 @@ ; RV64-NEXT: vsext.vf8 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1638,6 +1804,7 @@ ; RV32-NEXT: vzext.vf8 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f64: @@ -1646,6 +1813,7 @@ ; RV64-NEXT: vzext.vf8 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1661,6 +1829,7 @@ ; RV32-NEXT: vsll.vi v26, v26, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16_v8f64: @@ -1669,6 +1838,7 @@ ; RV64-NEXT: vsext.vf4 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) @@ -1682,6 +1852,7 @@ ; RV32-NEXT: vsext.vf4 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f64: @@ -1690,6 +1861,7 @@ ; RV64-NEXT: vsext.vf4 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1704,6 +1876,7 @@ ; RV32-NEXT: vzext.vf4 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f64: @@ -1712,6 +1885,7 @@ ; RV64-NEXT: vzext.vf4 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1726,6 +1900,7 @@ ; RV32-NEXT: vsll.vi v26, v12, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i32_v8f64: @@ -1734,6 +1909,7 @@ ; RV64-NEXT: vsext.vf2 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) @@ -1747,6 +1923,7 @@ ; RV32-NEXT: vsext.vf2 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8f64: @@ -1755,6 +1932,7 @@ ; RV64-NEXT: vsext.vf2 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1769,6 +1947,7 @@ ; RV32-NEXT: vzext.vf2 v28, v12 ; RV32-NEXT: vsll.vi v28, v28, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8f64: @@ -1777,6 +1956,7 @@ ; RV64-NEXT: vzext.vf2 v28, v12 ; RV64-NEXT: vsll.vi v28, v28, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1790,6 +1970,7 @@ ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsll.vi v28, v12, 3 ; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8f64: @@ -1797,6 +1978,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsll.vi v28, v12, 3 ; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) @@ -1812,6 +1994,7 @@ ; RV32-NEXT: vsext.vf4 v28, v9 ; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v16i8: @@ -1820,6 +2003,7 @@ ; RV64-NEXT: vsext.vf8 v16, v9 ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <16 x i8> %idxs call void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8> %val, <16 x i8*> %ptrs, i32 1, <16 x i1> %m) @@ -1836,6 +2020,7 @@ ; RV32-NEXT: vsext.vf4 v16, v10 ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v32i8: @@ -1853,6 +2038,7 @@ ; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vsoxei64.v v26, (a0), v8, v0.t +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> %val, <32 x i8*> %ptrs, i32 1, <32 x i1> %m) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll @@ -14,6 +14,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl) ret half %r @@ -27,6 +28,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl) ret half %r @@ -42,6 +44,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl) ret half %r @@ -55,6 +58,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl) ret half %r @@ -70,6 +74,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl) ret float %r @@ -83,6 +88,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl) ret float %r @@ -98,6 +104,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl) ret float %r @@ -111,6 +118,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl) ret float %r @@ -126,6 +134,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl) ret double %r @@ -139,6 +148,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl) ret double %r @@ -154,6 +164,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl) ret double %r @@ -167,6 +178,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl) ret double %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll @@ -11,6 +11,7 @@ ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x half>, <1 x half>* %x %red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v) @@ -27,6 +28,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x half>, <1 x half>* %x %red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v) @@ -48,6 +50,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x half>, <2 x half>* %x %red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v) @@ -64,6 +67,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x half>, <2 x half>* %x %red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v) @@ -85,6 +89,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v) @@ -101,6 +106,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v) @@ -122,6 +128,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x half>, <8 x half>* %x %red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v) @@ -138,6 +145,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x half>, <8 x half>* %x %red = call half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v) @@ -159,6 +167,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x half>, <16 x half>* %x %red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v) @@ -175,6 +184,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x half>, <16 x half>* %x %red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v) @@ -197,6 +207,7 @@ ; RV32-NEXT: vfredsum.vs v25, v28, v25 ; RV32-NEXT: vfmv.f.s ft0, v25 ; RV32-NEXT: fadd.h fa0, fa0, ft0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_fadd_v32f16: @@ -212,6 +223,7 @@ ; RV64-NEXT: vfredsum.vs v25, v28, v25 ; RV64-NEXT: vfmv.f.s ft0, v25 ; RV64-NEXT: fadd.h fa0, fa0, ft0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x half>, <32 x half>* %x %red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v) @@ -229,6 +241,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v28, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x half>, <32 x half>* %x %red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v) @@ -251,6 +264,7 @@ ; RV32-NEXT: vfredsum.vs v25, v8, v25 ; RV32-NEXT: vfmv.f.s ft0, v25 ; RV32-NEXT: fadd.h fa0, fa0, ft0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_fadd_v64f16: @@ -266,6 +280,7 @@ ; RV64-NEXT: vfredsum.vs v25, v8, v25 ; RV64-NEXT: vfmv.f.s ft0, v25 ; RV64-NEXT: fadd.h fa0, fa0, ft0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <64 x half>, <64 x half>* %x %red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v) @@ -283,6 +298,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x half>, <64 x half>* %x %red = call half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v) @@ -308,6 +324,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x half>, <128 x half>* %x %red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v) @@ -332,6 +349,7 @@ ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x half>, <128 x half>* %x %red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v) @@ -347,6 +365,7 @@ ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x float>, <1 x float>* %x %red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v) @@ -363,6 +382,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x float>, <1 x float>* %x %red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v) @@ -384,6 +404,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x float>, <2 x float>* %x %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v) @@ -400,6 +421,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x float>, <2 x float>* %x %red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v) @@ -421,6 +443,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v) @@ -437,6 +460,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v) @@ -458,6 +482,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x float>, <8 x float>* %x %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v) @@ -474,6 +499,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x float>, <8 x float>* %x %red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v) @@ -495,6 +521,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v28, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x float>, <16 x float>* %x %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v) @@ -511,6 +538,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v28, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x float>, <16 x float>* %x %red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v) @@ -533,6 +561,7 @@ ; RV32-NEXT: vfredsum.vs v25, v8, v25 ; RV32-NEXT: vfmv.f.s ft0, v25 ; RV32-NEXT: fadd.s fa0, fa0, ft0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_fadd_v32f32: @@ -548,6 +577,7 @@ ; RV64-NEXT: vfredsum.vs v25, v8, v25 ; RV64-NEXT: vfmv.f.s ft0, v25 ; RV64-NEXT: fadd.s fa0, fa0, ft0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x float>, <32 x float>* %x %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v) @@ -565,6 +595,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x float>, <32 x float>* %x %red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v) @@ -590,6 +621,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x float>, <64 x float>* %x %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v) @@ -614,6 +646,7 @@ ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x float>, <64 x float>* %x %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v) @@ -629,6 +662,7 @@ ; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x double>, <1 x double>* %x %red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v) @@ -645,6 +679,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x double>, <1 x double>* %x %red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v) @@ -666,6 +701,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x double>, <2 x double>* %x %red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v) @@ -682,6 +718,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x double>, <2 x double>* %x %red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v) @@ -703,6 +740,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v) @@ -719,6 +757,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v) @@ -740,6 +779,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v28, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x double>, <8 x double>* %x %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v) @@ -756,6 +796,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v28, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x double>, <8 x double>* %x %red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v) @@ -777,6 +818,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x double>, <16 x double>* %x %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v) @@ -793,6 +835,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x double>, <16 x double>* %x %red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v) @@ -817,6 +860,7 @@ ; CHECK-NEXT: vfredsum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x double>, <32 x double>* %x %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v) @@ -840,6 +884,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vfredosum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x double>, <32 x double>* %x %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v) @@ -860,6 +905,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x half>, <2 x half>* %x %red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v) @@ -880,6 +926,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) @@ -898,6 +945,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) @@ -916,6 +964,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) @@ -940,6 +989,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x half>, <128 x half>* %x %red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v) @@ -960,6 +1010,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x float>, <2 x float>* %x %red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v) @@ -980,6 +1031,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) @@ -998,6 +1050,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) @@ -1016,6 +1069,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) @@ -1046,6 +1100,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x float>, <128 x float>* %x %red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v) @@ -1066,6 +1121,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x double>, <2 x double>* %x %red = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %v) @@ -1086,6 +1142,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) @@ -1104,6 +1161,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) @@ -1122,6 +1180,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) @@ -1145,6 +1204,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vfredmin.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x double>, <32 x double>* %x %red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v) @@ -1165,6 +1225,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x half>, <2 x half>* %x %red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v) @@ -1185,6 +1246,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) @@ -1203,6 +1265,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) @@ -1221,6 +1284,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) @@ -1245,6 +1309,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x half>, <128 x half>* %x %red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v) @@ -1265,6 +1330,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x float>, <2 x float>* %x %red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v) @@ -1285,6 +1351,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) @@ -1303,6 +1370,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) @@ -1321,6 +1389,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) @@ -1351,6 +1420,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x float>, <128 x float>* %x %red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v) @@ -1371,6 +1441,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x double>, <2 x double>* %x %red = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %v) @@ -1391,6 +1462,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) @@ -1409,6 +1481,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) @@ -1427,6 +1500,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) @@ -1450,6 +1524,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vfredmax.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x double>, <32 x double>* %x %red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll @@ -14,6 +14,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.add.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -30,6 +31,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.umax.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -45,6 +47,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.smax.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -61,6 +64,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.umin.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -76,6 +80,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.smin.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -91,6 +96,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.and.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -106,6 +112,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.or.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -121,6 +128,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.xor.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -136,6 +144,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.add.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -152,6 +161,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.umax.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -167,6 +177,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.smax.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -183,6 +194,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.umin.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -198,6 +210,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.smin.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -213,6 +226,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.and.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -228,6 +242,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.or.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -243,6 +258,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.xor.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -258,6 +274,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.add.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -276,6 +293,7 @@ ; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v2i16: @@ -288,6 +306,7 @@ ; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umax.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -303,6 +322,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smax.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -321,6 +341,7 @@ ; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v2i16: @@ -333,6 +354,7 @@ ; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umin.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -348,6 +370,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smin.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -363,6 +386,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.and.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -378,6 +402,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.or.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -393,6 +418,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.xor.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -408,6 +434,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.add.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -426,6 +453,7 @@ ; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v4i16: @@ -438,6 +466,7 @@ ; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umax.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -453,6 +482,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smax.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -471,6 +501,7 @@ ; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v4i16: @@ -483,6 +514,7 @@ ; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umin.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -498,6 +530,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smin.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -513,6 +546,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.and.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -528,6 +562,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.or.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -543,6 +578,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.xor.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -558,6 +594,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.add.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -573,6 +610,7 @@ ; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v2i32: @@ -584,6 +622,7 @@ ; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -599,6 +638,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -614,6 +654,7 @@ ; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v2i32: @@ -625,6 +666,7 @@ ; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -640,6 +682,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -655,6 +698,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.and.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -670,6 +714,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.or.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -685,6 +730,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.xor.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -700,6 +746,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.add.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -715,6 +762,7 @@ ; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v4i32: @@ -726,6 +774,7 @@ ; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -741,6 +790,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -756,6 +806,7 @@ ; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v4i32: @@ -767,6 +818,7 @@ ; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -782,6 +834,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -797,6 +850,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.and.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -812,6 +866,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.or.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -827,6 +882,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.xor.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -852,6 +908,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_add_v2i64: @@ -861,6 +918,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.add.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -886,6 +944,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v2i64: @@ -895,6 +954,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umax.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -920,6 +980,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smax_v2i64: @@ -929,6 +990,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smax.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -954,6 +1016,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v2i64: @@ -963,6 +1026,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umin.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -988,6 +1052,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smin_v2i64: @@ -997,6 +1062,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smin.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -1022,6 +1088,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_and_v2i64: @@ -1031,6 +1098,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vredand.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.and.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -1056,6 +1124,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_or_v2i64: @@ -1065,6 +1134,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vredor.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.or.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -1090,6 +1160,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_xor_v2i64: @@ -1099,6 +1170,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.xor.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -1124,6 +1196,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_add_v4i64: @@ -1133,6 +1206,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.add.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1158,6 +1232,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v4i64: @@ -1167,6 +1242,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umax.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1192,6 +1268,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smax_v4i64: @@ -1201,6 +1278,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smax.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1226,6 +1304,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v4i64: @@ -1235,6 +1314,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umin.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1260,6 +1340,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smin_v4i64: @@ -1269,6 +1350,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smin.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1294,6 +1376,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_and_v4i64: @@ -1303,6 +1386,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; RV64-NEXT: vredand.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.and.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1328,6 +1412,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_or_v4i64: @@ -1337,6 +1422,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; RV64-NEXT: vredor.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.or.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1362,6 +1448,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_xor_v4i64: @@ -1371,6 +1458,7 @@ ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.xor.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll @@ -10,6 +10,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %v) @@ -28,6 +29,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v) @@ -46,6 +48,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %v) @@ -64,6 +67,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v) @@ -82,6 +86,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %v) @@ -101,6 +106,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vredsum.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %v) @@ -120,6 +126,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vredsum.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %v) @@ -139,6 +146,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %v) @@ -161,6 +169,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v256i8(<256 x i8> %v) @@ -175,6 +184,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %v) @@ -193,6 +203,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %v) @@ -211,6 +222,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v) @@ -229,6 +241,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %v) @@ -247,6 +260,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vredsum.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %v) @@ -266,6 +280,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vredsum.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %v) @@ -285,6 +300,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %v) @@ -307,6 +323,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %v) @@ -321,6 +338,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %v) @@ -339,6 +357,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %v) @@ -357,6 +376,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vredsum.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v) @@ -375,6 +395,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vredsum.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v) @@ -393,6 +414,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vredsum.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v) @@ -412,6 +434,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %v) @@ -434,6 +457,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredsum.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %v) @@ -451,6 +475,7 @@ ; RV32-NEXT: vsrl.vx v26, v25, a0 ; RV32-NEXT: vmv.x.s a1, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v1i64: @@ -458,6 +483,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %v) @@ -480,6 +506,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v2i64: @@ -491,6 +518,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vredsum.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v) @@ -513,6 +541,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v4i64: @@ -524,6 +553,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vredsum.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v) @@ -546,6 +576,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v8i64: @@ -557,6 +588,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vredsum.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %v) @@ -579,6 +611,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v16i64: @@ -590,6 +623,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredsum.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %v) @@ -615,6 +649,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v32i64: @@ -629,6 +664,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredsum.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %v) @@ -694,6 +730,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %v) @@ -712,6 +749,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v) @@ -730,6 +768,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v) @@ -748,6 +787,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v) @@ -766,6 +806,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %v) @@ -785,6 +826,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vredand.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v) @@ -804,6 +846,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vredand.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> %v) @@ -823,6 +866,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredand.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %v) @@ -845,6 +889,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredand.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %v) @@ -859,6 +904,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %v) @@ -877,6 +923,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v) @@ -895,6 +942,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v) @@ -913,6 +961,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %v) @@ -931,6 +980,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vredand.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v) @@ -950,6 +1000,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vredand.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> %v) @@ -969,6 +1020,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredand.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> %v) @@ -991,6 +1043,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredand.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %v) @@ -1005,6 +1058,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %v) @@ -1023,6 +1077,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v) @@ -1041,6 +1096,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vredand.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %v) @@ -1059,6 +1115,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vredand.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v) @@ -1077,6 +1134,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vredand.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %v) @@ -1096,6 +1154,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredand.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> %v) @@ -1118,6 +1177,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredand.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %v) @@ -1135,6 +1195,7 @@ ; RV32-NEXT: vsrl.vx v26, v25, a0 ; RV32-NEXT: vmv.x.s a1, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v1i64: @@ -1142,6 +1203,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %v) @@ -1164,6 +1226,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v2i64: @@ -1175,6 +1238,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vredand.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %v) @@ -1197,6 +1261,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v4i64: @@ -1208,6 +1273,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vredand.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v) @@ -1230,6 +1296,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v8i64: @@ -1241,6 +1308,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vredand.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %v) @@ -1263,6 +1331,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v16i64: @@ -1274,6 +1343,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredand.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %v) @@ -1299,6 +1369,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v32i64: @@ -1313,6 +1384,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredand.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %v) @@ -1378,6 +1450,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %v) @@ -1396,6 +1469,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> %v) @@ -1414,6 +1488,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %v) @@ -1432,6 +1507,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %v) @@ -1450,6 +1526,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %v) @@ -1469,6 +1546,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vredor.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %v) @@ -1488,6 +1566,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vredor.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> %v) @@ -1507,6 +1586,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %v) @@ -1529,6 +1609,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %v) @@ -1543,6 +1624,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v1i16(<1 x i16> %v) @@ -1561,6 +1643,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %v) @@ -1579,6 +1662,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v) @@ -1597,6 +1681,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %v) @@ -1615,6 +1700,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vredor.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %v) @@ -1634,6 +1720,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vredor.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> %v) @@ -1653,6 +1740,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> %v) @@ -1675,6 +1763,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %v) @@ -1689,6 +1778,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v1i32(<1 x i32> %v) @@ -1707,6 +1797,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %v) @@ -1725,6 +1816,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vredor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %v) @@ -1743,6 +1835,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vredor.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v) @@ -1761,6 +1854,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vredor.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %v) @@ -1780,6 +1874,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> %v) @@ -1802,6 +1897,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %v) @@ -1819,6 +1915,7 @@ ; RV32-NEXT: vsrl.vx v26, v25, a0 ; RV32-NEXT: vmv.x.s a1, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v1i64: @@ -1826,6 +1923,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %v) @@ -1848,6 +1946,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v2i64: @@ -1859,6 +1958,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vredor.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %v) @@ -1881,6 +1981,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v4i64: @@ -1892,6 +1993,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vredor.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v) @@ -1914,6 +2016,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v8i64: @@ -1925,6 +2028,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vredor.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %v) @@ -1947,6 +2051,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v16i64: @@ -1958,6 +2063,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredor.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %v) @@ -1983,6 +2089,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v32i64: @@ -1997,6 +2104,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredor.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %v) @@ -2062,6 +2170,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v1i8(<1 x i8> %v) @@ -2080,6 +2189,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> %v) @@ -2098,6 +2208,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %v) @@ -2116,6 +2227,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %v) @@ -2134,6 +2246,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %v) @@ -2153,6 +2266,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vredxor.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %v) @@ -2172,6 +2286,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vredxor.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> %v) @@ -2191,6 +2306,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %v) @@ -2213,6 +2329,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %v) @@ -2227,6 +2344,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v1i16(<1 x i16> %v) @@ -2245,6 +2363,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %v) @@ -2263,6 +2382,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %v) @@ -2281,6 +2401,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %v) @@ -2299,6 +2420,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vredxor.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %v) @@ -2318,6 +2440,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vredxor.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> %v) @@ -2337,6 +2460,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> %v) @@ -2359,6 +2483,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %v) @@ -2373,6 +2498,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v1i32(<1 x i32> %v) @@ -2391,6 +2517,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %v) @@ -2409,6 +2536,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vredxor.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %v) @@ -2427,6 +2555,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vredxor.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %v) @@ -2445,6 +2574,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vredxor.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %v) @@ -2464,6 +2594,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> %v) @@ -2486,6 +2617,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredxor.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %v) @@ -2503,6 +2635,7 @@ ; RV32-NEXT: vsrl.vx v26, v25, a0 ; RV32-NEXT: vmv.x.s a1, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v1i64: @@ -2510,6 +2643,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %v) @@ -2532,6 +2666,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v2i64: @@ -2543,6 +2678,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vredxor.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %v) @@ -2565,6 +2701,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v4i64: @@ -2576,6 +2713,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vredxor.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v) @@ -2598,6 +2736,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v8i64: @@ -2609,6 +2748,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vredxor.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %v) @@ -2631,6 +2771,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v16i64: @@ -2642,6 +2783,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredxor.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %v) @@ -2667,6 +2809,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v32i64: @@ -2681,6 +2824,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredxor.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %v) @@ -2746,6 +2890,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v1i8(<1 x i8> %v) @@ -2765,6 +2910,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vredmin.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %v) @@ -2784,6 +2930,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vredmin.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %v) @@ -2803,6 +2950,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vredmin.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v) @@ -2822,6 +2970,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vredmin.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %v) @@ -2842,6 +2991,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vredmin.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %v) @@ -2862,6 +3012,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vredmin.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> %v) @@ -2882,6 +3033,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredmin.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %v) @@ -2905,6 +3057,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredmin.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v256i8(<256 x i8> %v) @@ -2919,6 +3072,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v1i16(<1 x i16> %v) @@ -2939,6 +3093,7 @@ ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vredmin.vs v25, v25, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v2i16: @@ -2952,6 +3107,7 @@ ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vredmin.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %v) @@ -2972,6 +3128,7 @@ ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: vredmin.vs v25, v25, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v4i16: @@ -2985,6 +3142,7 @@ ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64-NEXT: vredmin.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v) @@ -3005,6 +3163,7 @@ ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV32-NEXT: vredmin.vs v25, v25, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v8i16: @@ -3018,6 +3177,7 @@ ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV64-NEXT: vredmin.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %v) @@ -3038,6 +3198,7 @@ ; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; RV32-NEXT: vredmin.vs v25, v26, v25 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v16i16: @@ -3051,6 +3212,7 @@ ; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; RV64-NEXT: vredmin.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %v) @@ -3072,6 +3234,7 @@ ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; RV32-NEXT: vredmin.vs v25, v28, v25 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v32i16: @@ -3086,6 +3249,7 @@ ; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; RV64-NEXT: vredmin.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> %v) @@ -3107,6 +3271,7 @@ ; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; RV32-NEXT: vredmin.vs v25, v8, v25 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v64i16: @@ -3121,6 +3286,7 @@ ; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; RV64-NEXT: vredmin.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> %v) @@ -3145,6 +3311,7 @@ ; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; RV32-NEXT: vredmin.vs v25, v8, v25 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v128i16: @@ -3162,6 +3329,7 @@ ; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; RV64-NEXT: vredmin.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v128i16(<128 x i16> %v) @@ -3176,6 +3344,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v1i32(<1 x i32> %v) @@ -3196,6 +3365,7 @@ ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vredmin.vs v25, v25, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v2i32: @@ -3209,6 +3379,7 @@ ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vredmin.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %v) @@ -3229,6 +3400,7 @@ ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vredmin.vs v25, v25, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v4i32: @@ -3242,6 +3414,7 @@ ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vredmin.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v) @@ -3262,6 +3435,7 @@ ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vredmin.vs v25, v26, v25 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v8i32: @@ -3275,6 +3449,7 @@ ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vredmin.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v) @@ -3295,6 +3470,7 @@ ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV32-NEXT: vredmin.vs v25, v28, v25 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v16i32: @@ -3308,6 +3484,7 @@ ; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV64-NEXT: vredmin.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %v) @@ -3329,6 +3506,7 @@ ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; RV32-NEXT: vredmin.vs v25, v8, v25 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v32i32: @@ -3343,6 +3521,7 @@ ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; RV64-NEXT: vredmin.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> %v) @@ -3367,6 +3546,7 @@ ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; RV32-NEXT: vredmin.vs v25, v8, v25 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v64i32: @@ -3384,6 +3564,7 @@ ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; RV64-NEXT: vredmin.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v64i32(<64 x i32> %v) @@ -3401,6 +3582,7 @@ ; RV32-NEXT: vsrl.vx v26, v25, a0 ; RV32-NEXT: vmv.x.s a1, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v1i64: @@ -3408,6 +3590,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> %v) @@ -3439,6 +3622,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v2i64: @@ -3452,6 +3636,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vredmin.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %v) @@ -3483,6 +3668,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v4i64: @@ -3496,6 +3682,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vredmin.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v) @@ -3527,6 +3714,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v8i64: @@ -3540,6 +3728,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vredmin.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %v) @@ -3571,6 +3760,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v16i64: @@ -3584,6 +3774,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredmin.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> %v) @@ -3618,6 +3809,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v32i64: @@ -3634,6 +3826,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredmin.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v32i64(<32 x i64> %v) @@ -3709,6 +3902,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v1i8(<1 x i8> %v) @@ -3728,6 +3922,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %v) @@ -3747,6 +3942,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %v) @@ -3766,6 +3962,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v) @@ -3785,6 +3982,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %v) @@ -3805,6 +4003,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vredmax.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %v) @@ -3825,6 +4024,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vredmax.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> %v) @@ -3845,6 +4045,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %v) @@ -3868,6 +4069,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v256i8(<256 x i8> %v) @@ -3882,6 +4084,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v1i16(<1 x i16> %v) @@ -3901,6 +4104,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %v) @@ -3920,6 +4124,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v) @@ -3939,6 +4144,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %v) @@ -3958,6 +4164,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vredmax.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v) @@ -3978,6 +4185,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vredmax.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> %v) @@ -3998,6 +4206,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> %v) @@ -4021,6 +4230,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v128i16(<128 x i16> %v) @@ -4035,6 +4245,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v1i32(<1 x i32> %v) @@ -4054,6 +4265,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %v) @@ -4073,6 +4285,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vredmax.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v) @@ -4092,6 +4305,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vredmax.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v) @@ -4111,6 +4325,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vredmax.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %v) @@ -4131,6 +4346,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> %v) @@ -4154,6 +4370,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v64i32(<64 x i32> %v) @@ -4171,6 +4388,7 @@ ; RV32-NEXT: vsrl.vx v26, v25, a0 ; RV32-NEXT: vmv.x.s a1, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v1i64: @@ -4178,6 +4396,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> %v) @@ -4207,6 +4426,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v2i64: @@ -4220,6 +4440,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vredmax.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %v) @@ -4249,6 +4470,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v4i64: @@ -4262,6 +4484,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vredmax.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v) @@ -4291,6 +4514,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v8i64: @@ -4304,6 +4528,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vredmax.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %v) @@ -4333,6 +4558,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v16i64: @@ -4346,6 +4572,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredmax.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> %v) @@ -4378,6 +4605,7 @@ ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v32i64: @@ -4394,6 +4622,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredmax.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v32i64(<32 x i64> %v) @@ -4467,6 +4696,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v1i8(<1 x i8> %v) @@ -4485,6 +4715,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> %v) @@ -4503,6 +4734,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> %v) @@ -4521,6 +4753,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v) @@ -4539,6 +4772,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %v) @@ -4558,6 +4792,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vredminu.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %v) @@ -4577,6 +4812,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vredminu.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> %v) @@ -4596,6 +4832,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredminu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %v) @@ -4618,6 +4855,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredminu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v256i8(<256 x i8> %v) @@ -4632,6 +4870,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v1i16(<1 x i16> %v) @@ -4650,6 +4889,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> %v) @@ -4668,6 +4908,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v) @@ -4686,6 +4927,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %v) @@ -4704,6 +4946,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vredminu.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %v) @@ -4723,6 +4966,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vredminu.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> %v) @@ -4742,6 +4986,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredminu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> %v) @@ -4764,6 +5009,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredminu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v128i16(<128 x i16> %v) @@ -4778,6 +5024,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v1i32(<1 x i32> %v) @@ -4796,6 +5043,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %v) @@ -4814,6 +5062,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vredminu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %v) @@ -4832,6 +5081,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vredminu.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v) @@ -4850,6 +5100,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vredminu.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %v) @@ -4869,6 +5120,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredminu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> %v) @@ -4891,6 +5143,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredminu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v64i32(<64 x i32> %v) @@ -4908,6 +5161,7 @@ ; RV32-NEXT: vsrl.vx v26, v25, a0 ; RV32-NEXT: vmv.x.s a1, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v1i64: @@ -4915,6 +5169,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> %v) @@ -4937,6 +5192,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v2i64: @@ -4948,6 +5204,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vredminu.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %v) @@ -4970,6 +5227,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v4i64: @@ -4981,6 +5239,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vredminu.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v) @@ -5003,6 +5262,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v8i64: @@ -5014,6 +5274,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vredminu.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %v) @@ -5036,6 +5297,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v16i64: @@ -5047,6 +5309,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredminu.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> %v) @@ -5072,6 +5335,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v32i64: @@ -5086,6 +5350,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredminu.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v32i64(<32 x i64> %v) @@ -5151,6 +5416,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %v) @@ -5169,6 +5435,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %v) @@ -5187,6 +5454,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %v) @@ -5205,6 +5473,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v) @@ -5223,6 +5492,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %v) @@ -5242,6 +5512,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %v) @@ -5261,6 +5532,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> %v) @@ -5280,6 +5552,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %v) @@ -5302,6 +5575,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v256i8(<256 x i8> %v) @@ -5316,6 +5590,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %v) @@ -5334,6 +5609,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %v) @@ -5352,6 +5628,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v) @@ -5370,6 +5647,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %v) @@ -5388,6 +5666,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %v) @@ -5407,6 +5686,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> %v) @@ -5426,6 +5706,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> %v) @@ -5448,6 +5729,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v128i16(<128 x i16> %v) @@ -5462,6 +5744,7 @@ ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %v) @@ -5480,6 +5763,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %v) @@ -5498,6 +5782,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v25, v26 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %v) @@ -5516,6 +5801,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v26, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %v) @@ -5534,6 +5820,7 @@ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v28, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %v) @@ -5553,6 +5840,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> %v) @@ -5575,6 +5863,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vredmaxu.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v64i32(<64 x i32> %v) @@ -5592,6 +5881,7 @@ ; RV32-NEXT: vsrl.vx v26, v25, a0 ; RV32-NEXT: vmv.x.s a1, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v1i64: @@ -5599,6 +5889,7 @@ ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %v) @@ -5621,6 +5912,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v2i64: @@ -5632,6 +5924,7 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vredmaxu.vs v25, v25, v26 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %v) @@ -5654,6 +5947,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v4i64: @@ -5665,6 +5959,7 @@ ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vredmaxu.vs v25, v26, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v) @@ -5687,6 +5982,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v8i64: @@ -5698,6 +5994,7 @@ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vredmaxu.vs v25, v28, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %v) @@ -5720,6 +6017,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v16i64: @@ -5731,6 +6029,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredmaxu.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> %v) @@ -5756,6 +6055,7 @@ ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v32i64: @@ -5770,6 +6070,7 @@ ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vredmaxu.vs v25, v8, v25 ; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v32i64(<32 x i64> %v) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll @@ -16,6 +16,7 @@ ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.and.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl) ret i1 %r @@ -34,6 +35,7 @@ ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.or.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl) ret i1 %r @@ -51,6 +53,7 @@ ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.xor.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl) ret i1 %r @@ -68,6 +71,7 @@ ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.and.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl) ret i1 %r @@ -86,6 +90,7 @@ ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.or.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl) ret i1 %r @@ -103,6 +108,7 @@ ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.xor.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl) ret i1 %r @@ -120,6 +126,7 @@ ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.and.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl) ret i1 %r @@ -138,6 +145,7 @@ ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.or.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl) ret i1 %r @@ -155,6 +163,7 @@ ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.xor.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl) ret i1 %r @@ -172,6 +181,7 @@ ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.and.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl) ret i1 %r @@ -190,6 +200,7 @@ ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.or.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl) ret i1 %r @@ -207,6 +218,7 @@ ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.xor.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl) ret i1 %r @@ -224,6 +236,7 @@ ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.and.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl) ret i1 %r @@ -242,6 +255,7 @@ ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.or.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl) ret i1 %r @@ -259,6 +273,7 @@ ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %r = call i1 @llvm.vp.reduce.xor.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl) ret i1 %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll @@ -12,6 +12,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x half> %a, <2 x half> %b ret <2 x half> %v @@ -26,6 +27,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq half %a, %b %v = select i1 %cmp, <2 x half> %c, <2 x half> %d @@ -40,6 +42,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x half> %a, <4 x half> %b ret <4 x half> %v @@ -54,6 +57,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq half %a, %b %v = select i1 %cmp, <4 x half> %c, <4 x half> %d @@ -68,6 +72,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x half> %a, <8 x half> %b ret <8 x half> %v @@ -82,6 +87,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq half %a, %b %v = select i1 %cmp, <8 x half> %c, <8 x half> %d @@ -96,6 +102,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x half> %a, <16 x half> %b ret <16 x half> %v @@ -110,6 +117,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq half %a, %b %v = select i1 %cmp, <16 x half> %c, <16 x half> %d @@ -124,6 +132,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x float> %a, <2 x float> %b ret <2 x float> %v @@ -138,6 +147,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq float %a, %b %v = select i1 %cmp, <2 x float> %c, <2 x float> %d @@ -152,6 +162,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x float> %a, <4 x float> %b ret <4 x float> %v @@ -166,6 +177,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq float %a, %b %v = select i1 %cmp, <4 x float> %c, <4 x float> %d @@ -180,6 +192,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x float> %a, <8 x float> %b ret <8 x float> %v @@ -194,6 +207,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq float %a, %b %v = select i1 %cmp, <8 x float> %c, <8 x float> %d @@ -208,6 +222,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x float> %a, <16 x float> %b ret <16 x float> %v @@ -222,6 +237,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq float %a, %b %v = select i1 %cmp, <16 x float> %c, <16 x float> %d @@ -236,6 +252,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x double> %a, <2 x double> %b ret <2 x double> %v @@ -250,6 +267,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq double %a, %b %v = select i1 %cmp, <2 x double> %c, <2 x double> %d @@ -264,6 +282,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x double> %a, <4 x double> %b ret <4 x double> %v @@ -278,6 +297,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq double %a, %b %v = select i1 %cmp, <4 x double> %c, <4 x double> %d @@ -292,6 +312,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x double> %a, <8 x double> %b ret <8 x double> %v @@ -306,6 +327,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq double %a, %b %v = select i1 %cmp, <8 x double> %c, <8 x double> %d @@ -320,6 +342,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x double> %a, <16 x double> %b ret <16 x double> %v @@ -334,6 +357,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = fcmp oeq double %a, %b %v = select i1 %cmp, <16 x double> %c, <16 x double> %d diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll @@ -13,6 +13,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <1 x i1> %a, <1 x i1> %b ret <1 x i1> %v @@ -29,6 +30,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <1 x i1> %c, <1 x i1> %d @@ -44,6 +46,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x i1> %a, <2 x i1> %b ret <2 x i1> %v @@ -60,6 +63,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <2 x i1> %c, <2 x i1> %d @@ -75,6 +79,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x i1> %a, <4 x i1> %b ret <4 x i1> %v @@ -91,6 +96,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <4 x i1> %c, <4 x i1> %d @@ -106,6 +112,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x i1> %a, <8 x i1> %b ret <8 x i1> %v @@ -122,6 +129,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <8 x i1> %c, <8 x i1> %d @@ -137,6 +145,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x i1> %a, <16 x i1> %b ret <16 x i1> %v @@ -153,6 +162,7 @@ ; CHECK-NEXT: vmandnot.mm v26, v8, v25 ; CHECK-NEXT: vmand.mm v25, v0, v25 ; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <16 x i1> %c, <16 x i1> %d @@ -166,6 +176,7 @@ ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x i8> %a, <2 x i8> %b ret <2 x i8> %v @@ -180,6 +191,7 @@ ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i8 %a, %b %v = select i1 %cmp, <2 x i8> %c, <2 x i8> %d @@ -193,6 +205,7 @@ ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x i8> %a, <4 x i8> %b ret <4 x i8> %v @@ -207,6 +220,7 @@ ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i8 %a, %b %v = select i1 %cmp, <4 x i8> %c, <4 x i8> %d @@ -220,6 +234,7 @@ ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x i8> %a, <8 x i8> %b ret <8 x i8> %v @@ -234,6 +249,7 @@ ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i8 %a, %b %v = select i1 %cmp, <8 x i8> %c, <8 x i8> %d @@ -247,6 +263,7 @@ ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x i8> %a, <16 x i8> %b ret <16 x i8> %v @@ -261,6 +278,7 @@ ; CHECK-NEXT: vmv.v.x v25, a0 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i8 %a, %b %v = select i1 %cmp, <16 x i8> %c, <16 x i8> %d @@ -275,6 +293,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x i16> %a, <2 x i16> %b ret <2 x i16> %v @@ -290,6 +309,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i16 %a, %b %v = select i1 %cmp, <2 x i16> %c, <2 x i16> %d @@ -304,6 +324,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x i16> %a, <4 x i16> %b ret <4 x i16> %v @@ -319,6 +340,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i16 %a, %b %v = select i1 %cmp, <4 x i16> %c, <4 x i16> %d @@ -333,6 +355,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x i16> %a, <8 x i16> %b ret <8 x i16> %v @@ -348,6 +371,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i16 %a, %b %v = select i1 %cmp, <8 x i16> %c, <8 x i16> %d @@ -362,6 +386,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x i16> %a, <16 x i16> %b ret <16 x i16> %v @@ -377,6 +402,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i16 %a, %b %v = select i1 %cmp, <16 x i16> %c, <16 x i16> %d @@ -391,6 +417,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x i32> %a, <2 x i32> %b ret <2 x i32> %v @@ -406,6 +433,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i32 %a, %b %v = select i1 %cmp, <2 x i32> %c, <2 x i32> %d @@ -420,6 +448,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x i32> %a, <4 x i32> %b ret <4 x i32> %v @@ -435,6 +464,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i32 %a, %b %v = select i1 %cmp, <4 x i32> %c, <4 x i32> %d @@ -449,6 +479,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x i32> %a, <8 x i32> %b ret <8 x i32> %v @@ -464,6 +495,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i32 %a, %b %v = select i1 %cmp, <8 x i32> %c, <8 x i32> %d @@ -478,6 +510,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x i32> %a, <16 x i32> %b ret <16 x i32> %v @@ -493,6 +526,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %cmp = icmp ne i32 %a, %b %v = select i1 %cmp, <16 x i32> %c, <16 x i32> %d @@ -507,6 +541,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x i64> %a, <2 x i64> %b ret <2 x i64> %v @@ -524,6 +559,7 @@ ; RV32-NEXT: vmsne.vi v0, v25, 0 ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vmerge.vvm v8, v9, v8, v0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: selectcc_v2i64: @@ -535,6 +571,7 @@ ; RV64-NEXT: vmsne.vi v0, v25, 0 ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vmerge.vvm v8, v9, v8, v0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %cmp = icmp ne i64 %a, %b %v = select i1 %cmp, <2 x i64> %c, <2 x i64> %d @@ -549,6 +586,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x i64> %a, <4 x i64> %b ret <4 x i64> %v @@ -566,6 +604,7 @@ ; RV32-NEXT: vmsne.vi v0, v25, 0 ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32-NEXT: vmerge.vvm v8, v10, v8, v0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: selectcc_v4i64: @@ -577,6 +616,7 @@ ; RV64-NEXT: vmsne.vi v0, v25, 0 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV64-NEXT: vmerge.vvm v8, v10, v8, v0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %cmp = icmp ne i64 %a, %b %v = select i1 %cmp, <4 x i64> %c, <4 x i64> %d @@ -591,6 +631,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x i64> %a, <8 x i64> %b ret <8 x i64> %v @@ -608,6 +649,7 @@ ; RV32-NEXT: vmsne.vi v0, v25, 0 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vmerge.vvm v8, v12, v8, v0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: selectcc_v8i64: @@ -619,6 +661,7 @@ ; RV64-NEXT: vmsne.vi v0, v25, 0 ; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV64-NEXT: vmerge.vvm v8, v12, v8, v0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %cmp = icmp ne i64 %a, %b %v = select i1 %cmp, <8 x i64> %c, <8 x i64> %d @@ -633,6 +676,7 @@ ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x i64> %a, <16 x i64> %b ret <16 x i64> %v @@ -650,6 +694,7 @@ ; RV32-NEXT: vmsne.vi v0, v25, 0 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vmerge.vvm v8, v16, v8, v0 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: selectcc_v16i64: @@ -661,6 +706,7 @@ ; RV64-NEXT: vmsne.vi v0, v25, 0 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64-NEXT: vmerge.vvm v8, v16, v8, v0 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %cmp = icmp ne i64 %a, %b %v = select i1 %cmp, <16 x i64> %c, <16 x i64> %d diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll @@ -9,6 +9,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <2 x i8> @llvm.experimental.stepvector.v2i8() ret <2 x i8> %v @@ -21,6 +22,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <4 x i8> @llvm.experimental.stepvector.v4i8() ret <4 x i8> %v @@ -33,6 +35,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <8 x i8> @llvm.experimental.stepvector.v8i8() ret <8 x i8> %v @@ -45,6 +48,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <16 x i8> @llvm.experimental.stepvector.v16i8() ret <16 x i8> %v @@ -57,6 +61,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <2 x i16> @llvm.experimental.stepvector.v2i16() ret <2 x i16> %v @@ -69,6 +74,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <4 x i16> @llvm.experimental.stepvector.v4i16() ret <4 x i16> %v @@ -81,6 +87,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <8 x i16> @llvm.experimental.stepvector.v8i16() ret <8 x i16> %v @@ -94,12 +101,14 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vid.v v8 ; LMULMAX1-NEXT: vadd.vi v9, v8, 8 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-NEXT: vid.v v8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <16 x i16> @llvm.experimental.stepvector.v16i16() ret <16 x i16> %v @@ -112,6 +121,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <2 x i32> @llvm.experimental.stepvector.v2i32() ret <2 x i32> %v @@ -124,6 +134,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <4 x i32> @llvm.experimental.stepvector.v4i32() ret <4 x i32> %v @@ -137,12 +148,14 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vid.v v8 ; LMULMAX1-NEXT: vadd.vi v9, v8, 4 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vid.v v8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <8 x i32> @llvm.experimental.stepvector.v8i32() ret <8 x i32> %v @@ -158,6 +171,7 @@ ; LMULMAX1-NEXT: vadd.vi v9, v8, 4 ; LMULMAX1-NEXT: vadd.vi v10, v8, 8 ; LMULMAX1-NEXT: vadd.vi v11, v8, 12 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v16i32: @@ -165,6 +179,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vid.v v8 ; LMULMAX2-NEXT: vadd.vi v10, v8, 8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <16 x i32> @llvm.experimental.stepvector.v16i32() ret <16 x i32> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll @@ -9,6 +9,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <2 x i8> @llvm.experimental.stepvector.v2i8() ret <2 x i8> %v @@ -21,6 +22,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <4 x i8> @llvm.experimental.stepvector.v4i8() ret <4 x i8> %v @@ -33,6 +35,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <8 x i8> @llvm.experimental.stepvector.v8i8() ret <8 x i8> %v @@ -45,6 +48,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <16 x i8> @llvm.experimental.stepvector.v16i8() ret <16 x i8> %v @@ -57,6 +61,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <2 x i16> @llvm.experimental.stepvector.v2i16() ret <2 x i16> %v @@ -69,6 +74,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <4 x i16> @llvm.experimental.stepvector.v4i16() ret <4 x i16> %v @@ -81,6 +87,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <8 x i16> @llvm.experimental.stepvector.v8i16() ret <8 x i16> %v @@ -94,12 +101,14 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vid.v v8 ; LMULMAX1-NEXT: vadd.vi v9, v8, 8 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-NEXT: vid.v v8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <16 x i16> @llvm.experimental.stepvector.v16i16() ret <16 x i16> %v @@ -112,6 +121,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <2 x i32> @llvm.experimental.stepvector.v2i32() ret <2 x i32> %v @@ -124,6 +134,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <4 x i32> @llvm.experimental.stepvector.v4i32() ret <4 x i32> %v @@ -137,12 +148,14 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vid.v v8 ; LMULMAX1-NEXT: vadd.vi v9, v8, 4 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vid.v v8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <8 x i32> @llvm.experimental.stepvector.v8i32() ret <8 x i32> %v @@ -158,6 +171,7 @@ ; LMULMAX1-NEXT: vadd.vi v9, v8, 4 ; LMULMAX1-NEXT: vadd.vi v10, v8, 8 ; LMULMAX1-NEXT: vadd.vi v11, v8, 12 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v16i32: @@ -165,6 +179,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vid.v v8 ; LMULMAX2-NEXT: vadd.vi v10, v8, 8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <16 x i32> @llvm.experimental.stepvector.v16i32() ret <16 x i32> %v @@ -177,6 +192,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <2 x i64> @llvm.experimental.stepvector.v2i64() ret <2 x i64> %v @@ -190,12 +206,14 @@ ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vid.v v8 ; LMULMAX1-NEXT: vadd.vi v9, v8, 2 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-NEXT: vid.v v8 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <4 x i64> @llvm.experimental.stepvector.v4i64() ret <4 x i64> %v @@ -211,6 +229,7 @@ ; LMULMAX1-NEXT: vadd.vi v9, v8, 2 ; LMULMAX1-NEXT: vadd.vi v10, v8, 4 ; LMULMAX1-NEXT: vadd.vi v11, v8, 6 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v8i64: @@ -218,6 +237,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-NEXT: vid.v v8 ; LMULMAX2-NEXT: vadd.vi v10, v8, 4 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <8 x i64> @llvm.experimental.stepvector.v8i64() ret <8 x i64> %v @@ -237,6 +257,7 @@ ; LMULMAX1-NEXT: vadd.vi v13, v8, 10 ; LMULMAX1-NEXT: vadd.vi v14, v8, 12 ; LMULMAX1-NEXT: vadd.vi v15, v8, 14 +; LMULMAX1-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX1-NEXT: ret ; ; LMULMAX2-LABEL: stepvector_v16i64: @@ -246,6 +267,7 @@ ; LMULMAX2-NEXT: vadd.vi v10, v8, 4 ; LMULMAX2-NEXT: vadd.vi v12, v8, 8 ; LMULMAX2-NEXT: vadd.vi v14, v8, 12 +; LMULMAX2-NEXT: .cfi_def_cfa_offset 0 ; LMULMAX2-NEXT: ret %v = call <16 x i64> @llvm.experimental.stepvector.v16i64() ret <16 x i64> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll @@ -9,12 +9,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vle8.v v8, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: load_v4i32_align1: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vle8.v v8, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %z = load <4 x i32>, <4 x i32>* %ptr, align 1 ret <4 x i32> %z @@ -25,12 +27,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vle8.v v8, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: load_v4i32_align2: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vle8.v v8, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %z = load <4 x i32>, <4 x i32>* %ptr, align 2 ret <4 x i32> %z @@ -41,12 +45,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vse8.v v8, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: store_v4i32_align1: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vse8.v v8, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <4 x i32> %x, <4 x i32>* %ptr, align 1 ret void @@ -57,12 +63,14 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vse8.v v8, (a0) +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: store_v4i32_align2: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vse8.v v8, (a0) +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret store <4 x i32> %x, <4 x i32>* %ptr, align 2 ret void @@ -116,6 +124,7 @@ ; RV32-NEXT: .LBB4_4: # %else2 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i16_align1: @@ -163,6 +172,7 @@ ; RV64-NEXT: .LBB4_4: # %else2 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 1, <2 x i1> %m, <2 x i16> %passthru) ret <2 x i16> %v @@ -216,6 +226,7 @@ ; RV32-NEXT: .LBB5_4: # %else2 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_v2i64_align4: @@ -263,6 +274,7 @@ ; RV64-NEXT: .LBB5_4: # %else2 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret %v = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> %ptrs, i32 4, <2 x i1> %m, <2 x i64> %passthru) ret <2 x i64> %v @@ -300,6 +312,7 @@ ; RV32-NEXT: bnez a0, .LBB6_8 ; RV32-NEXT: .LBB6_4: # %else6 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; RV32-NEXT: .LBB6_5: # %cond.store ; RV32-NEXT: vsetivli zero, 0, e16, mf2, ta, mu @@ -346,6 +359,7 @@ ; RV32-NEXT: srli a0, a0, 8 ; RV32-NEXT: sb a0, 1(a1) ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v4i16_align1: @@ -377,6 +391,7 @@ ; RV64-NEXT: bnez a0, .LBB6_8 ; RV64-NEXT: .LBB6_4: # %else6 ; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ; RV64-NEXT: .LBB6_5: # %cond.store ; RV64-NEXT: vsetivli zero, 0, e16, mf2, ta, mu @@ -423,6 +438,7 @@ ; RV64-NEXT: srli a0, a0, 8 ; RV64-NEXT: sb a0, 1(a1) ; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> %val, <4 x i16*> %ptrs, i32 1, <4 x i1> %m) ret void @@ -454,6 +470,7 @@ ; RV32-NEXT: bnez a0, .LBB7_4 ; RV32-NEXT: .LBB7_2: # %else2 ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; RV32-NEXT: .LBB7_3: # %cond.store ; RV32-NEXT: vsetivli zero, 0, e32, mf2, ta, mu @@ -474,6 +491,7 @@ ; RV32-NEXT: srli a0, a0, 16 ; RV32-NEXT: sh a0, 2(a1) ; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i32_align2: @@ -499,6 +517,7 @@ ; RV64-NEXT: bnez a0, .LBB7_4 ; RV64-NEXT: .LBB7_2: # %else2 ; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret ; RV64-NEXT: .LBB7_3: # %cond.store ; RV64-NEXT: vsetivli zero, 0, e32, mf2, ta, mu @@ -521,6 +540,7 @@ ; RV64-NEXT: srli a0, a0, 16 ; RV64-NEXT: sh a0, 2(a1) ; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %val, <2 x i32*> %ptrs, i32 2, <2 x i1> %m) ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll @@ -11,6 +11,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.add.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) ret <8 x i7> %v @@ -23,6 +24,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) ret <2 x i8> %v @@ -33,6 +35,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %head = insertelement <2 x i1> undef, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer @@ -45,6 +48,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer @@ -57,6 +61,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer @@ -71,6 +76,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> undef, i8 -1, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer @@ -83,6 +89,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vadd.vi v8, v8, -1 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> undef, i8 -1, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer @@ -99,6 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) ret <4 x i8> %v @@ -109,6 +117,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %head = insertelement <4 x i1> undef, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer @@ -121,6 +130,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer @@ -133,6 +143,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer @@ -147,6 +158,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> undef, i8 -1, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer @@ -159,6 +171,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vadd.vi v8, v8, -1 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> undef, i8 -1, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer @@ -175,6 +188,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) ret <5 x i8> %v @@ -185,6 +199,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %head = insertelement <5 x i1> undef, i1 true, i32 0 %m = shufflevector <5 x i1> %head, <5 x i1> undef, <5 x i32> zeroinitializer @@ -197,6 +212,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> undef, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> undef, <5 x i32> zeroinitializer @@ -209,6 +225,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> undef, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> undef, <5 x i32> zeroinitializer @@ -223,6 +240,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> undef, i8 -1, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> undef, <5 x i32> zeroinitializer @@ -235,6 +253,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vi v8, v8, -1 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> undef, i8 -1, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> undef, <5 x i32> zeroinitializer @@ -251,6 +270,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) ret <8 x i8> %v @@ -261,6 +281,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret %head = insertelement <8 x i1> undef, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x