diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3718,12 +3718,6 @@ HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); } - if (X86::BNDRRegClass.hasSubClassEq(RC)) { - if (STI.is64Bit()) - return load ? X86::BNDMOV64rm : X86::BNDMOV64mr; - else - return load ? X86::BNDMOV32rm : X86::BNDMOV32mr; - } llvm_unreachable("Unknown 16-byte regclass"); } case 32: diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -3159,9 +3159,6 @@ include "X86InstrMMX.td" include "X86Instr3DNow.td" -// MPX instructions -include "X86InstrMPX.td" - include "X86InstrVMX.td" include "X86InstrSVM.td" include "X86InstrSNP.td" diff --git a/llvm/lib/Target/X86/X86InstrMPX.td b/llvm/lib/Target/X86/X86InstrMPX.td deleted file mode 100644 --- a/llvm/lib/Target/X86/X86InstrMPX.td +++ /dev/null @@ -1,77 +0,0 @@ -//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file describes the X86 MPX instruction set, defining the -// instructions, and properties of the instructions which are needed for code -// generation, machine code emission, and analysis. -// -//===----------------------------------------------------------------------===// - -// FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM. -let SchedRW = [WriteSystem] in { - -multiclass mpx_bound_make opc, string OpcodeStr> { - def 32rm: I, - Requires<[Not64BitMode]>; - def 64rm: I, - Requires<[In64BitMode]>; -} - -defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS; - -multiclass mpx_bound_check opc, string OpcodeStr> { - def 32rm: I, - Requires<[Not64BitMode]>; - def 64rm: I, - Requires<[In64BitMode]>; - - def 32rr: I, - Requires<[Not64BitMode]>; - def 64rr: I, - Requires<[In64BitMode]>; -} -defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable; -defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable; -defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable; - -def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - NotMemoryFoldable; -let mayLoad = 1 in { -def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[Not64BitMode]>, NotMemoryFoldable; -def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[In64BitMode]>, NotMemoryFoldable; -} -let isCodeGenOnly = 1, ForceDisassemble = 1 in -def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - NotMemoryFoldable; -let mayStore = 1 in { -def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[Not64BitMode]>, NotMemoryFoldable; -def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[In64BitMode]>, NotMemoryFoldable; - -def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src), - "bndstx\t{$src, $dst|$dst, $src}", []>, PS; -} -let mayLoad = 1 in -def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), - "bndldx\t{$src, $dst|$dst, $src}", []>, PS; -} // SchedRW diff --git a/llvm/test/MC/X86/mpx-encodings.s b/llvm/test/MC/X86/mpx-encodings.s deleted file mode 100644 --- a/llvm/test/MC/X86/mpx-encodings.s +++ /dev/null @@ -1,41 +0,0 @@ -// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\ -// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING - -// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\ -// RUN: llvm-objdump -d - | FileCheck %s - -// CHECK: bndmk (%rax), %bnd0 -// ENCODING: encoding: [0xf3,0x0f,0x1b,0x00] -bndmk (%rax), %bnd0 - -// CHECK: bndmk 1024(%rax), %bnd1 -// ENCODING: encoding: [0xf3,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00] -bndmk 1024(%rax), %bnd1 - -// CHECK: bndmov %bnd2, %bnd1 -// ENCODING: encoding: [0x66,0x0f,0x1a,0xca] -bndmov %bnd2, %bnd1 - -// CHECK: bndmov %bnd1, 1024(%r9) -// ENCODING: encoding: [0x66,0x41,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00] -bndmov %bnd1, 1024(%r9) - -// CHECK: bndstx %bnd1, 1024(%rax) -// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00] -bndstx %bnd1, 1024(%rax) - -// CHECK: bndldx 1024(%r8), %bnd1 -// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00] -bndldx 1024(%r8), %bnd1 - -// CHECK: bndcl 121(%r10), %bnd1 -// ENCODING: encoding: [0xf3,0x41,0x0f,0x1a,0x4a,0x79] -bndcl 121(%r10), %bnd1 - -// CHECK: bndcn 121(%rcx), %bnd3 -// ENCODING: encoding: [0xf2,0x0f,0x1b,0x59,0x79] -bndcn 121(%rcx), %bnd3 - -// CHECK: bndcu %rdx, %bnd3 -// ENCODING: encoding: [0xf2,0x0f,0x1a,0xda] -bndcu %rdx, %bnd3 diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -213,26 +213,6 @@ ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm()); } -TEST_F(X86ParallelSnippetGeneratorTest, ParallelInstruction) { - // - BNDCL32rr - // - Op0 Explicit Use RegClass(BNDR) - // - Op1 Explicit Use RegClass(GR32) - // - Var0 [Op0] - // - Var1 [Op1] - const unsigned Opcode = X86::BNDCL32rr; - const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); - ASSERT_THAT(CodeTemplates, SizeIs(1)); - const auto &CT = CodeTemplates[0]; - EXPECT_THAT(CT.Info, HasSubstr("parallel")); - EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN); - ASSERT_THAT(CT.Instructions, SizeIs(1)); - const InstructionTemplate &IT = CT.Instructions[0]; - EXPECT_THAT(IT.getOpcode(), Opcode); - ASSERT_THAT(IT.getVariableValues(), SizeIs(2)); - EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()); - EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()); -} - TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) { // - CDQ // - Op0 Implicit Def Reg(EAX)