Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -241,15 +241,20 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMemEVA(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCacheOpR6(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, @@ -1101,10 +1106,30 @@ Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - if(Inst.getOpcode() == Mips::SC || - Inst.getOpcode() == Mips::SCD){ + if (Inst.getOpcode() == Mips::SC || + Inst.getOpcode() == Mips::SCD) Inst.addOperand(MCOperand::createReg(Reg)); - } + + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + + return MCDisassembler::Success; +} + +static DecodeStatus DecodeMemEVA(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<9>(Insn >> 7); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + if (Inst.getOpcode() == Mips::SCE) + Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1147,11 +1172,11 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCacheOpR6(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { - int Offset = fieldFromInstruction(Insn, 7, 9); +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<9>(Insn >> 7); unsigned Hint = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Index: lib/Target/Mips/Mips.td =================================================================== --- lib/Target/Mips/Mips.td +++ lib/Target/Mips/Mips.td @@ -157,6 +157,8 @@ def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; +def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">; + def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", "microMips mode">; Index: lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips32r6InstrInfo.td +++ lib/Target/Mips/Mips32r6InstrInfo.td @@ -559,7 +559,7 @@ dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); list Pattern = []; - string DecoderMethod = "DecodeCacheOpR6"; + string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; } class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>; Index: lib/Target/Mips/MipsEVAInstrFormats.td =================================================================== --- /dev/null +++ lib/Target/Mips/MipsEVAInstrFormats.td @@ -0,0 +1,84 @@ +//===- MipsEVAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes Mips32r6 instruction formats. +// +//===----------------------------------------------------------------------===// + +class MipsEVAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, + PredicateControl, StdArch { + let DecoderNamespace = "Mips"; + let EncodingPredicates = [HasStdEnc]; +} + +//===----------------------------------------------------------------------===// +// +// Field Values +// +//===----------------------------------------------------------------------===// + +// Memory Load/Store EVA +def OPCODE6_LBE : OPCODE6<0b101100>; +def OPCODE6_LBuE : OPCODE6<0b101000>; +def OPCODE6_LHE : OPCODE6<0b101101>; +def OPCODE6_LHuE : OPCODE6<0b101001>; +def OPCODE6_LWE : OPCODE6<0b101111>; + +def OPCODE6_SBE : OPCODE6<0b011100>; +def OPCODE6_SHE : OPCODE6<0b011101>; +def OPCODE6_SWE : OPCODE6<0b011111>; + +// load/store left/right EVA +def OPCODE6_LWLE : OPCODE6<0b011001>; +def OPCODE6_LWRE : OPCODE6<0b011010>; +def OPCODE6_SWLE : OPCODE6<0b100001>; +def OPCODE6_SWRE : OPCODE6<0b100010>; + +// Load-linked EVA, Store-conditional EVA +def OPCODE6_LLE : OPCODE6<0b101110>; +def OPCODE6_SCE : OPCODE6<0b011110>; + +def OPCODE6_TLBINV : OPCODE6<0b000011>; +def OPCODE6_TLBINVF : OPCODE6<0b000100>; + +def OPCODE6_CACHEE : OPCODE6<0b011011>; +def OPCODE6_PREFE : OPCODE6<0b100011>; + +def OPGROUP_COP0 : OPGROUP<0b010000>; + +//===----------------------------------------------------------------------===// +// +// Encoding Formats +// +//===----------------------------------------------------------------------===// + +class SPECIAL3_EVA_LOAD_STORE_FM : MipsEVAInst { + bits<21> addr; + bits<5> hint; + bits<5> base = addr{20-16}; + bits<9> offset = addr{8-0}; + + bits<32> Inst; + + let Inst{31-26} = OPGROUP_SPECIAL3.Value; + let Inst{25-21} = base; + let Inst{20-16} = hint; + let Inst{15-7} = offset; + let Inst{6} = 0; + let Inst{5-0} = Operation.Value; +} + +class TLB_FM : MipsEVAInst { + bits<32> Inst; + + let Inst{31-26} = OPGROUP_COP0.Value; + let Inst{25} = 1; // CO + let Inst{24-6} = 0; + let Inst{5-0} = Operation.Value; +} Index: lib/Target/Mips/MipsEVAInstrInfo.td =================================================================== --- /dev/null +++ lib/Target/Mips/MipsEVAInstrInfo.td @@ -0,0 +1,192 @@ +//===- MipsEVAInstrInfo.td - EVA ASE instructions -*- tablegen ------------*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes Mips EVA ASE instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// Instruction encodings +// +//===----------------------------------------------------------------------===// + +// Memory Load/Store EVA encodings +class LBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class LBuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class LHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class LHuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class LWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; + +class SBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class SHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class SWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; + +// load/store left/right EVA encodings +class LWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class LWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class SWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class SWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; + +// Load-linked EVA, Store-conditional EVA encodings +class LLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class SCE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; + +class TLBINV_ENC : TLB_FM; +class TLBINVF_ENC : TLB_FM; + +class CACHEE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; +class PREFE_ENC : SPECIAL3_EVA_LOAD_STORE_FM; + +//===----------------------------------------------------------------------===// +// +// Instruction descriptions +// +//===----------------------------------------------------------------------===// + +// Memory Load/Store EVA descriptions +class LOAD_EVA_DESC_BASE { + dag OutOperandList = (outs GPROpnd:$rt); + dag InOperandList = (ins mem_simm9:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + list Pattern = []; + string DecoderMethod = "DecodeMemEVA"; + bit canFoldAsLoad = 1; + bit mayLoad = 1; +} + +class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd>; +class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd>; +class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd>; +class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd>; +class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd>; + +class STORE_EVA_DESC_BASE { + dag OutOperandList = (outs); + dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + list Pattern = []; + string DecoderMethod = "DecodeMemEVA"; + bit mayStore = 1; +} + +class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd>; +class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd>; +class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd>; + +// Load/Store Left/Right EVA descriptions +class LOAD_LEFT_RIGHT_EVA_DESC_BASE { + dag OutOperandList = (outs GPROpnd:$rt); + dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + list Pattern = []; + string DecoderMethod = "DecodeMemEVA"; + string Constraints = "$src = $rt"; + bit canFoldAsLoad = 1; +} + +class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd>; +class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd>; + +class STORE_LEFT_RIGHT_EVA_DESC_BASE { + dag OutOperandList = (outs); + dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + list Pattern = []; + string DecoderMethod = "DecodeMemEVA"; +} + +class SWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd>; +class SWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd>; + +// Load-linked EVA, Store-conditional EVA descriptions +class LLE_DESC_BASE { + dag OutOperandList = (outs GPROpnd:$rt); + dag InOperandList = (ins mem_simm9:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + list Pattern = []; + bit mayLoad = 1; + string DecoderMethod = "DecodeMemEVA"; +} + +class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd>; + +class SCE_DESC_BASE { + dag OutOperandList = (outs GPROpnd:$dst); + dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + list Pattern = []; + bit mayStore = 1; + string Constraints = "$rt = $dst"; + string DecoderMethod = "DecodeMemEVA"; +} + +class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd>; + +class TLB_DESC_BASE { + dag OutOperandList = (outs); + dag InOperandList = (ins); + string AsmString = instr_asm; + list Pattern = []; +} + +class TLBINV_DESC : TLB_DESC_BASE<"tlbinv">; +class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf">; + +class CACHEE_DESC_BASE { + dag OutOperandList = (outs); + dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); + string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); + list Pattern = []; + string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; +} + +class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem>; +class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem>; + +//===----------------------------------------------------------------------===// +// +// Instruction definitions +// +//===----------------------------------------------------------------------===// + +/// Load and Store EVA Instructions +def LBE : LBE_ENC, LBE_DESC, INSN_EVA; +def LBuE : LBuE_ENC, LBuE_DESC, INSN_EVA; +def LHE : LHE_ENC, LHE_DESC, INSN_EVA; +def LHuE : LHuE_ENC, LHuE_DESC, INSN_EVA; +let AdditionalPredicates = [NotInMicroMips] in { +def LWE : LWE_ENC, LWE_DESC, INSN_EVA; +} +def SBE : SBE_ENC, SBE_DESC, INSN_EVA; +def SHE : SHE_ENC, SHE_DESC, INSN_EVA; +let AdditionalPredicates = [NotInMicroMips] in { +def SWE : SWE_ENC, SWE_DESC, INSN_EVA; +} + +/// load/store left/right EVA +let AdditionalPredicates = [NotInMicroMips] in { +def LWLE : LWLE_ENC, LWLE_DESC, INSN_EVA_NOT_32R6_64R6; +def LWRE : LWRE_ENC, LWRE_DESC, INSN_EVA_NOT_32R6_64R6; +def SWLE : SWLE_ENC, SWLE_DESC, INSN_EVA_NOT_32R6_64R6; +def SWRE : SWRE_ENC, SWRE_DESC, INSN_EVA_NOT_32R6_64R6; +} + +/// Load-linked EVA, Store-conditional EVA +let AdditionalPredicates = [NotInMicroMips] in { +def LLE : LLE_ENC, LLE_DESC, INSN_EVA; +def SCE : SCE_ENC, SCE_DESC, INSN_EVA; +} + +def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA; +def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA; + +def CACHEE : CACHEE_ENC, CACHEE_DESC, INSN_EVA; +def PREFE : PREFE_ENC, PREFE_DESC, INSN_EVA; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -206,6 +206,8 @@ def IsBE : Predicate<"!Subtarget->isLittle()">; def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">; +def HasEVA : Predicate<"Subtarget->hasEVA()">, + AssemblerPredicate<"FeatureEVA,FeatureMips32r2">; //===----------------------------------------------------------------------===// // Mips GPR size adjectives. @@ -263,6 +265,11 @@ list InsnPredicates = [HasMicroMips64r6]; } +class INSN_EVA { list InsnPredicates = [HasEVA]; } +class INSN_EVA_NOT_32R6_64R6 { + list InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA]; +} + // The portions of MIPS-III that were also added to MIPS32 class INSN_MIPS3_32 { list InsnPredicates = [HasMips3_32]; } @@ -1992,6 +1999,10 @@ include "MipsMSAInstrFormats.td" include "MipsMSAInstrInfo.td" +// EVA +include "MipsEVAInstrFormats.td" +include "MipsEVAInstrInfo.td" + // Micromips include "MicroMipsInstrFormats.td" include "MicroMipsInstrInfo.td" Index: lib/Target/Mips/MipsSchedule.td =================================================================== --- lib/Target/Mips/MipsSchedule.td +++ lib/Target/Mips/MipsSchedule.td @@ -69,20 +69,27 @@ def II_FLOOR : InstrItinClass; def II_INS : InstrItinClass; // Any INS instruction def II_LB : InstrItinClass; +def II_LBE : InstrItinClass; def II_LBU : InstrItinClass; +def II_LBUE : InstrItinClass; def II_LD : InstrItinClass; def II_LDC1 : InstrItinClass; def II_LDL : InstrItinClass; def II_LDR : InstrItinClass; def II_LDXC1 : InstrItinClass; def II_LH : InstrItinClass; +def II_LHE : InstrItinClass; def II_LHU : InstrItinClass; +def II_LHUE : InstrItinClass; def II_LUI : InstrItinClass; def II_LUXC1 : InstrItinClass; def II_LW : InstrItinClass; +def II_LWE : InstrItinClass; def II_LWC1 : InstrItinClass; def II_LWL : InstrItinClass; +def II_LWLE : InstrItinClass; def II_LWR : InstrItinClass; +def II_LWRE : InstrItinClass; def II_LWU : InstrItinClass; def II_LWXC1 : InstrItinClass; def II_MADD : InstrItinClass; @@ -134,6 +141,7 @@ def II_ROUND : InstrItinClass; def II_SAVE : InstrItinClass; def II_SB : InstrItinClass; +def II_SBE : InstrItinClass; def II_SD : InstrItinClass; def II_SDC1 : InstrItinClass; def II_SDL : InstrItinClass; @@ -144,6 +152,7 @@ def II_SEQ_SNE : InstrItinClass; // seq and sne def II_SEQI_SNEI : InstrItinClass; // seqi and snei def II_SH : InstrItinClass; +def II_SHE : InstrItinClass; def II_SLL : InstrItinClass; def II_SLLV : InstrItinClass; def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu @@ -159,9 +168,12 @@ def II_SUB_S : InstrItinClass; def II_SUXC1 : InstrItinClass; def II_SW : InstrItinClass; +def II_SWE : InstrItinClass; def II_SWC1 : InstrItinClass; def II_SWL : InstrItinClass; +def II_SWLE : InstrItinClass; def II_SWR : InstrItinClass; +def II_SWRE : InstrItinClass; def II_SWXC1 : InstrItinClass; def II_TRUNC : InstrItinClass; def II_XOR : InstrItinClass; Index: lib/Target/Mips/MipsSubtarget.h =================================================================== --- lib/Target/Mips/MipsSubtarget.h +++ lib/Target/Mips/MipsSubtarget.h @@ -133,6 +133,9 @@ // UseTCCInDIV -- Enables the use of trapping in the assembler. bool UseTCCInDIV; + // HasEVA -- supports EVA ASE. + bool HasEVA; + InstrItineraryData InstrItins; // We can override the determination of whether we are in mips16 mode @@ -235,6 +238,7 @@ bool hasDSP() const { return HasDSP; } bool hasDSPR2() const { return HasDSPR2; } bool hasMSA() const { return HasMSA; } + bool hasEVA() const { return HasEVA; } bool useSmallSection() const { return UseSmallSection; } bool hasStandardEncoding() const { return !inMips16Mode(); } Index: lib/Target/Mips/MipsSubtarget.cpp =================================================================== --- lib/Target/Mips/MipsSubtarget.cpp +++ lib/Target/Mips/MipsSubtarget.cpp @@ -70,7 +70,8 @@ HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), - HasMSA(false), UseTCCInDIV(false), TM(TM), TargetTriple(TT), TSInfo(), + HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM), + TargetTriple(TT), TSInfo(), InstrInfo( MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), Index: test/MC/Disassembler/Mips/eva/valid_R6-eva.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/Mips/eva/valid_R6-eva.txt @@ -0,0 +1,38 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r6 -mattr=eva | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r6 -mattr=eva | FileCheck %s +# CHECK: .text +0x7c 0xff 0x7f 0x9b # CHECK: cachee 31, 255($7) +0x7c 0x80 0x80 0x1b # CHECK: cachee 0, -256($4) +0x7c 0x85 0xba 0x1b # CHECK: cachee 5, -140($4) +0x7f 0x2a 0x80 0x2c # CHECK: lbe $10, -256($25) +0x7d 0xed 0x7f 0xac # CHECK: lbe $13, 255($15) +0x7d 0xcb 0x49 0x2c # CHECK: lbe $11, 146($14) +0x7c 0x6d 0x80 0x28 # CHECK: lbue $13, -256($3) +0x7c 0x4d 0x7f 0xa8 # CHECK: lbue $13, 255($2) +0x7c 0x6d 0xa1 0x28 # CHECK: lbue $13, -190($3) +0x7e 0xad 0x80 0x2d # CHECK: lhe $13, -256($21) +0x7e 0x0c 0x7f 0xad # CHECK: lhe $12, 255($16) +0x7e 0x0d 0x28 0xad # CHECK: lhe $13, 81($16) +0x7c 0x72 0x80 0x29 # CHECK: lhue $18, -256($3) +0x7c 0x72 0x7f 0xa9 # CHECK: lhue $18, 255($3) +0x7c 0x56 0xac 0x29 # CHECK: lhue $22, -168($2) +0x7e 0xa2 0x80 0x2e # CHECK: lle $2, -256($21) +0x7e 0x63 0x7f 0xae # CHECK: lle $3, 255($19) +0x7e 0xc3 0xdc 0xae # CHECK: lle $3, -71($22) +0x7c 0x4e 0x80 0x23 # CHECK: prefe 14, -256($2) +0x7c 0x6b 0x7f 0xa3 # CHECK: prefe 11, 255($3) +0x7c 0x6e 0xed 0xa3 # CHECK: prefe 14, -37($3) +0x7d 0x71 0x7f 0x9c # CHECK: sbe $17, 255($11) +0x7d 0x51 0x80 0x1c # CHECK: sbe $17, -256($10) +0x7d 0xd3 0x00 0x1c # CHECK: sbe $19, 0($14) +0x7e 0x49 0x7f 0x9e # CHECK: sce $9, 255($18) +0x7e 0xac 0x80 0x1e # CHECK: sce $12, -256($21) +0x7e 0xed 0xf0 0x9e # CHECK: sce $13, -31($23) +0x7d 0xee 0x7f 0x9d # CHECK: she $14, 255($15) +0x7d 0xee 0x80 0x1d # CHECK: she $14, -256($15) +0x7d 0x69 0x75 0x9d # CHECK: she $9, 235($11) +0x7f 0xbf 0x7f 0x9f # CHECK: swe $ra, 255($sp) +0x7f 0xbf 0x80 0x1f # CHECK: swe $ra, -256($sp) +0x7f 0xbf 0xe5 0x9f # CHECK: swe $ra, -53($sp) +0x42 0x00 0x00 0x03 # CHECK: tlbinv +0x42 0x00 0x00 0x04 # CHECK: tlbinvf Index: test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt @@ -0,0 +1,54 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r2 -mattr=eva | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r3 -mattr=eva | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r5 -mattr=eva | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=eva | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r3 -mattr=eva | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r5 -mattr=eva | FileCheck %s +# CHECK: .text +0x7c 0xff 0x7f 0x9b # CHECK: cachee 31, 255($7) +0x7c 0x80 0x80 0x1b # CHECK: cachee 0, -256($4) +0x7c 0x85 0xba 0x1b # CHECK: cachee 5, -140($4) +0x7f 0x2a 0x80 0x2c # CHECK: lbe $10, -256($25) +0x7d 0xed 0x7f 0xac # CHECK: lbe $13, 255($15) +0x7d 0xcb 0x49 0x2c # CHECK: lbe $11, 146($14) +0x7c 0x6d 0x80 0x28 # CHECK: lbue $13, -256($3) +0x7c 0x4d 0x7f 0xa8 # CHECK: lbue $13, 255($2) +0x7c 0x6d 0xa1 0x28 # CHECK: lbue $13, -190($3) +0x7e 0xad 0x80 0x2d # CHECK: lhe $13, -256($21) +0x7e 0x0c 0x7f 0xad # CHECK: lhe $12, 255($16) +0x7e 0x0d 0x28 0xad # CHECK: lhe $13, 81($16) +0x7c 0x72 0x80 0x29 # CHECK: lhue $18, -256($3) +0x7c 0x72 0x7f 0xa9 # CHECK: lhue $18, 255($3) +0x7c 0x56 0xac 0x29 # CHECK: lhue $22, -168($2) +0x7e 0xa2 0x80 0x2e # CHECK: lle $2, -256($21) +0x7e 0x63 0x7f 0xae # CHECK: lle $3, 255($19) +0x7e 0xc3 0xdc 0xae # CHECK: lle $3, -71($22) +0x7d 0xf6 0x7f 0x99 # CHECK: lwle $22, 255($15) +0x7d 0x57 0x80 0x19 # CHECK: lwle $23, -256($10) +0x7d 0xb7 0xa8 0x19 # CHECK: lwle $23, -176($13) +0x7f 0x80 0x7f 0x9a # CHECK: lwre $zero, 255($gp) +0x7f 0x80 0x80 0x1a # CHECK: lwre $zero, -256($gp) +0x7f 0x80 0xa8 0x1a # CHECK: lwre $zero, -176($gp) +0x7c 0x4e 0x80 0x23 # CHECK: prefe 14, -256($2) +0x7c 0x6b 0x7f 0xa3 # CHECK: prefe 11, 255($3) +0x7c 0x6e 0xed 0xa3 # CHECK: prefe 14, -37($3) +0x7d 0x71 0x7f 0x9c # CHECK: sbe $17, 255($11) +0x7d 0x51 0x80 0x1c # CHECK: sbe $17, -256($10) +0x7d 0xd3 0x00 0x1c # CHECK: sbe $19, 0($14) +0x7e 0x49 0x7f 0x9e # CHECK: sce $9, 255($18) +0x7e 0xac 0x80 0x1e # CHECK: sce $12, -256($21) +0x7e 0xed 0xf0 0x9e # CHECK: sce $13, -31($23) +0x7d 0xee 0x7f 0x9d # CHECK: she $14, 255($15) +0x7d 0xee 0x80 0x1d # CHECK: she $14, -256($15) +0x7d 0x69 0x75 0x9d # CHECK: she $9, 235($11) +0x7f 0xbf 0x7f 0x9f # CHECK: swe $ra, 255($sp) +0x7f 0xbf 0x80 0x1f # CHECK: swe $ra, -256($sp) +0x7f 0xbf 0xe5 0x9f # CHECK: swe $ra, -53($sp) +0x7e 0x29 0x7f 0xa1 # CHECK: swle $9, 255($17) +0x7e 0x6a 0x80 0x21 # CHECK: swle $10, -256($19) +0x7e 0xa8 0x41 0xa1 # CHECK: swle $8, 131($21) +0x7d 0xb4 0x7f 0xa2 # CHECK: swre $20, 255($13) +0x7d 0xb4 0x80 0x22 # CHECK: swre $20, -256($13) +0x7d 0xd2 0x2b 0x22 # CHECK: swre $18, 86($14) +0x42 0x00 0x00 0x03 # CHECK: tlbinv +0x42 0x00 0x00 0x04 # CHECK: tlbinvf Index: test/MC/Mips/eva/invalid-noeva-wrong-error.s =================================================================== --- /dev/null +++ test/MC/Mips/eva/invalid-noeva-wrong-error.s @@ -0,0 +1,69 @@ +# invalid operand for instructions that are invalid without -mattr=+eva flag and +# are correctly rejected but use the wrong error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r3 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r5 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r6 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + cachee 31, 255($7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + cachee 0, -256($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + cachee 5, -140($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbe $10,-256($25) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbe $13,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbe $11,146($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbue $13,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbue $13,255($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbue $13,-190($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $13,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $12,255($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $13,81($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $s2,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $s2,255($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $s6,-168($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lle $v0,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lle $v1,255($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lle $v1,-71($s6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwe $15,255($a2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwe $13,-256($a2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwe $15,-200($a1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s6,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s7,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s7,-176($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,255($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-256($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-176($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + prefe 14, -256($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + prefe 11, 255($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + prefe 14, -37($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sbe $s1,255($11) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sbe $s1,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sbe $s3,0($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sce $9,255($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sce $12,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sce $13,-31($s7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + she $14,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + she $14,-256($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + she $9,235($11) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swe $ra,255($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swe $ra,-256($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swe $ra,-53($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $9,255($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $10,-256($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $8,131($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s4,255($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s4,-256($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s2,86($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/eva/invalid-noeva.s =================================================================== --- /dev/null +++ test/MC/Mips/eva/invalid-noeva.s @@ -0,0 +1,22 @@ +# invalid operand for instructions that are invalid without -mattr=+eva flag +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r3 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r5 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r6 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + tlbinv # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlbinvf # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/eva/invalid_R6.s =================================================================== --- /dev/null +++ test/MC/Mips/eva/invalid_R6.s @@ -0,0 +1,20 @@ +# Instructions that are invalid as they were removed in R6 +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=+eva 2>%t1 +# RUN: FileCheck %s < %t1 +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=+eva 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + lwle $s6,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s7,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s7,-176($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,255($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-256($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-176($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $9,255($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $10,-256($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $8,131($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s4,255($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s4,-256($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s2,86($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/eva/valid_R6.s =================================================================== --- /dev/null +++ test/MC/Mips/eva/valid_R6.s @@ -0,0 +1,47 @@ +# Instructions that are valid +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=+eva | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=+eva | FileCheck %s +a: + .set noat + cachee 31, 255($7) # CHECK: cachee 31, 255($7) # encoding: [0x7c,0xff,0x7f,0x9b] + cachee 0, -256($4) # CHECK: cachee 0, -256($4) # encoding: [0x7c,0x80,0x80,0x1b] + cachee 5, -140($4) # CHECK: cachee 5, -140($4) # encoding: [0x7c,0x85,0xba,0x1b] + lbe $10,-256($25) # CHECK: lbe $10, -256($25) # encoding: [0x7f,0x2a,0x80,0x2c] + lbe $13,255($15) # CHECK: lbe $13, 255($15) # encoding: [0x7d,0xed,0x7f,0xac] + lbe $11,146($14) # CHECK: lbe $11, 146($14) # encoding: [0x7d,0xcb,0x49,0x2c] + lbue $13,-256($v1) # CHECK: lbue $13, -256($3) # encoding: [0x7c,0x6d,0x80,0x28] + lbue $13,255($v0) # CHECK: lbue $13, 255($2) # encoding: [0x7c,0x4d,0x7f,0xa8] + lbue $13,-190($v1) # CHECK: lbue $13, -190($3) # encoding: [0x7c,0x6d,0xa1,0x28] + lhe $13,-256($s5) # CHECK: lhe $13, -256($21) # encoding: [0x7e,0xad,0x80,0x2d] + lhe $12,255($s0) # CHECK: lhe $12, 255($16) # encoding: [0x7e,0x0c,0x7f,0xad] + lhe $13,81($s0) # CHECK: lhe $13, 81($16) # encoding: [0x7e,0x0d,0x28,0xad] + lhue $s2,-256($v1) # CHECK: lhue $18, -256($3) # encoding: [0x7c,0x72,0x80,0x29] + lhue $s2,255($v1) # CHECK: lhue $18, 255($3) # encoding: [0x7c,0x72,0x7f,0xa9] + lhue $s6,-168($v0) # CHECK: lhue $22, -168($2) # encoding: [0x7c,0x56,0xac,0x29] + lle $v0,-256($s5) # CHECK: lle $2, -256($21) # encoding: [0x7e,0xa2,0x80,0x2e] + lle $v1,255($s3) # CHECK: lle $3, 255($19) # encoding: [0x7e,0x63,0x7f,0xae] + lle $v1,-71($s6) # CHECK: lle $3, -71($22) # encoding: [0x7e,0xc3,0xdc,0xae] + lwe $15,255($a2) # CHECK: lwe $15, 255($6) # encoding: [0x7c,0xcf,0x7f,0xaf] + lwe $13,-256($a2) # CHECK: lwe $13, -256($6) # encoding: [0x7c,0xcd,0x80,0x2f] + lwe $15,-200($a1) # CHECK: lwe $15, -200($5) # encoding: [0x7c,0xaf,0x9c,0x2f] + prefe 14, -256($2) # CHECK: prefe 14, -256($2) # encoding: [0x7c,0x4e,0x80,0x23] + prefe 11, 255($3) # CHECK: prefe 11, 255($3) # encoding: [0x7c,0x6b,0x7f,0xa3] + prefe 14, -37($3) # CHECK: prefe 14, -37($3) # encoding: [0x7c,0x6e,0xed,0xa3] + sbe $s1,255($11) # CHECK: sbe $17, 255($11) # encoding: [0x7d,0x71,0x7f,0x9c] + sbe $s1,-256($10) # CHECK: sbe $17, -256($10) # encoding: [0x7d,0x51,0x80,0x1c] + sbe $s3,0($14) # CHECK: sbe $19, 0($14) # encoding: [0x7d,0xd3,0x00,0x1c] + sce $9,255($s2) # CHECK: sce $9, 255($18) # encoding: [0x7e,0x49,0x7f,0x9e] + sce $12,-256($s5) # CHECK: sce $12, -256($21) # encoding: [0x7e,0xac,0x80,0x1e] + sce $13,-31($s7) # CHECK: sce $13, -31($23) # encoding: [0x7e,0xed,0xf0,0x9e] + she $14,255($15) # CHECK: she $14, 255($15) # encoding: [0x7d,0xee,0x7f,0x9d] + she $14,-256($15) # CHECK: she $14, -256($15) # encoding: [0x7d,0xee,0x80,0x1d] + she $9,235($11) # CHECK: she $9, 235($11) # encoding: [0x7d,0x69,0x75,0x9d] + swe $ra,255($sp) # CHECK: swe $ra, 255($sp) # encoding: [0x7f,0xbf,0x7f,0x9f] + swe $ra,-256($sp) # CHECK: swe $ra, -256($sp) # encoding: [0x7f,0xbf,0x80,0x1f] + swe $ra,-53($sp) # CHECK: swe $ra, -53($sp) # encoding: [0x7f,0xbf,0xe5,0x9f] + tlbinv # CHECK: tlbinv # encoding: [0x42,0x00,0x00,0x03] + tlbinvf # CHECK: tlbinvf # encoding: [0x42,0x00,0x00,0x04] + + +1: Index: test/MC/Mips/eva/valid_preR6.s =================================================================== --- /dev/null +++ test/MC/Mips/eva/valid_preR6.s @@ -0,0 +1,62 @@ +# Instructions that are valid +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+eva | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 -mattr=+eva | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 -mattr=+eva | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 -mattr=+eva | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r3 -mattr=+eva | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r5 -mattr=+eva | FileCheck %s +a: + .set noat + cachee 31, 255($7) # CHECK: cachee 31, 255($7) # encoding: [0x7c,0xff,0x7f,0x9b] + cachee 0, -256($4) # CHECK: cachee 0, -256($4) # encoding: [0x7c,0x80,0x80,0x1b] + cachee 5, -140($4) # CHECK: cachee 5, -140($4) # encoding: [0x7c,0x85,0xba,0x1b] + lbe $10,-256($25) # CHECK: lbe $10, -256($25) # encoding: [0x7f,0x2a,0x80,0x2c] + lbe $13,255($15) # CHECK: lbe $13, 255($15) # encoding: [0x7d,0xed,0x7f,0xac] + lbe $11,146($14) # CHECK: lbe $11, 146($14) # encoding: [0x7d,0xcb,0x49,0x2c] + lbue $13,-256($v1) # CHECK: lbue $13, -256($3) # encoding: [0x7c,0x6d,0x80,0x28] + lbue $13,255($v0) # CHECK: lbue $13, 255($2) # encoding: [0x7c,0x4d,0x7f,0xa8] + lbue $13,-190($v1) # CHECK: lbue $13, -190($3) # encoding: [0x7c,0x6d,0xa1,0x28] + lhe $13,-256($s5) # CHECK: lhe $13, -256($21) # encoding: [0x7e,0xad,0x80,0x2d] + lhe $12,255($s0) # CHECK: lhe $12, 255($16) # encoding: [0x7e,0x0c,0x7f,0xad] + lhe $13,81($s0) # CHECK: lhe $13, 81($16) # encoding: [0x7e,0x0d,0x28,0xad] + lhue $s2,-256($v1) # CHECK: lhue $18, -256($3) # encoding: [0x7c,0x72,0x80,0x29] + lhue $s2,255($v1) # CHECK: lhue $18, 255($3) # encoding: [0x7c,0x72,0x7f,0xa9] + lhue $s6,-168($v0) # CHECK: lhue $22, -168($2) # encoding: [0x7c,0x56,0xac,0x29] + lle $v0,-256($s5) # CHECK: lle $2, -256($21) # encoding: [0x7e,0xa2,0x80,0x2e] + lle $v1,255($s3) # CHECK: lle $3, 255($19) # encoding: [0x7e,0x63,0x7f,0xae] + lle $v1,-71($s6) # CHECK: lle $3, -71($22) # encoding: [0x7e,0xc3,0xdc,0xae] + lwe $15,255($a2) # CHECK: lwe $15, 255($6) # encoding: [0x7c,0xcf,0x7f,0xaf] + lwe $13,-256($a2) # CHECK: lwe $13, -256($6) # encoding: [0x7c,0xcd,0x80,0x2f] + lwe $15,-200($a1) # CHECK: lwe $15, -200($5) # encoding: [0x7c,0xaf,0x9c,0x2f] + lwle $s6,255($15) # CHECK: lwle $22, 255($15) # encoding: [0x7d,0xf6,0x7f,0x99] + lwle $s7,-256($10) # CHECK: lwle $23, -256($10) # encoding: [0x7d,0x57,0x80,0x19] + lwle $s7,-176($13) # CHECK: lwle $23, -176($13) # encoding: [0x7d,0xb7,0xa8,0x19] + lwre $zero,255($gp) # CHECK: lwre $zero, 255($gp) # encoding: [0x7f,0x80,0x7f,0x9a] + lwre $zero,-256($gp) # CHECK: lwre $zero, -256($gp) # encoding: [0x7f,0x80,0x80,0x1a] + lwre $zero,-176($gp) # CHECK: lwre $zero, -176($gp) # encoding: [0x7f,0x80,0xa8,0x1a] + prefe 14, -256($2) # CHECK: prefe 14, -256($2) # encoding: [0x7c,0x4e,0x80,0x23] + prefe 11, 255($3) # CHECK: prefe 11, 255($3) # encoding: [0x7c,0x6b,0x7f,0xa3] + prefe 14, -37($3) # CHECK: prefe 14, -37($3) # encoding: [0x7c,0x6e,0xed,0xa3] + sbe $s1,255($11) # CHECK: sbe $17, 255($11) # encoding: [0x7d,0x71,0x7f,0x9c] + sbe $s1,-256($10) # CHECK: sbe $17, -256($10) # encoding: [0x7d,0x51,0x80,0x1c] + sbe $s3,0($14) # CHECK: sbe $19, 0($14) # encoding: [0x7d,0xd3,0x00,0x1c] + sce $9,255($s2) # CHECK: sce $9, 255($18) # encoding: [0x7e,0x49,0x7f,0x9e] + sce $12,-256($s5) # CHECK: sce $12, -256($21) # encoding: [0x7e,0xac,0x80,0x1e] + sce $13,-31($s7) # CHECK: sce $13, -31($23) # encoding: [0x7e,0xed,0xf0,0x9e] + she $14,255($15) # CHECK: she $14, 255($15) # encoding: [0x7d,0xee,0x7f,0x9d] + she $14,-256($15) # CHECK: she $14, -256($15) # encoding: [0x7d,0xee,0x80,0x1d] + she $9,235($11) # CHECK: she $9, 235($11) # encoding: [0x7d,0x69,0x75,0x9d] + swe $ra,255($sp) # CHECK: swe $ra, 255($sp) # encoding: [0x7f,0xbf,0x7f,0x9f] + swe $ra,-256($sp) # CHECK: swe $ra, -256($sp) # encoding: [0x7f,0xbf,0x80,0x1f] + swe $ra,-53($sp) # CHECK: swe $ra, -53($sp) # encoding: [0x7f,0xbf,0xe5,0x9f] + swle $9,255($s1) # CHECK: swle $9, 255($17) # encoding: [0x7e,0x29,0x7f,0xa1] + swle $10,-256($s3) # CHECK: swle $10, -256($19) # encoding: [0x7e,0x6a,0x80,0x21] + swle $8,131($s5) # CHECK: swle $8, 131($21) # encoding: [0x7e,0xa8,0x41,0xa1] + swre $s4,255($13) # CHECK: swre $20, 255($13) # encoding: [0x7d,0xb4,0x7f,0xa2] + swre $s4,-256($13) # CHECK: swre $20, -256($13) # encoding: [0x7d,0xb4,0x80,0x22] + swre $s2,86($14) # CHECK: swre $18, 86($14) # encoding: [0x7d,0xd2,0x2b,0x22] + tlbinv # CHECK: tlbinv # encoding: [0x42,0x00,0x00,0x03] + tlbinvf # CHECK: tlbinvf # encoding: [0x42,0x00,0x00,0x04] + +1: Index: test/MC/Mips/mips32/valid.s =================================================================== --- test/MC/Mips/mips32/valid.s +++ test/MC/Mips/mips32/valid.s @@ -40,7 +40,7 @@ bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 Index: test/MC/Mips/mips32r2/valid.s =================================================================== --- test/MC/Mips/mips32r2/valid.s +++ test/MC/Mips/mips32r2/valid.s @@ -40,7 +40,7 @@ bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 Index: test/MC/Mips/mips32r3/valid.s =================================================================== --- test/MC/Mips/mips32r3/valid.s +++ test/MC/Mips/mips32r3/valid.s @@ -40,7 +40,7 @@ bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 Index: test/MC/Mips/mips32r5/valid.s =================================================================== --- test/MC/Mips/mips32r5/valid.s +++ test/MC/Mips/mips32r5/valid.s @@ -40,7 +40,7 @@ bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 Index: test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s =================================================================== --- test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s +++ test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -11,7 +11,7 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips32r6/valid.s =================================================================== --- test/MC/Mips/mips32r6/valid.s +++ test/MC/Mips/mips32r6/valid.s @@ -64,7 +64,7 @@ bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25] cmp.af.s $f2,$f3,$f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] cmp.af.d $f2,$f3,$f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] Index: test/MC/Mips/mips64/valid.s =================================================================== --- test/MC/Mips/mips64/valid.s +++ test/MC/Mips/mips64/valid.s @@ -40,7 +40,7 @@ bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 Index: test/MC/Mips/mips64r2/valid.s =================================================================== --- test/MC/Mips/mips64r2/valid.s +++ test/MC/Mips/mips64r2/valid.s @@ -40,7 +40,7 @@ bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 Index: test/MC/Mips/mips64r3/valid.s =================================================================== --- test/MC/Mips/mips64r3/valid.s +++ test/MC/Mips/mips64r3/valid.s @@ -40,7 +40,7 @@ bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 Index: test/MC/Mips/mips64r5/valid.s =================================================================== --- test/MC/Mips/mips64r5/valid.s +++ test/MC/Mips/mips64r5/valid.s @@ -40,7 +40,7 @@ bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 Index: test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s =================================================================== --- test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s +++ test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s @@ -11,7 +11,7 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s =================================================================== --- test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s +++ test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s @@ -17,7 +17,7 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips64r6/valid.s =================================================================== --- test/MC/Mips/mips64r6/valid.s +++ test/MC/Mips/mips64r6/valid.s @@ -64,7 +64,7 @@ bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01] - cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]