diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -149,6 +149,9 @@ // all sizes attached to them have been eliminated. // TiedOpsRewritten: The twoaddressinstruction pass will set this flag, it // means that tied-def have been rewritten to meet the RegConstraint. + // Verifies: Means that the function is expected to pass machine verification. + // This can be cleared by passes that introduce known problems that have not + // been fixed yet. enum class Property : unsigned { IsSSA, NoPHIs, @@ -159,7 +162,8 @@ RegBankSelected, Selected, TiedOpsRewritten, - LastProperty = TiedOpsRewritten, + Verifies, + LastProperty = Verifies, }; bool hasProperty(Property P) const { diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h --- a/llvm/include/llvm/CodeGen/TargetPassConfig.h +++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h @@ -187,8 +187,7 @@ void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID); /// Insert InsertedPassID pass after TargetPassID pass. - void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, - bool VerifyAfter = true); + void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID); /// Allow the target to enable a specific standard pass by default. void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } @@ -323,8 +322,7 @@ /// Add standard passes after a pass that has just been added. For example, /// the MachineVerifier if it is enabled. - void addMachinePostPasses(const std::string &Banner, bool AllowVerify = true, - bool AllowStrip = true); + void addMachinePostPasses(const std::string &Banner); /// Check whether or not GlobalISel should abort on error. /// When this is disabled, GlobalISel will fall back on SDISel instead of @@ -449,16 +447,12 @@ /// Add a CodeGen pass at this point in the pipeline after checking overrides. /// Return the pass that was added, or zero if no pass was added. - /// @p verifyAfter if true and adding a machine function pass add an extra - /// machine verification pass afterwards. - AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true); + AnalysisID addPass(AnalysisID PassID); /// Add a pass to the PassManager if that pass is supposed to be run, as /// determined by the StartAfter and StopAfter options. Takes ownership of the /// pass. - /// @p verifyAfter if true and adding a machine function pass add an extra - /// machine verification pass afterwards. - void addPass(Pass *P, bool verifyAfter = true); + void addPass(Pass *P); /// addMachinePasses helper to create the target-selected or overriden /// regalloc pass. diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -99,6 +99,7 @@ case P::Selected: return "Selected"; case P::TracksLiveness: return "TracksLiveness"; case P::TiedOpsRewritten: return "TiedOpsRewritten"; + case P::Verifies: return "Verifies"; } llvm_unreachable("Invalid machine function property"); } @@ -156,6 +157,7 @@ // Assume the function starts in SSA form with correct liveness. Properties.set(MachineFunctionProperties::Property::IsSSA); Properties.set(MachineFunctionProperties::Property::TracksLiveness); + Properties.set(MachineFunctionProperties::Property::Verifies); if (STI->getRegisterInfo()) RegInfo = new (Allocator) MachineRegisterInfo(this); else diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -292,6 +292,13 @@ } bool runOnMachineFunction(MachineFunction &MF) override { + // Skip functions that have known verification problems. + // FIXME: Remove this mechanism when all problematic passes have been + // fixed. + if (!MF.getProperties().hasProperty( + MachineFunctionProperties::Property::Verifies)) + return false; + unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF); if (FoundErrors) report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors."); diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -361,12 +361,9 @@ struct InsertedPass { AnalysisID TargetPassID; IdentifyingPassPtr InsertedPassID; - bool VerifyAfter; - InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, - bool VerifyAfter) - : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID), - VerifyAfter(VerifyAfter) {} + InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID) + : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID) {} Pass *getInsertedPass() const { assert(InsertedPassID.isValid() && "Illegal Pass ID!"); @@ -641,14 +638,13 @@ /// Insert InsertedPassID pass after TargetPassID. void TargetPassConfig::insertPass(AnalysisID TargetPassID, - IdentifyingPassPtr InsertedPassID, - bool VerifyAfter) { + IdentifyingPassPtr InsertedPassID) { assert(((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && "Insert a pass after itself!"); - Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter); + Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID); } /// createPassConfig - Create a pass configuration object to be used by @@ -726,7 +722,7 @@ /// a later pass or that it should stop after an earlier pass, then do not add /// the pass. Finally, compare the current pass against the StartAfter /// and StopAfter options and change the Started/Stopped flags accordingly. -void TargetPassConfig::addPass(Pass *P, bool verifyAfter) { +void TargetPassConfig::addPass(Pass *P) { assert(!Initialized && "PassConfig is immutable"); // Cache the Pass ID here in case the pass manager finds this pass is @@ -744,16 +740,16 @@ addMachinePrePasses(); std::string Banner; // Construct banner message before PM->add() as that may delete the pass. - if (AddingMachinePasses && verifyAfter) + if (AddingMachinePasses) Banner = std::string("After ") + std::string(P->getPassName()); PM->add(P); if (AddingMachinePasses) - addMachinePostPasses(Banner, /*AllowVerify*/ verifyAfter); + addMachinePostPasses(Banner); // Add the passes after the pass P if there is any. for (const auto &IP : Impl->InsertedPasses) { if (IP.TargetPassID == PassID) - addPass(IP.getInsertedPass(), IP.VerifyAfter); + addPass(IP.getInsertedPass()); } } else { delete P; @@ -773,7 +769,7 @@ /// /// addPass cannot return a pointer to the pass instance because is internal the /// PassManager and the instance we create here may already be freed. -AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter) { +AnalysisID TargetPassConfig::addPass(AnalysisID PassID) { IdentifyingPassPtr TargetID = getPassSubstitution(PassID); IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID); if (!FinalPtr.isValid()) @@ -788,7 +784,7 @@ llvm_unreachable("Pass ID not registered"); } AnalysisID FinalID = P->getPassID(); - addPass(P, verifyAfter); // Ends the lifetime of P. + addPass(P); // Ends the lifetime of P. return FinalID; } @@ -832,8 +828,7 @@ addDebugifyPass(); } -void TargetPassConfig::addMachinePostPasses(const std::string &Banner, - bool AllowVerify, bool AllowStrip) { +void TargetPassConfig::addMachinePostPasses(const std::string &Banner) { if (DebugifyIsSafe) { if (DebugifyCheckAndStripAll == cl::BOU_TRUE) { addCheckDebugPass(); @@ -841,8 +836,7 @@ } else if (DebugifyAndStripAll == cl::BOU_TRUE) addStripDebugPass(); } - if (AllowVerify) - addVerifyPass(Banner); + addVerifyPass(Banner); } /// Add common target configurable passes that perform LLVM IR to IR transforms @@ -1247,10 +1241,10 @@ // FIXME: Some backends are incompatible with running the verifier after // addPreEmitPass. Maybe only pass "false" here for those targets? - addPass(&FuncletLayoutID, false); + addPass(&FuncletLayoutID); - addPass(&StackMapLivenessID, false); - addPass(&LiveDebugValuesID, false); + addPass(&StackMapLivenessID); + addPass(&LiveDebugValuesID); if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None && EnableMachineOutliner != RunOutliner::NeverOutline) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -1171,7 +1171,7 @@ // This must be run immediately after phi elimination and before // TwoAddressInstructions, otherwise the processing of the tied operand of // SI_ELSE will introduce a copy of the tied operand source after the else. - insertPass(&PHIEliminationID, &SILowerControlFlowID, false); + insertPass(&PHIEliminationID, &SILowerControlFlowID); insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID); insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID); @@ -1201,11 +1201,11 @@ // the register in LiveVariables, this would trigger a failure in verifier, // we should fix it and enable the verifier. if (OptVGPRLiveRange) - insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID, false); + insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID); // This must be run immediately after phi elimination and before // TwoAddressInstructions, otherwise the processing of the tied operand of // SI_ELSE will introduce a copy of the tied operand source after the else. - insertPass(&PHIEliminationID, &SILowerControlFlowID, false); + insertPass(&PHIEliminationID, &SILowerControlFlowID); if (EnableDCEInRA) insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID); diff --git a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp --- a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp @@ -127,6 +127,9 @@ bool prepare(); bool runOnMachineFunction(MachineFunction &MF) override { + // FIXME: This pass causes verification failures. + MF.getProperties().reset(MachineFunctionProperties::Property::Verifies); + TII = MF.getSubtarget().getInstrInfo(); TRI = &TII->getRegisterInfo(); LLVM_DEBUG(MF.dump();); diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp --- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp @@ -124,18 +124,18 @@ void R600PassConfig::addPreRegAlloc() { addPass(createR600VectorRegMerger()); } void R600PassConfig::addPreSched2() { - addPass(createR600EmitClauseMarkers(), false); + addPass(createR600EmitClauseMarkers()); if (EnableR600IfConvert) - addPass(&IfConverterID, false); - addPass(createR600ClauseMergePass(), false); + addPass(&IfConverterID); + addPass(createR600ClauseMergePass()); } void R600PassConfig::addPreEmitPass() { - addPass(createAMDGPUCFGStructurizerPass(), false); - addPass(createR600ExpandSpecialInstrsPass(), false); - addPass(&FinalizeMachineBundlesID, false); - addPass(createR600Packetizer(), false); - addPass(createR600ControlFlowFinalizer(), false); + addPass(createAMDGPUCFGStructurizerPass()); + addPass(createR600ExpandSpecialInstrsPass()); + addPass(&FinalizeMachineBundlesID); + addPass(createR600Packetizer()); + addPass(createR600ControlFlowFinalizer()); } TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) { diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -787,6 +787,9 @@ } bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) { + // FIXME: This pass causes verification failures. + MF.getProperties().reset(MachineFunctionProperties::Property::Verifies); + const GCNSubtarget &ST = MF.getSubtarget(); TII = ST.getInstrInfo(); TRI = &TII->getRegisterInfo(); diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -1498,6 +1498,10 @@ } bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) { + // This pass is a convenient place to re-enable machine verification after the + // problems caused by SILowerControlFlow have been fixed. + MF.getProperties().set(MachineFunctionProperties::Property::Verifies); + LLVM_DEBUG(dbgs() << "SI Whole Quad Mode on " << MF.getName() << " ------------- \n"); LLVM_DEBUG(MF.dump();); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -447,11 +447,11 @@ } // Packetization is mandatory: it handles gather/scatter at all opt levels. - addPass(createHexagonPacketizer(NoOpt), false); + addPass(createHexagonPacketizer(NoOpt)); if (EnableVectorPrint) - addPass(createHexagonVectorPrint(), false); + addPass(createHexagonVectorPrint()); // Add CFI instructions if necessary. - addPass(createHexagonCallFrameInformation(), false); + addPass(createHexagonCallFrameInformation()); } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -203,6 +203,9 @@ } bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) { + // FIXME: This pass causes verification failures. + MF.getProperties().reset(MachineFunctionProperties::Property::Verifies); + auto &HST = MF.getSubtarget(); HII = HST.getInstrInfo(); HRI = HST.getRegisterInfo(); diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -81,5 +81,5 @@ void MSP430PassConfig::addPreEmitPass() { // Must run branch selection immediately preceding the asm printer. - addPass(createMSP430BranchSelectionPass(), false); + addPass(createMSP430BranchSelectionPass()); } diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -350,7 +350,7 @@ } void NVPTXPassConfig::addPostRegAlloc() { - addPass(createNVPTXPrologEpilogPass(), false); + addPass(createNVPTXPrologEpilogPass()); if (getOptLevel() != CodeGenOpt::None) { // NVPTXPrologEpilogPass calculates frame object offset and replace frame // index with VRFrame register. NVPTXPeephole need to be run after that and diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -285,7 +285,7 @@ // vector instructions will be shortened into opcodes that compare // elimination recognizes. if (getOptLevel() != CodeGenOpt::None) - addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false); + addPass(createSystemZShortenInstPass(getSystemZTargetMachine())); // We eliminate comparisons here rather than earlier because some // transformations can change the set of available CC values and we @@ -311,7 +311,7 @@ // between the comparison and the branch, but it isn't clear whether // preventing that would be a win or not. if (getOptLevel() != CodeGenOpt::None) - addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false); + addPass(createSystemZElimComparePass(getSystemZTargetMachine())); addPass(createSystemZLongBranchPass(getSystemZTargetMachine())); // Do final scheduling after all other optimizations, to get an diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -99,7 +99,7 @@ } void XCorePassConfig::addPreEmitPass() { - addPass(createXCoreFrameToArgsOffsetEliminationPass(), false); + addPass(createXCoreFrameToArgsOffsetEliminationPass()); } // Force static initialization.