diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h --- a/clang/lib/Basic/Targets/RISCV.h +++ b/clang/lib/Basic/Targets/RISCV.h @@ -30,7 +30,6 @@ bool HasF = false; bool HasD = false; bool HasC = false; - bool HasB = false; bool HasV = false; bool HasZba = false; bool HasZbb = false; diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -176,11 +176,6 @@ Builder.defineMacro("__riscv_compressed"); } - if (HasB) { - Builder.defineMacro("__riscv_b", "93000"); - Builder.defineMacro("__riscv_bitmanip"); - } - if (HasV) { Builder.defineMacro("__riscv_v", "10000"); Builder.defineMacro("__riscv_vector"); @@ -262,7 +257,6 @@ .Case("f", HasF) .Case("d", HasD) .Case("c", HasC) - .Case("experimental-b", HasB) .Case("experimental-v", HasV) .Case("experimental-zba", HasZba) .Case("experimental-zbb", HasZbb) @@ -294,8 +288,6 @@ HasD = true; else if (Feature == "+c") HasC = true; - else if (Feature == "+experimental-b") - HasB = true; else if (Feature == "+experimental-v") HasV = true; else if (Feature == "+experimental-zba") diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -58,9 +58,9 @@ // extension that the compiler currently supports. static Optional isExperimentalExtension(StringRef Ext) { - if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" || - Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || - Ext == "zbr" || Ext == "zbs" || Ext == "zbt") + if (Ext == "zba" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" || + Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" || + Ext == "zbs" || Ext == "zbt") return RISCVExtensionVersion{"0", "93"}; if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg") return RISCVExtensionVersion{"0", "10"}; @@ -417,19 +417,6 @@ case 'c': Features.push_back("+c"); break; - case 'b': - Features.push_back("+experimental-b"); - Features.push_back("+experimental-zba"); - Features.push_back("+experimental-zbb"); - Features.push_back("+experimental-zbc"); - Features.push_back("+experimental-zbe"); - Features.push_back("+experimental-zbf"); - Features.push_back("+experimental-zbm"); - Features.push_back("+experimental-zbp"); - Features.push_back("+experimental-zbr"); - Features.push_back("+experimental-zbs"); - Features.push_back("+experimental-zbt"); - break; case 'v': Features.push_back("+experimental-v"); Features.push_back("+experimental-zvlsseg"); diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -382,25 +382,6 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf" -// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s -// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib' -// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' - -// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s -// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib' -// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number - -// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s -// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1' -// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension - -// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p93 -menable-experimental-extensions -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s -// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-b" - // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s // RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb' diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -99,25 +99,6 @@ // CHECK-C-EXT: __riscv_c 2000000 // CHECK-C-EXT: __riscv_compressed 1 -// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32ib0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s -// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64ib0p93 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s -// CHECK-B-EXT: __riscv_b 93000 -// CHECK-B-EXT: __riscv_bitmanip 1 -// CHECK-B-EXT: __riscv_zba 93000 -// CHECK-B-EXT: __riscv_zbb 93000 -// CHECK-B-EXT: __riscv_zbc 93000 -// CHECK-B-EXT: __riscv_zbe 93000 -// CHECK-B-EXT: __riscv_zbf 93000 -// CHECK-B-EXT: __riscv_zbm 93000 -// CHECK-B-EXT: __riscv_zbp 93000 -// CHECK-B-EXT: __riscv_zbr 93000 -// CHECK-B-EXT: __riscv_zbs 93000 -// CHECK-B-EXT: __riscv_zbt 93000 - // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ // RUN: -march=rv32izba0p93 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2068,7 +2068,6 @@ clearFeatureBits(RISCV::FeatureStdExtF, "f"); clearFeatureBits(RISCV::FeatureStdExtD, "d"); clearFeatureBits(RISCV::FeatureStdExtC, "c"); - clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b"); clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v"); clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh"); clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba"); @@ -2107,8 +2106,6 @@ setFeatureBits(RISCV::FeatureStdExtD, "d"); } else if (Arch[0] == 'c') { setFeatureBits(RISCV::FeatureStdExtC, "c"); - } else if (Arch[0] == 'b') { - setFeatureBits(RISCV::FeatureStdExtB, "experimental-b"); } else if (Arch[0] == 'v') { setFeatureBits(RISCV::FeatureStdExtV, "experimental-v"); } else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') { @@ -2182,8 +2179,6 @@ formalArchStr = (Twine(formalArchStr) + "_d2p0").str(); if (getFeatureBits(RISCV::FeatureStdExtC)) formalArchStr = (Twine(formalArchStr) + "_c2p0").str(); - if (getFeatureBits(RISCV::FeatureStdExtB)) - formalArchStr = (Twine(formalArchStr) + "_b0p93").str(); if (getFeatureBits(RISCV::FeatureStdExtV)) formalArchStr = (Twine(formalArchStr) + "_v0p10").str(); if (getFeatureBits(RISCV::FeatureStdExtZfh)) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -60,8 +60,6 @@ Arch += "_d2p0"; if (STI.hasFeature(RISCV::FeatureStdExtC)) Arch += "_c2p0"; - if (STI.hasFeature(RISCV::FeatureStdExtB)) - Arch += "_b0p93"; if (STI.hasFeature(RISCV::FeatureStdExtV)) Arch += "_v0p10"; if (STI.hasFeature(RISCV::FeatureStdExtZfh)) diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -135,23 +135,6 @@ "'Zbb' (Base 'B' Instructions) or " "'Zbp' (Permutation 'B' Instructions)">; -def FeatureStdExtB - : SubtargetFeature<"experimental-b", "HasStdExtB", "true", - "'B' (Bit Manipulation Instructions)", - [FeatureStdExtZba, - FeatureStdExtZbb, - FeatureStdExtZbc, - FeatureStdExtZbe, - FeatureStdExtZbf, - FeatureStdExtZbm, - FeatureStdExtZbp, - FeatureStdExtZbr, - FeatureStdExtZbs, - FeatureStdExtZbt]>; -def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, - AssemblerPredicate<(all_of FeatureStdExtB), - "'B' (Bit Manipulation Instructions)">; - def FeatureNoRVCHints : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", "Disable RVC Hint Instructions.">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1460,6 +1460,6 @@ include "RISCVInstrInfoF.td" include "RISCVInstrInfoD.td" include "RISCVInstrInfoC.td" -include "RISCVInstrInfoB.td" +include "RISCVInstrInfoZb.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZfh.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td rename from llvm/lib/Target/RISCV/RISCVInstrInfoB.td rename to llvm/lib/Target/RISCV/RISCVInstrInfoZb.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -1,4 +1,4 @@ -//===-- RISCVInstrInfoB.td - RISC-V 'B' instructions -------*- tablegen -*-===// +//===-- RISCVInstrInfoZb.td - RISC-V Bitmanip instructions -*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,9 +6,9 @@ // //===----------------------------------------------------------------------===// // -// This file describes the RISC-V instructions from the standard 'B' Bitmanip -// extension, version 0.93. -// This version is still experimental as the 'B' extension hasn't been +// This file describes the RISC-V instructions from the standard Bitmanip +// extensions, version 0.93. +// This version is still experimental as the Bitmanip extensions haven't been // ratified yet. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -39,7 +39,6 @@ bool HasStdExtF = false; bool HasStdExtD = false; bool HasStdExtC = false; - bool HasStdExtB = false; bool HasStdExtZba = false; bool HasStdExtZbb = false; bool HasStdExtZbc = false; @@ -106,7 +105,6 @@ bool hasStdExtF() const { return HasStdExtF; } bool hasStdExtD() const { return HasStdExtD; } bool hasStdExtC() const { return HasStdExtC; } - bool hasStdExtB() const { return HasStdExtB; } bool hasStdExtZba() const { return HasStdExtZba; } bool hasStdExtZbb() const { return HasStdExtZbb; } bool hasStdExtZbc() const { return HasStdExtZbc; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -5,7 +5,6 @@ ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV32B %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32V %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s @@ -24,7 +23,6 @@ ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s @@ -44,7 +42,6 @@ ; RV32F: .attribute 5, "rv32i2p0_f2p0" ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32C: .attribute 5, "rv32i2p0_c2p0" -; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93" ; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1" ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93" @@ -64,7 +61,6 @@ ; RV64F: .attribute 5, "rv64i2p0_f2p0" ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64C: .attribute 5, "rv64i2p0_c2p0" -; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93" ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1" ; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93" ; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93" diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll --- a/llvm/test/CodeGen/RISCV/rv32zba.ll +++ b/llvm/test/CodeGen/RISCV/rv32zba.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBA @@ -14,12 +12,6 @@ ; RV32I-NEXT: lh a0, 0(a0) ; RV32I-NEXT: ret ; -; RV32B-LABEL: sh1add: -; RV32B: # %bb.0: -; RV32B-NEXT: sh1add a0, a0, a2 -; RV32B-NEXT: lh a0, 0(a0) -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: sh1add: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a2 @@ -38,12 +30,6 @@ ; RV32I-NEXT: lw a0, 0(a0) ; RV32I-NEXT: ret ; -; RV32B-LABEL: sh2add: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a0, a0, a2 -; RV32B-NEXT: lw a0, 0(a0) -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: sh2add: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a2 @@ -63,13 +49,6 @@ ; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: ret ; -; RV32B-LABEL: sh3add: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a1, a0, a2 -; RV32B-NEXT: lw a0, 0(a1) -; RV32B-NEXT: lw a1, 4(a1) -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: sh3add: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a1, a0, a2 @@ -89,12 +68,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul6: -; RV32B: # %bb.0: -; RV32B-NEXT: sh1add a0, a0, a0 -; RV32B-NEXT: sh1add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul6: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a0 @@ -113,12 +86,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul10: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a0, a0, a0 -; RV32B-NEXT: sh1add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul10: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a0 @@ -137,12 +104,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul12: -; RV32B: # %bb.0: -; RV32B-NEXT: sh1add a0, a0, a0 -; RV32B-NEXT: sh2add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul12: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a0 @@ -161,12 +122,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul18: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a0, a0, a0 -; RV32B-NEXT: sh1add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul18: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 @@ -185,12 +140,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul20: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a0, a0, a0 -; RV32B-NEXT: sh2add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul20: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a0 @@ -209,12 +158,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul24: -; RV32B: # %bb.0: -; RV32B-NEXT: sh1add a0, a0, a0 -; RV32B-NEXT: sh3add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul24: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a0 @@ -233,12 +176,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul36: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a0, a0, a0 -; RV32B-NEXT: sh2add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul36: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 @@ -257,12 +194,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul40: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a0, a0, a0 -; RV32B-NEXT: sh3add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul40: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a0 @@ -281,12 +212,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addmul72: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a0, a0, a0 -; RV32B-NEXT: sh3add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addmul72: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 @@ -304,12 +229,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul96: -; RV32B: # %bb.0: -; RV32B-NEXT: sh1add a0, a0, a0 -; RV32B-NEXT: slli a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul96: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a0, a0 @@ -326,12 +245,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul160: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a0, a0, a0 -; RV32B-NEXT: slli a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul160: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a0, a0 @@ -348,12 +261,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul288: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a0, a0, a0 -; RV32B-NEXT: slli a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul288: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 @@ -370,12 +277,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul258: -; RV32B: # %bb.0: -; RV32B-NEXT: addi a1, zero, 258 -; RV32B-NEXT: mul a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul258: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 258 @@ -392,12 +293,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul260: -; RV32B: # %bb.0: -; RV32B-NEXT: addi a1, zero, 260 -; RV32B-NEXT: mul a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul260: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 260 @@ -414,12 +309,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul264: -; RV32B: # %bb.0: -; RV32B-NEXT: addi a1, zero, 264 -; RV32B-NEXT: mul a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul264: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 264 @@ -436,12 +325,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul11: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a1, a0, a0 -; RV32B-NEXT: sh1add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul11: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a1, a0, a0 @@ -458,12 +341,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul19: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a1, a0, a0 -; RV32B-NEXT: sh1add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul19: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a1, a0, a0 @@ -480,12 +357,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul13: -; RV32B: # %bb.0: -; RV32B-NEXT: sh1add a1, a0, a0 -; RV32B-NEXT: sh2add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul13: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a1, a0, a0 @@ -502,12 +373,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul21: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a1, a0, a0 -; RV32B-NEXT: sh2add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul21: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a1, a0, a0 @@ -524,12 +389,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul37: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a1, a0, a0 -; RV32B-NEXT: sh2add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul37: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a1, a0, a0 @@ -546,12 +405,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul25: -; RV32B: # %bb.0: -; RV32B-NEXT: sh1add a1, a0, a0 -; RV32B-NEXT: sh3add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul25: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a1, a0, a0 @@ -568,12 +421,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul41: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a1, a0, a0 -; RV32B-NEXT: sh3add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul41: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a1, a0, a0 @@ -590,12 +437,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul73: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a1, a0, a0 -; RV32B-NEXT: sh3add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul73: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a1, a0, a0 @@ -612,12 +453,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul27: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a0, a0, a0 -; RV32B-NEXT: sh1add a0, a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul27: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 @@ -634,12 +469,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul45: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a0, a0, a0 -; RV32B-NEXT: sh2add a0, a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul45: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 @@ -656,12 +485,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul81: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a0, a0, a0 -; RV32B-NEXT: sh3add a0, a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul81: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a0, a0 @@ -679,12 +502,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul4098: -; RV32B: # %bb.0: -; RV32B-NEXT: slli a1, a0, 12 -; RV32B-NEXT: sh1add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul4098: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: slli a1, a0, 12 @@ -702,12 +519,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul4100: -; RV32B: # %bb.0: -; RV32B-NEXT: slli a1, a0, 12 -; RV32B-NEXT: sh2add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul4100: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: slli a1, a0, 12 @@ -725,12 +536,6 @@ ; RV32I-NEXT: mul a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: mul4104: -; RV32B: # %bb.0: -; RV32B-NEXT: slli a1, a0, 12 -; RV32B-NEXT: sh3add a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: mul4104: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: slli a1, a0, 12 @@ -748,12 +553,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: add4104: -; RV32B: # %bb.0: -; RV32B-NEXT: addi a1, zero, 1026 -; RV32B-NEXT: sh2add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: add4104: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 1026 @@ -771,12 +570,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: add8208: -; RV32B: # %bb.0: -; RV32B-NEXT: addi a1, zero, 1026 -; RV32B-NEXT: sh3add a0, a1, a0 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: add8208: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: addi a1, zero, 1026 @@ -794,12 +587,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addshl_5_6: -; RV32B: # %bb.0: -; RV32B-NEXT: sh1add a0, a1, a0 -; RV32B-NEXT: slli a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addshl_5_6: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh1add a0, a1, a0 @@ -819,12 +606,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addshl_5_7: -; RV32B: # %bb.0: -; RV32B-NEXT: sh2add a0, a1, a0 -; RV32B-NEXT: slli a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addshl_5_7: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh2add a0, a1, a0 @@ -844,12 +625,6 @@ ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: addshl_5_8: -; RV32B: # %bb.0: -; RV32B-NEXT: sh3add a0, a1, a0 -; RV32B-NEXT: slli a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBA-LABEL: addshl_5_8: ; RV32ZBA: # %bb.0: ; RV32ZBA-NEXT: sh3add a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll --- a/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll @@ -1,17 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBB declare i32 @llvm.riscv.orc.b.i32(i32) define i32 @orcb(i32 %a) nounwind { -; RV32B-LABEL: orcb: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: orcb: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: orc.b a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll --- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBB ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ @@ -15,11 +13,6 @@ ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: andn_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: andn a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: andn_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: andn a0, a0, a1 @@ -43,12 +36,6 @@ ; RV32I-NEXT: and a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: andn_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: andn a0, a0, a2 -; RV32B-NEXT: andn a1, a1, a3 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: andn_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: andn a0, a0, a2 @@ -72,11 +59,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: orn_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orn a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: orn_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: orn a0, a0, a1 @@ -100,12 +82,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: orn_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orn a0, a0, a2 -; RV32B-NEXT: orn a1, a1, a3 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: orn_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: orn a0, a0, a2 @@ -129,11 +105,6 @@ ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: xnor_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: xnor a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: xnor_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: xnor a0, a0, a1 @@ -157,12 +128,6 @@ ; RV32I-NEXT: not a1, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: xnor_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: xnor a0, a0, a2 -; RV32B-NEXT: xnor a1, a1, a3 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: xnor_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: xnor a0, a0, a2 @@ -190,11 +155,6 @@ ; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: rol_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rol a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: rol_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: rol a0, a0, a1 @@ -208,8 +168,6 @@ ret i32 %or } -; As we are not matching directly i64 code patterns on RV32 some i64 patterns -; don't have yet any matching bit manipulation instructions on RV32. ; This test is presented here in case future expansions of the experimental-b ; extension introduce instructions suitable for this pattern. @@ -257,41 +215,6 @@ ; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: ret ; -; RV32B-LABEL: rol_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: sll a7, a1, a2 -; RV32B-NEXT: andi a4, a2, 63 -; RV32B-NEXT: addi a6, zero, 31 -; RV32B-NEXT: sub a5, a6, a4 -; RV32B-NEXT: srli a3, a0, 1 -; RV32B-NEXT: srl a3, a3, a5 -; RV32B-NEXT: or a7, a7, a3 -; RV32B-NEXT: addi t1, a4, -32 -; RV32B-NEXT: sll a5, a0, t1 -; RV32B-NEXT: slti a3, t1, 0 -; RV32B-NEXT: cmov a7, a3, a7, a5 -; RV32B-NEXT: neg a5, a2 -; RV32B-NEXT: srl t0, a1, a5 -; RV32B-NEXT: andi t2, a5, 63 -; RV32B-NEXT: addi a4, t2, -32 -; RV32B-NEXT: srai a3, a4, 31 -; RV32B-NEXT: and a3, a3, t0 -; RV32B-NEXT: or a7, a7, a3 -; RV32B-NEXT: srl t0, a0, a5 -; RV32B-NEXT: sub a5, a6, t2 -; RV32B-NEXT: slli a3, a1, 1 -; RV32B-NEXT: sll a3, a3, a5 -; RV32B-NEXT: or a3, t0, a3 -; RV32B-NEXT: srl a1, a1, a4 -; RV32B-NEXT: slti a4, a4, 0 -; RV32B-NEXT: cmov a1, a4, a3, a1 -; RV32B-NEXT: sll a0, a0, a2 -; RV32B-NEXT: srai a2, t1, 31 -; RV32B-NEXT: and a0, a2, a0 -; RV32B-NEXT: or a0, a0, a1 -; RV32B-NEXT: mv a1, a7 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: rol_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: mv a7, a1 @@ -388,11 +311,6 @@ ; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: ror_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: ror a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: ror_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: ror a0, a0, a1 @@ -406,8 +324,6 @@ ret i32 %or } -; As we are not matching directly i64 code patterns on RV32 some i64 patterns -; don't have yet any matching bit manipulation instructions on RV32. ; This test is presented here in case future expansions of the experimental-b ; extension introduce instructions suitable for this pattern. @@ -455,41 +371,6 @@ ; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: ret ; -; RV32B-LABEL: ror_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: srl a7, a0, a2 -; RV32B-NEXT: andi a4, a2, 63 -; RV32B-NEXT: addi a6, zero, 31 -; RV32B-NEXT: sub a5, a6, a4 -; RV32B-NEXT: slli a3, a1, 1 -; RV32B-NEXT: sll a3, a3, a5 -; RV32B-NEXT: or a7, a7, a3 -; RV32B-NEXT: addi t1, a4, -32 -; RV32B-NEXT: srl a5, a1, t1 -; RV32B-NEXT: slti a3, t1, 0 -; RV32B-NEXT: cmov a7, a3, a7, a5 -; RV32B-NEXT: neg a5, a2 -; RV32B-NEXT: sll t0, a0, a5 -; RV32B-NEXT: andi t2, a5, 63 -; RV32B-NEXT: addi a4, t2, -32 -; RV32B-NEXT: srai a3, a4, 31 -; RV32B-NEXT: and a3, a3, t0 -; RV32B-NEXT: or a7, a7, a3 -; RV32B-NEXT: sll t0, a1, a5 -; RV32B-NEXT: sub a5, a6, t2 -; RV32B-NEXT: srli a3, a0, 1 -; RV32B-NEXT: srl a3, a3, a5 -; RV32B-NEXT: or a3, t0, a3 -; RV32B-NEXT: sll a0, a0, a4 -; RV32B-NEXT: slti a4, a4, 0 -; RV32B-NEXT: cmov a0, a4, a3, a0 -; RV32B-NEXT: srl a1, a1, a2 -; RV32B-NEXT: srai a2, t1, 31 -; RV32B-NEXT: and a1, a2, a1 -; RV32B-NEXT: or a1, a1, a0 -; RV32B-NEXT: mv a0, a7 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: ror_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: mv t0, a0 @@ -583,11 +464,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: rori_i32_fshl: -; RV32B: # %bb.0: -; RV32B-NEXT: rori a0, a0, 1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: rori_i32_fshl: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: rori a0, a0, 1 @@ -609,11 +485,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: rori_i32_fshr: -; RV32B: # %bb.0: -; RV32B-NEXT: rori a0, a0, 31 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: rori_i32_fshr: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: rori a0, a0, 31 @@ -639,13 +510,6 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: rori_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: fsri a2, a0, a1, 1 -; RV32B-NEXT: fsri a1, a1, a0, 1 -; RV32B-NEXT: mv a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: rori_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: slli a2, a1, 31 @@ -683,13 +547,6 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: rori_i64_fshr: -; RV32B: # %bb.0: -; RV32B-NEXT: fsri a2, a1, a0, 31 -; RV32B-NEXT: fsri a1, a0, a1, 31 -; RV32B-NEXT: mv a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: rori_i64_fshr: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: slli a2, a0, 1 @@ -722,12 +579,6 @@ ; RV32I-NEXT: srli a0, a0, 6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: srli_i8: -; RV32B: # %bb.0: -; RV32B-NEXT: andi a0, a0, 192 -; RV32B-NEXT: srli a0, a0, 6 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: srli_i8: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: andi a0, a0, 192 @@ -750,12 +601,6 @@ ; RV32I-NEXT: srai a0, a0, 29 ; RV32I-NEXT: ret ; -; RV32B-LABEL: srai_i8: -; RV32B: # %bb.0: -; RV32B-NEXT: sext.b a0, a0 -; RV32B-NEXT: srai a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: srai_i8: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: sext.b a0, a0 @@ -778,12 +623,6 @@ ; RV32I-NEXT: srli a0, a0, 22 ; RV32I-NEXT: ret ; -; RV32B-LABEL: srli_i16: -; RV32B: # %bb.0: -; RV32B-NEXT: zext.h a0, a0 -; RV32B-NEXT: srli a0, a0, 6 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: srli_i16: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: zext.h a0, a0 @@ -806,12 +645,6 @@ ; RV32I-NEXT: srai a0, a0, 25 ; RV32I-NEXT: ret ; -; RV32B-LABEL: srai_i16: -; RV32B: # %bb.0: -; RV32B-NEXT: sext.h a0, a0 -; RV32B-NEXT: srai a0, a0, 9 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: srai_i16: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: sext.h a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll --- a/llvm/test/CodeGen/RISCV/rv32zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBB @@ -53,11 +51,6 @@ ; RV32I-NEXT: addi a0, zero, 32 ; RV32I-NEXT: ret ; -; RV32B-LABEL: ctlz_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: clz a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: ctlz_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: clz a0, a0 @@ -157,15 +150,6 @@ ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32B-LABEL: ctlz_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: clz a2, a1 -; RV32B-NEXT: clz a0, a0 -; RV32B-NEXT: addi a0, a0, 32 -; RV32B-NEXT: cmov a0, a1, a2, a0 -; RV32B-NEXT: mv a1, zero -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: ctlz_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: bnez a1, .LBB1_2 @@ -221,11 +205,6 @@ ; RV32I-NEXT: addi a0, zero, 32 ; RV32I-NEXT: ret ; -; RV32B-LABEL: cttz_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: ctz a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: cttz_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: ctz a0, a0 @@ -309,15 +288,6 @@ ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32B-LABEL: cttz_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: ctz a2, a0 -; RV32B-NEXT: ctz a1, a1 -; RV32B-NEXT: addi a1, a1, 32 -; RV32B-NEXT: cmov a0, a0, a2, a1 -; RV32B-NEXT: mv a1, zero -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: cttz_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: bnez a0, .LBB3_2 @@ -365,11 +335,6 @@ ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32B-LABEL: ctpop_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: cpop a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: ctpop_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: cpop a0, a0 @@ -438,14 +403,6 @@ ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32B-LABEL: ctpop_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: cpop a1, a1 -; RV32B-NEXT: cpop a0, a0 -; RV32B-NEXT: add a0, a0, a1 -; RV32B-NEXT: mv a1, zero -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: ctpop_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: cpop a1, a1 @@ -464,11 +421,6 @@ ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sextb_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: sext.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: sextb_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: sext.b a0, a0 @@ -486,12 +438,6 @@ ; RV32I-NEXT: srai a1, a1, 31 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sextb_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: sext.b a0, a0 -; RV32B-NEXT: srai a1, a0, 31 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: sextb_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: sext.b a0, a0 @@ -509,11 +455,6 @@ ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sexth_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: sext.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: sexth_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: sext.h a0, a0 @@ -531,12 +472,6 @@ ; RV32I-NEXT: srai a1, a1, 31 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sexth_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: sext.h a0, a0 -; RV32B-NEXT: srai a1, a0, 31 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: sexth_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: sext.h a0, a0 @@ -556,11 +491,6 @@ ; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: min_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: min a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: min_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: min a0, a0, a1 @@ -592,16 +522,6 @@ ; RV32I-NEXT: .LBB11_4: ; RV32I-NEXT: ret ; -; RV32B-LABEL: min_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: slt a4, a1, a3 -; RV32B-NEXT: cmov a4, a4, a0, a2 -; RV32B-NEXT: minu a0, a0, a2 -; RV32B-NEXT: xor a2, a1, a3 -; RV32B-NEXT: cmov a0, a2, a4, a0 -; RV32B-NEXT: min a1, a1, a3 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: min_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: mv a4, a0 @@ -632,11 +552,6 @@ ; RV32I-NEXT: .LBB12_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: max_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: max a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: max_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: max a0, a0, a1 @@ -668,16 +583,6 @@ ; RV32I-NEXT: .LBB13_4: ; RV32I-NEXT: ret ; -; RV32B-LABEL: max_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: slt a4, a3, a1 -; RV32B-NEXT: cmov a4, a4, a0, a2 -; RV32B-NEXT: maxu a0, a0, a2 -; RV32B-NEXT: xor a2, a1, a3 -; RV32B-NEXT: cmov a0, a2, a4, a0 -; RV32B-NEXT: max a1, a1, a3 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: max_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: mv a4, a0 @@ -708,11 +613,6 @@ ; RV32I-NEXT: .LBB14_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: minu_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: minu a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: minu_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: minu a0, a0, a1 @@ -744,16 +644,6 @@ ; RV32I-NEXT: .LBB15_4: ; RV32I-NEXT: ret ; -; RV32B-LABEL: minu_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: sltu a4, a1, a3 -; RV32B-NEXT: cmov a4, a4, a0, a2 -; RV32B-NEXT: minu a0, a0, a2 -; RV32B-NEXT: xor a2, a1, a3 -; RV32B-NEXT: cmov a0, a2, a4, a0 -; RV32B-NEXT: minu a1, a1, a3 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: minu_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: mv a4, a0 @@ -784,11 +674,6 @@ ; RV32I-NEXT: .LBB16_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: maxu_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: maxu a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: maxu_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: maxu a0, a0, a1 @@ -820,16 +705,6 @@ ; RV32I-NEXT: .LBB17_4: ; RV32I-NEXT: ret ; -; RV32B-LABEL: maxu_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: sltu a4, a3, a1 -; RV32B-NEXT: cmov a4, a4, a0, a2 -; RV32B-NEXT: maxu a0, a0, a2 -; RV32B-NEXT: xor a2, a1, a3 -; RV32B-NEXT: cmov a0, a2, a4, a0 -; RV32B-NEXT: maxu a1, a1, a3 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: maxu_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: mv a4, a0 @@ -861,12 +736,6 @@ ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: abs_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: neg a1, a0 -; RV32B-NEXT: max a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: abs_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: neg a1, a0 @@ -890,18 +759,6 @@ ; RV32I-NEXT: .LBB19_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: abs_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: neg a2, a0 -; RV32B-NEXT: slti a3, a1, 0 -; RV32B-NEXT: cmov a2, a3, a2, a0 -; RV32B-NEXT: snez a0, a0 -; RV32B-NEXT: add a0, a1, a0 -; RV32B-NEXT: neg a0, a0 -; RV32B-NEXT: cmov a1, a3, a0, a1 -; RV32B-NEXT: mv a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: abs_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: bgez a1, .LBB19_2 @@ -924,11 +781,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: zexth_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: zext.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: zexth_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: zext.h a0, a0 @@ -946,12 +798,6 @@ ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: ret ; -; RV32B-LABEL: zexth_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: zext.h a0, a0 -; RV32B-NEXT: mv a1, zero -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: zexth_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: zext.h a0, a0 @@ -980,11 +826,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bswap_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8 a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: bswap_i32: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: rev8 a0, a0 @@ -1022,13 +863,6 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bswap_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8 a2, a1 -; RV32B-NEXT: rev8 a1, a0 -; RV32B-NEXT: mv a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBB-LABEL: bswap_i64: ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: rev8 a2, a1 diff --git a/llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll --- a/llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll @@ -1,17 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBC declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b) define i32 @clmul32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: clmul32: -; RV32B: # %bb.0: -; RV32B-NEXT: clmul a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBC-LABEL: clmul32: ; RV32ZBC: # %bb.0: ; RV32ZBC-NEXT: clmul a0, a0, a1 @@ -23,11 +16,6 @@ declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b) define i32 @clmul32h(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: clmul32h: -; RV32B: # %bb.0: -; RV32B-NEXT: clmulh a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBC-LABEL: clmul32h: ; RV32ZBC: # %bb.0: ; RV32ZBC-NEXT: clmulh a0, a0, a1 @@ -39,11 +27,6 @@ declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) define i32 @clmul32r(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: clmul32r: -; RV32B: # %bb.0: -; RV32B-NEXT: clmulr a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBC-LABEL: clmul32r: ; RV32ZBC: # %bb.0: ; RV32ZBC-NEXT: clmulr a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll --- a/llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll @@ -1,17 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBE declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) define i32 @bcompress32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: bcompress32: -; RV32B: # %bb.0: -; RV32B-NEXT: bcompress a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBE-LABEL: bcompress32: ; RV32ZBE: # %bb.0: ; RV32ZBE-NEXT: bcompress a0, a0, a1 @@ -23,11 +16,6 @@ declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) define i32 @bdecompress32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: bdecompress32: -; RV32B: # %bb.0: -; RV32B-NEXT: bdecompress a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBE-LABEL: bdecompress32: ; RV32ZBE: # %bb.0: ; RV32ZBE-NEXT: bdecompress a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll --- a/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll @@ -1,17 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBP declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) define i32 @grev32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: grev32: -; RV32B: # %bb.0: -; RV32B-NEXT: grev a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: grev a0, a0, a1 @@ -21,11 +14,6 @@ } define i32 @grev32_demandedbits(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: grev32_demandedbits: -; RV32B: # %bb.0: -; RV32B-NEXT: grev a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev32_demandedbits: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: grev a0, a0, a1 @@ -36,11 +24,6 @@ } define i32 @grevi32(i32 %a) nounwind { -; RV32B-LABEL: grevi32: -; RV32B: # %bb.0: -; RV32B-NEXT: grevi a0, a0, 13 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grevi32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: grevi a0, a0, 13 @@ -52,11 +35,6 @@ declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) define i32 @gorc32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: gorc32: -; RV32B: # %bb.0: -; RV32B-NEXT: gorc a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: gorc a0, a0, a1 @@ -66,11 +44,6 @@ } define i32 @gorc32_demandedbits(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: gorc32_demandedbits: -; RV32B: # %bb.0: -; RV32B-NEXT: gorc a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc32_demandedbits: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: gorc a0, a0, a1 @@ -81,11 +54,6 @@ } define i32 @gorci32(i32 %a) nounwind { -; RV32B-LABEL: gorci32: -; RV32B: # %bb.0: -; RV32B-NEXT: gorci a0, a0, 13 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorci32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: gorci a0, a0, 13 @@ -97,11 +65,6 @@ declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b) define i32 @shfl32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: shfl32: -; RV32B: # %bb.0: -; RV32B-NEXT: shfl a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: shfl a0, a0, a1 @@ -111,11 +74,6 @@ } define i32 @shfl32_demandedbits(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: shfl32_demandedbits: -; RV32B: # %bb.0: -; RV32B-NEXT: shfl a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl32_demandedbits: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: shfl a0, a0, a1 @@ -126,11 +84,6 @@ } define i32 @shfli32(i32 %a) nounwind { -; RV32B-LABEL: shfli32: -; RV32B: # %bb.0: -; RV32B-NEXT: shfli a0, a0, 13 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfli32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: shfli a0, a0, 13 @@ -142,11 +95,6 @@ declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b) define i32 @unshfl32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: unshfl32: -; RV32B: # %bb.0: -; RV32B-NEXT: unshfl a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: unshfl32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: unshfl a0, a0, a1 @@ -156,11 +104,6 @@ } define i32 @unshfl32_demandedbits(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: unshfl32_demandedbits: -; RV32B: # %bb.0: -; RV32B-NEXT: unshfl a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: unshfl32_demandedbits: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: unshfl a0, a0, a1 @@ -171,11 +114,6 @@ } define i32 @unshfli32(i32 %a) nounwind { -; RV32B-LABEL: unshfli32: -; RV32B: # %bb.0: -; RV32B-NEXT: unshfli a0, a0, 13 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: unshfli32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: unshfli a0, a0, 13 @@ -187,11 +125,6 @@ declare i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b) define i32 @xpermn32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: xpermn32: -; RV32B: # %bb.0: -; RV32B-NEXT: xperm.n a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: xpermn32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: xperm.n a0, a0, a1 @@ -203,11 +136,6 @@ declare i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b) define i32 @xpermb32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: xpermb32: -; RV32B: # %bb.0: -; RV32B-NEXT: xperm.b a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: xpermb32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: xperm.b a0, a0, a1 @@ -219,11 +147,6 @@ declare i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b) define i32 @xpermh32(i32 %a, i32 %b) nounwind { -; RV32B-LABEL: xpermh32: -; RV32B: # %bb.0: -; RV32B-NEXT: xperm.h a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: xpermh32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: xperm.h a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/rv32zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbp.ll --- a/llvm/test/CodeGen/RISCV/rv32zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbp.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBP @@ -21,11 +19,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc1_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.p a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc1_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc.p a0, a0 @@ -60,12 +53,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc1_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.p a0, a0 -; RV32B-NEXT: orc.p a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc1_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc.p a0, a0 @@ -95,11 +82,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc2_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc2.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc2_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc2.n a0, a0 @@ -134,12 +116,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc2_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc2.n a0, a0 -; RV32B-NEXT: orc2.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc2_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc2.n a0, a0 @@ -179,11 +155,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc3_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc3_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc.n a0, a0 @@ -240,12 +211,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc3_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.n a0, a0 -; RV32B-NEXT: orc.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc3_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc.n a0, a0 @@ -281,11 +246,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc4_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc4.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc4_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc4.b a0, a0 @@ -320,12 +280,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc4_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc4.b a0, a0 -; RV32B-NEXT: orc4.b a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc4_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc4.b a0, a0 @@ -365,11 +319,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc5_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: gorci a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc5_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: gorci a0, a0, 5 @@ -426,12 +375,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc5_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: gorci a0, a0, 5 -; RV32B-NEXT: gorci a1, a1, 5 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc5_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: gorci a0, a0, 5 @@ -477,11 +420,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc6_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc2.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc6_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc2.b a0, a0 @@ -538,12 +476,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc6_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc2.b a0, a0 -; RV32B-NEXT: orc2.b a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc6_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc2.b a0, a0 @@ -599,11 +531,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc7_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc7_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc.b a0, a0 @@ -682,12 +609,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc7_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.b a0, a0 -; RV32B-NEXT: orc.b a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc7_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc.b a0, a0 @@ -729,11 +650,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc8_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc8.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc8_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc8.h a0, a0 @@ -768,12 +684,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc8_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc8.h a0, a0 -; RV32B-NEXT: orc8.h a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc8_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc8.h a0, a0 @@ -797,11 +707,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc16_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc16 a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc16_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc16 a0, a0 @@ -822,11 +727,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc16_rotl_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc16 a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc16_rotl_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc16 a0, a0 @@ -845,11 +745,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc16_rotr_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc16 a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc16_rotr_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc16 a0, a0 @@ -872,12 +767,6 @@ ; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc16_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc16 a0, a0 -; RV32B-NEXT: orc16 a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc16_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc16 a0, a0 @@ -914,11 +803,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc2b_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc2.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc2b_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc2.n a0, a0 @@ -972,12 +856,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc2b_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc2.n a0, a0 -; RV32B-NEXT: orc2.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc2b_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc2.n a0, a0 @@ -1030,11 +908,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc3b_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc3b_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc.n a0, a0 @@ -1110,12 +983,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: gorc3b_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: orc.n a0, a0 -; RV32B-NEXT: orc.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: gorc3b_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: orc.n a0, a0 @@ -1156,11 +1023,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev1_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.p a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev1_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.p a0, a0 @@ -1192,12 +1054,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev1_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.p a0, a0 -; RV32B-NEXT: rev.p a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev1_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.p a0, a0 @@ -1225,11 +1081,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev2_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev2.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev2_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev2.n a0, a0 @@ -1261,12 +1112,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev2_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev2.n a0, a0 -; RV32B-NEXT: rev2.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev2_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev2.n a0, a0 @@ -1303,11 +1148,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev3_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev3_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.n a0, a0 @@ -1358,12 +1198,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev3_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.n a0, a0 -; RV32B-NEXT: rev.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev3_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.n a0, a0 @@ -1396,11 +1230,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev4_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev4.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev4_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev4.b a0, a0 @@ -1432,12 +1261,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev4_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev4.b a0, a0 -; RV32B-NEXT: rev4.b a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev4_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev4.b a0, a0 @@ -1474,11 +1297,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev5_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: grevi a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev5_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: grevi a0, a0, 5 @@ -1529,12 +1347,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev5_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: grevi a0, a0, 5 -; RV32B-NEXT: grevi a1, a1, 5 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev5_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: grevi a0, a0, 5 @@ -1577,11 +1389,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev6_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev2.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev6_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev2.b a0, a0 @@ -1632,12 +1439,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev6_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev2.b a0, a0 -; RV32B-NEXT: rev2.b a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev6_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev2.b a0, a0 @@ -1688,11 +1489,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev7_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev7_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.b a0, a0 @@ -1762,12 +1558,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev7_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.b a0, a0 -; RV32B-NEXT: rev.b a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev7_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.b a0, a0 @@ -1805,11 +1595,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev8_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev8_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8.h a0, a0 @@ -1841,12 +1626,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev8_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8.h a0, a0 -; RV32B-NEXT: rev8.h a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev8_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8.h a0, a0 @@ -1868,11 +1647,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev16_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rori a0, a0, 16 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev16_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rori a0, a0, 16 @@ -1907,11 +1681,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev3b_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev3b_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.n a0, a0 @@ -1962,12 +1731,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev3b_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.n a0, a0 -; RV32B-NEXT: rev.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev3b_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.n a0, a0 @@ -2015,11 +1778,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev2b_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev2.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev2b_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev2.n a0, a0 @@ -2086,12 +1844,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev2b_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev2.n a0, a0 -; RV32B-NEXT: rev2.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev2b_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev2.n a0, a0 @@ -2149,10 +1901,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev0_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev0_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: ret @@ -2233,10 +1981,6 @@ ; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev0_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev0_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: ret @@ -2274,11 +2018,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev16_i32_fshl: -; RV32B: # %bb.0: -; RV32B-NEXT: rori a0, a0, 16 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev16_i32_fshl: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rori a0, a0, 16 @@ -2295,11 +2034,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev16_i32_fshr: -; RV32B: # %bb.0: -; RV32B-NEXT: rori a0, a0, 16 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev16_i32_fshr: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rori a0, a0, 16 @@ -2319,12 +2053,6 @@ ; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: grev16_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rori a0, a0, 16 -; RV32B-NEXT: rori a1, a1, 16 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: grev16_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rori a0, a0, 16 @@ -2351,11 +2079,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bswap_i16: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bswap_i16: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8.h a0, a0 @@ -2383,11 +2106,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bswap_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8 a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bswap_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8 a0, a0 @@ -2425,13 +2143,6 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bswap_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8 a2, a1 -; RV32B-NEXT: rev8 a1, a0 -; RV32B-NEXT: mv a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bswap_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8 a2, a1 @@ -2463,11 +2174,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bitreverse_i8: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bitreverse_i8: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.b a0, a0 @@ -2507,11 +2213,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bitreverse_i16: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bitreverse_i16: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.h a0, a0 @@ -2560,11 +2261,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bitreverse_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bitreverse_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev a0, a0 @@ -2638,13 +2334,6 @@ ; RV32I-NEXT: mv a0, t0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bitreverse_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev a2, a1 -; RV32B-NEXT: rev a1, a0 -; RV32B-NEXT: mv a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bitreverse_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev a2, a1 @@ -2675,11 +2364,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bswap_rotr_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bswap_rotr_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8.h a0, a0 @@ -2709,11 +2393,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bswap_rotl_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev8.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bswap_rotl_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev8.h a0, a0 @@ -2770,11 +2449,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bitreverse_bswap_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bitreverse_bswap_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.b a0, a0 @@ -2864,12 +2538,6 @@ ; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: bitreverse_bswap_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: rev.b a0, a0 -; RV32B-NEXT: rev.b a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: bitreverse_bswap_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: rev.b a0, a0 @@ -2898,11 +2566,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: shfl1_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: zip.n a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl1_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zip.n a0, a0 @@ -2942,12 +2605,6 @@ ; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: shfl1_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: zip.n a0, a0 -; RV32B-NEXT: zip.n a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl1_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zip.n a0, a0 @@ -2981,11 +2638,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: shfl2_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: zip2.b a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl2_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zip2.b a0, a0 @@ -3025,12 +2677,6 @@ ; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: shfl2_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: zip2.b a0, a0 -; RV32B-NEXT: zip2.b a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl2_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zip2.b a0, a0 @@ -3064,11 +2710,6 @@ ; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: shfl4_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: zip4.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl4_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zip4.h a0, a0 @@ -3108,12 +2749,6 @@ ; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: ret ; -; RV32B-LABEL: shfl4_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: zip4.h a0, a0 -; RV32B-NEXT: zip4.h a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl4_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zip4.h a0, a0 @@ -3146,11 +2781,6 @@ ; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: shfl8_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: zip8 a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl8_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zip8 a0, a0 @@ -3189,12 +2819,6 @@ ; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: shfl8_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: zip8 a0, a0 -; RV32B-NEXT: zip8 a1, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: shfl8_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zip8 a0, a0 @@ -3220,11 +2844,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: pack_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: pack a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: pack_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: pack a0, a0, a1 @@ -3246,11 +2865,6 @@ ; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: pack_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: mv a1, a2 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: pack_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: mv a1, a2 @@ -3270,11 +2884,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: packu_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: packu a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: packu_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: packu a0, a0, a1 @@ -3297,12 +2906,6 @@ ; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: ret ; -; RV32B-LABEL: packu_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: mv a0, a1 -; RV32B-NEXT: mv a1, a3 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: packu_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: mv a0, a1 @@ -3323,11 +2926,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: packh_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: packh a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: packh_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: packh a0, a0, a1 @@ -3349,12 +2947,6 @@ ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: ret ; -; RV32B-LABEL: packh_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: packh a0, a0, a2 -; RV32B-NEXT: mv a1, zero -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: packh_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: packh a0, a0, a2 @@ -3375,11 +2967,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: zexth_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: zext.h a0, a0 -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: zexth_i32: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zext.h a0, a0 @@ -3397,12 +2984,6 @@ ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: ret ; -; RV32B-LABEL: zexth_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: zext.h a0, a0 -; RV32B-NEXT: mv a1, zero -; RV32B-NEXT: ret -; ; RV32ZBP-LABEL: zexth_i64: ; RV32ZBP: # %bb.0: ; RV32ZBP-NEXT: zext.h a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll --- a/llvm/test/CodeGen/RISCV/rv32zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBS @@ -15,11 +13,6 @@ ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclr_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: bclr a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclr_i32: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclr a0, a0, a1 @@ -40,11 +33,6 @@ ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclr_i32_no_mask: -; RV32B: # %bb.0: -; RV32B-NEXT: bclr a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclr_i32_no_mask: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclr a0, a0, a1 @@ -73,19 +61,6 @@ ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclr_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: bset a3, zero, a2 -; RV32B-NEXT: andi a2, a2, 63 -; RV32B-NEXT: addi a2, a2, -32 -; RV32B-NEXT: srai a4, a2, 31 -; RV32B-NEXT: and a3, a4, a3 -; RV32B-NEXT: slti a4, a2, 0 -; RV32B-NEXT: bclr a2, a1, a2 -; RV32B-NEXT: cmov a1, a4, a1, a2 -; RV32B-NEXT: andn a0, a0, a3 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclr_i64: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: andi a3, a2, 63 @@ -112,11 +87,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbset_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: bset a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbset_i32: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bset a0, a0, a1 @@ -135,11 +105,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbset_i32_no_mask: -; RV32B: # %bb.0: -; RV32B-NEXT: bset a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbset_i32_no_mask: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bset a0, a0, a1 @@ -157,11 +122,6 @@ ; RV32I-NEXT: sll a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbset_i32_zero: -; RV32B: # %bb.0: -; RV32B-NEXT: bset a0, zero, a0 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbset_i32_zero: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bset a0, zero, a0 @@ -185,14 +145,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbset_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: bset a3, zero, a2 -; RV32B-NEXT: srai a3, a3, 31 -; RV32B-NEXT: bset a0, a0, a2 -; RV32B-NEXT: or a1, a3, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbset_i64: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bset a3, zero, a2 @@ -223,17 +175,6 @@ ; RV32I-NEXT: sll a0, a2, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbset_i64_zero: -; RV32B: # %bb.0: -; RV32B-NEXT: addi a2, a0, -32 -; RV32B-NEXT: bset a1, zero, a2 -; RV32B-NEXT: slti a3, a2, 0 -; RV32B-NEXT: cmov a1, a3, zero, a1 -; RV32B-NEXT: bset a0, zero, a0 -; RV32B-NEXT: srai a2, a2, 31 -; RV32B-NEXT: and a0, a2, a0 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbset_i64_zero: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: addi a1, a0, -32 @@ -258,11 +199,6 @@ ; RV32I-NEXT: xor a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbinv_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: binv a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbinv_i32: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: binv a0, a0, a1 @@ -288,14 +224,6 @@ ; RV32I-NEXT: xor a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbinv_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: bset a3, zero, a2 -; RV32B-NEXT: srai a3, a3, 31 -; RV32B-NEXT: binv a0, a0, a2 -; RV32B-NEXT: xor a1, a3, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbinv_i64: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bset a3, zero, a2 @@ -318,11 +246,6 @@ ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbext_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: bext a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbext_i32: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bext a0, a0, a1 @@ -340,11 +263,6 @@ ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbext_i32_no_mask: -; RV32B: # %bb.0: -; RV32B-NEXT: bext a0, a0, a1 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbext_i32_no_mask: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bext a0, a0, a1 @@ -380,23 +298,6 @@ ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbext_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: srl a0, a0, a2 -; RV32B-NEXT: andi a2, a2, 63 -; RV32B-NEXT: addi a3, zero, 31 -; RV32B-NEXT: sub a3, a3, a2 -; RV32B-NEXT: slli a4, a1, 1 -; RV32B-NEXT: sll a3, a4, a3 -; RV32B-NEXT: or a0, a0, a3 -; RV32B-NEXT: addi a2, a2, -32 -; RV32B-NEXT: srl a1, a1, a2 -; RV32B-NEXT: slti a2, a2, 0 -; RV32B-NEXT: cmov a0, a2, a0, a1 -; RV32B-NEXT: andi a0, a0, 1 -; RV32B-NEXT: mv a1, zero -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbext_i64: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: andi a3, a2, 63 @@ -429,11 +330,6 @@ ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbexti_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: bexti a0, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbexti_i32: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bexti a0, a0, 5 @@ -451,12 +347,6 @@ ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbexti_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: bexti a0, a0, 5 -; RV32B-NEXT: mv a1, zero -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbexti_i64: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bexti a0, a0, 5 @@ -473,11 +363,6 @@ ; RV32I-NEXT: andi a0, a0, -1025 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclri_i32_10: -; RV32B: # %bb.0: -; RV32B-NEXT: andi a0, a0, -1025 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclri_i32_10: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: andi a0, a0, -1025 @@ -494,11 +379,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclri_i32_11: -; RV32B: # %bb.0: -; RV32B-NEXT: bclri a0, a0, 11 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclri_i32_11: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclri a0, a0, 11 @@ -515,11 +395,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclri_i32_30: -; RV32B: # %bb.0: -; RV32B-NEXT: bclri a0, a0, 30 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclri_i32_30: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclri a0, a0, 30 @@ -536,11 +411,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclri_i32_31: -; RV32B: # %bb.0: -; RV32B-NEXT: bclri a0, a0, 31 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclri_i32_31: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclri a0, a0, 31 @@ -557,12 +427,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclri_i32_large0: -; RV32B: # %bb.0: -; RV32B-NEXT: andi a0, a0, -256 -; RV32B-NEXT: bclri a0, a0, 24 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclri_i32_large0: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: andi a0, a0, -256 @@ -580,12 +444,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclri_i32_large1: -; RV32B: # %bb.0: -; RV32B-NEXT: bclri a0, a0, 16 -; RV32B-NEXT: bclri a0, a0, 24 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclri_i32_large1: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclri a0, a0, 16 @@ -603,12 +461,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclri_i32_large2: -; RV32B: # %bb.0: -; RV32B-NEXT: bclri a0, a0, 2 -; RV32B-NEXT: bclri a0, a0, 31 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclri_i32_large2: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclri a0, a0, 2 @@ -626,12 +478,6 @@ ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbclri_i32_large3: -; RV32B: # %bb.0: -; RV32B-NEXT: andi a0, a0, -6 -; RV32B-NEXT: bclri a0, a0, 31 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbclri_i32_large3: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: andi a0, a0, -6 @@ -647,11 +493,6 @@ ; RV32I-NEXT: ori a0, a0, 1024 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbseti_i32_10: -; RV32B: # %bb.0: -; RV32B-NEXT: ori a0, a0, 1024 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbseti_i32_10: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: ori a0, a0, 1024 @@ -668,11 +509,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbseti_i32_11: -; RV32B: # %bb.0: -; RV32B-NEXT: bseti a0, a0, 11 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbseti_i32_11: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bseti a0, a0, 11 @@ -688,11 +524,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbseti_i32_30: -; RV32B: # %bb.0: -; RV32B-NEXT: bseti a0, a0, 30 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbseti_i32_30: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bseti a0, a0, 30 @@ -708,11 +539,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbseti_i32_31: -; RV32B: # %bb.0: -; RV32B-NEXT: bseti a0, a0, 31 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbseti_i32_31: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bseti a0, a0, 31 @@ -727,11 +553,6 @@ ; RV32I-NEXT: xori a0, a0, 1024 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbinvi_i32_10: -; RV32B: # %bb.0: -; RV32B-NEXT: xori a0, a0, 1024 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbinvi_i32_10: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: xori a0, a0, 1024 @@ -748,11 +569,6 @@ ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbinvi_i32_11: -; RV32B: # %bb.0: -; RV32B-NEXT: binvi a0, a0, 11 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbinvi_i32_11: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: binvi a0, a0, 11 @@ -768,11 +584,6 @@ ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbinvi_i32_30: -; RV32B: # %bb.0: -; RV32B-NEXT: binvi a0, a0, 30 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbinvi_i32_30: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: binvi a0, a0, 30 @@ -788,11 +599,6 @@ ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: sbinvi_i32_31: -; RV32B: # %bb.0: -; RV32B-NEXT: binvi a0, a0, 31 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: sbinvi_i32_31: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: binvi a0, a0, 31 @@ -809,12 +615,6 @@ ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: xor_i32_4098: -; RV32B: # %bb.0: -; RV32B-NEXT: binvi a0, a0, 1 -; RV32B-NEXT: binvi a0, a0, 12 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: xor_i32_4098: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: binvi a0, a0, 1 @@ -832,12 +632,6 @@ ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: xor_i32_4099: -; RV32B: # %bb.0: -; RV32B-NEXT: xori a0, a0, 3 -; RV32B-NEXT: binvi a0, a0, 12 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: xor_i32_4099: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: xori a0, a0, 3 @@ -853,11 +647,6 @@ ; RV32I-NEXT: xori a0, a0, 96 ; RV32I-NEXT: ret ; -; RV32B-LABEL: xor_i32_96: -; RV32B: # %bb.0: -; RV32B-NEXT: xori a0, a0, 96 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: xor_i32_96: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: xori a0, a0, 96 @@ -874,12 +663,6 @@ ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: xor_i32_66901: -; RV32B: # %bb.0: -; RV32B-NEXT: xori a0, a0, 1365 -; RV32B-NEXT: binvi a0, a0, 16 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: xor_i32_66901: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: xori a0, a0, 1365 @@ -897,12 +680,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: or_i32_4098: -; RV32B: # %bb.0: -; RV32B-NEXT: bseti a0, a0, 1 -; RV32B-NEXT: bseti a0, a0, 12 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: or_i32_4098: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bseti a0, a0, 1 @@ -920,12 +697,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: or_i32_4099: -; RV32B: # %bb.0: -; RV32B-NEXT: ori a0, a0, 3 -; RV32B-NEXT: bseti a0, a0, 12 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: or_i32_4099: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: ori a0, a0, 3 @@ -941,11 +712,6 @@ ; RV32I-NEXT: ori a0, a0, 96 ; RV32I-NEXT: ret ; -; RV32B-LABEL: or_i32_96: -; RV32B: # %bb.0: -; RV32B-NEXT: ori a0, a0, 96 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: or_i32_96: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: ori a0, a0, 96 @@ -962,12 +728,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: or_i32_66901: -; RV32B: # %bb.0: -; RV32B-NEXT: ori a0, a0, 1365 -; RV32B-NEXT: bseti a0, a0, 16 -; RV32B-NEXT: ret -; ; RV32ZBS-LABEL: or_i32_66901: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: ori a0, a0, 1365 diff --git a/llvm/test/CodeGen/RISCV/rv32zbt.ll b/llvm/test/CodeGen/RISCV/rv32zbt.ll --- a/llvm/test/CodeGen/RISCV/rv32zbt.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbt.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV32B ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBT @@ -15,11 +13,6 @@ ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmix_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: cmix a0, a1, a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmix_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: cmix a0, a1, a0, a2 @@ -44,12 +37,6 @@ ; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmix_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: cmix a0, a2, a0, a4 -; RV32B-NEXT: cmix a1, a3, a1, a5 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmix_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: cmix a0, a2, a0, a4 @@ -72,11 +59,6 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: cmov a0, a1, a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: cmov a0, a1, a0, a2 @@ -95,12 +77,6 @@ ; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_sle_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: slt a1, a2, a1 -; RV32B-NEXT: cmov a0, a1, a3, a0 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_sle_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: slt a1, a2, a1 @@ -120,12 +96,6 @@ ; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_sge_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: slt a1, a1, a2 -; RV32B-NEXT: cmov a0, a1, a3, a0 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_sge_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: slt a1, a1, a2 @@ -145,12 +115,6 @@ ; RV32I-NEXT: .LBB5_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_ule_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: sltu a1, a2, a1 -; RV32B-NEXT: cmov a0, a1, a3, a0 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_ule_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: sltu a1, a2, a1 @@ -170,12 +134,6 @@ ; RV32I-NEXT: .LBB6_2: ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_uge_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: sltu a1, a1, a2 -; RV32B-NEXT: cmov a0, a1, a3, a0 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_uge_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: sltu a1, a1, a2 @@ -199,13 +157,6 @@ ; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: or a2, a2, a3 -; RV32B-NEXT: cmov a0, a2, a0, a4 -; RV32B-NEXT: cmov a1, a2, a1, a5 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: or a2, a2, a3 @@ -236,18 +187,6 @@ ; RV32I-NEXT: .LBB8_4: ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_sle_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: xor t0, a3, a5 -; RV32B-NEXT: sltu a2, a4, a2 -; RV32B-NEXT: xori a2, a2, 1 -; RV32B-NEXT: slt a3, a5, a3 -; RV32B-NEXT: xori a3, a3, 1 -; RV32B-NEXT: cmov a2, t0, a3, a2 -; RV32B-NEXT: cmov a0, a2, a0, a6 -; RV32B-NEXT: cmov a1, a2, a1, a7 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_sle_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: xor t0, a3, a5 @@ -283,18 +222,6 @@ ; RV32I-NEXT: .LBB9_4: ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_sge_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: xor t0, a3, a5 -; RV32B-NEXT: sltu a2, a2, a4 -; RV32B-NEXT: xori a2, a2, 1 -; RV32B-NEXT: slt a3, a3, a5 -; RV32B-NEXT: xori a3, a3, 1 -; RV32B-NEXT: cmov a2, t0, a3, a2 -; RV32B-NEXT: cmov a0, a2, a0, a6 -; RV32B-NEXT: cmov a1, a2, a1, a7 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_sge_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: xor t0, a3, a5 @@ -330,18 +257,6 @@ ; RV32I-NEXT: .LBB10_4: ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_ule_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: xor t0, a3, a5 -; RV32B-NEXT: sltu a2, a4, a2 -; RV32B-NEXT: xori a2, a2, 1 -; RV32B-NEXT: sltu a3, a5, a3 -; RV32B-NEXT: xori a3, a3, 1 -; RV32B-NEXT: cmov a2, t0, a3, a2 -; RV32B-NEXT: cmov a0, a2, a0, a6 -; RV32B-NEXT: cmov a1, a2, a1, a7 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_ule_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: xor t0, a3, a5 @@ -377,18 +292,6 @@ ; RV32I-NEXT: .LBB11_4: ; RV32I-NEXT: ret ; -; RV32B-LABEL: cmov_uge_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: xor t0, a3, a5 -; RV32B-NEXT: sltu a2, a2, a4 -; RV32B-NEXT: xori a2, a2, 1 -; RV32B-NEXT: sltu a3, a3, a5 -; RV32B-NEXT: xori a3, a3, 1 -; RV32B-NEXT: cmov a2, t0, a3, a2 -; RV32B-NEXT: cmov a0, a2, a0, a6 -; RV32B-NEXT: cmov a1, a2, a1, a7 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: cmov_uge_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: xor t0, a3, a5 @@ -417,12 +320,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: fshl_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: andi a2, a2, 31 -; RV32B-NEXT: fsl a0, a0, a1, a2 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: fshl_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: andi a2, a2, 31 @@ -485,43 +382,6 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: fshl_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: sll a7, a1, a4 -; RV32B-NEXT: andi a5, a4, 63 -; RV32B-NEXT: addi a6, zero, 31 -; RV32B-NEXT: sub t0, a6, a5 -; RV32B-NEXT: srli a1, a0, 1 -; RV32B-NEXT: srl a1, a1, t0 -; RV32B-NEXT: or a7, a7, a1 -; RV32B-NEXT: addi t1, a5, -32 -; RV32B-NEXT: sll t0, a0, t1 -; RV32B-NEXT: slti a1, t1, 0 -; RV32B-NEXT: cmov t0, a1, a7, t0 -; RV32B-NEXT: not a7, a4 -; RV32B-NEXT: srli t4, a3, 1 -; RV32B-NEXT: srl t2, t4, a7 -; RV32B-NEXT: addi a1, zero, 63 -; RV32B-NEXT: andn t3, a1, a4 -; RV32B-NEXT: addi a5, t3, -32 -; RV32B-NEXT: srai a1, a5, 31 -; RV32B-NEXT: and a1, a1, t2 -; RV32B-NEXT: or a1, t0, a1 -; RV32B-NEXT: fsri a2, a2, a3, 1 -; RV32B-NEXT: srl a7, a2, a7 -; RV32B-NEXT: sub a3, a6, t3 -; RV32B-NEXT: slli a2, t4, 1 -; RV32B-NEXT: sll a2, a2, a3 -; RV32B-NEXT: or a2, a7, a2 -; RV32B-NEXT: srl a3, t4, a5 -; RV32B-NEXT: slti a5, a5, 0 -; RV32B-NEXT: cmov a2, a5, a2, a3 -; RV32B-NEXT: sll a0, a0, a4 -; RV32B-NEXT: srai a3, t1, 31 -; RV32B-NEXT: and a0, a3, a0 -; RV32B-NEXT: or a0, a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: fshl_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: sll a7, a1, a4 @@ -573,12 +433,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: fshr_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: andi a2, a2, 31 -; RV32B-NEXT: fsr a0, a1, a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: fshr_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: andi a2, a2, 31 @@ -643,44 +497,6 @@ ; RV32I-NEXT: .LBB15_7: ; RV32I-NEXT: ret ; -; RV32B-LABEL: fshr_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: srl a7, a2, a4 -; RV32B-NEXT: andi a5, a4, 63 -; RV32B-NEXT: addi a6, zero, 31 -; RV32B-NEXT: sub t0, a6, a5 -; RV32B-NEXT: slli a2, a3, 1 -; RV32B-NEXT: sll a2, a2, t0 -; RV32B-NEXT: or a7, a7, a2 -; RV32B-NEXT: addi t2, a5, -32 -; RV32B-NEXT: srl t0, a3, t2 -; RV32B-NEXT: slti a2, t2, 0 -; RV32B-NEXT: cmov a7, a2, a7, t0 -; RV32B-NEXT: not t3, a4 -; RV32B-NEXT: slli t0, a0, 1 -; RV32B-NEXT: sll t1, t0, t3 -; RV32B-NEXT: addi a5, zero, 63 -; RV32B-NEXT: andn t4, a5, a4 -; RV32B-NEXT: addi a2, t4, -32 -; RV32B-NEXT: srai a5, a2, 31 -; RV32B-NEXT: and a5, a5, t1 -; RV32B-NEXT: or a7, a5, a7 -; RV32B-NEXT: fsri a1, a0, a1, 31 -; RV32B-NEXT: sll a1, a1, t3 -; RV32B-NEXT: sub a5, a6, t4 -; RV32B-NEXT: bclri a0, a0, 31 -; RV32B-NEXT: srl a0, a0, a5 -; RV32B-NEXT: or a0, a1, a0 -; RV32B-NEXT: sll a1, t0, a2 -; RV32B-NEXT: slti a2, a2, 0 -; RV32B-NEXT: cmov a0, a2, a0, a1 -; RV32B-NEXT: srl a1, a3, a4 -; RV32B-NEXT: srai a2, t2, 31 -; RV32B-NEXT: and a1, a2, a1 -; RV32B-NEXT: or a1, a0, a1 -; RV32B-NEXT: mv a0, a7 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: fshr_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: srl a7, a2, a4 @@ -731,11 +547,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: fshri_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: fsri a0, a1, a0, 5 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: fshri_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: fsri a0, a1, a0, 5 @@ -756,13 +567,6 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: fshri_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: fsri a2, a2, a3, 5 -; RV32B-NEXT: fsri a1, a3, a0, 5 -; RV32B-NEXT: mv a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: fshri_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: fsri a2, a2, a3, 5 @@ -781,11 +585,6 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; -; RV32B-LABEL: fshli_i32: -; RV32B: # %bb.0: -; RV32B-NEXT: fsri a0, a1, a0, 27 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: fshli_i32: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: fsri a0, a1, a0, 27 @@ -806,13 +605,6 @@ ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret ; -; RV32B-LABEL: fshli_i64: -; RV32B: # %bb.0: -; RV32B-NEXT: fsri a2, a3, a0, 27 -; RV32B-NEXT: fsri a1, a0, a1, 27 -; RV32B-NEXT: mv a0, a2 -; RV32B-NEXT: ret -; ; RV32ZBT-LABEL: fshli_i64: ; RV32ZBT: # %bb.0: ; RV32ZBT-NEXT: fsri a2, a3, a0, 27 diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBA @@ -13,11 +11,6 @@ ; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: ret ; -; RV64B-LABEL: slliuw: -; RV64B: # %bb.0: -; RV64B-NEXT: slli.uw a0, a0, 1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: slliuw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli.uw a0, a0, 1 @@ -37,14 +30,6 @@ ; RV64I-NEXT: ld a1, 8(a1) ; RV64I-NEXT: ret ; -; RV64B-LABEL: slliuw_2: -; RV64B: # %bb.0: -; RV64B-NEXT: slli.uw a0, a0, 4 -; RV64B-NEXT: add a1, a1, a0 -; RV64B-NEXT: ld a0, 0(a1) -; RV64B-NEXT: ld a1, 8(a1) -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: slliuw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli.uw a0, a0, 4 @@ -66,11 +51,6 @@ ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: adduw: -; RV64B: # %bb.0: -; RV64B-NEXT: add.uw a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: adduw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: add.uw a0, a1, a0 @@ -89,12 +69,6 @@ ; RV64I-NEXT: lb a0, 0(a0) ; RV64I-NEXT: ret ; -; RV64B-LABEL: adduw_2: -; RV64B: # %bb.0: -; RV64B-NEXT: add.uw a0, a0, a1 -; RV64B-NEXT: lb a0, 0(a0) -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: adduw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: add.uw a0, a0, a1 @@ -113,11 +87,6 @@ ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: ret ; -; RV64B-LABEL: zextw_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: zext.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: zextw_i64: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: zext.w a0, a0 @@ -136,12 +105,6 @@ ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: ret ; -; RV64B-LABEL: zextw_demandedbits_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: ori a0, a0, 1 -; RV64B-NEXT: zext.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: zextw_demandedbits_i64: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: ori a0, a0, 1 @@ -160,12 +123,6 @@ ; RV64I-NEXT: lh a0, 0(a0) ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh1add: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a0, a0, a1 -; RV64B-NEXT: lh a0, 0(a0) -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh1add: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a1 @@ -184,12 +141,6 @@ ; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh2add: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a0, a1 -; RV64B-NEXT: lw a0, 0(a0) -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh2add: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a1 @@ -208,12 +159,6 @@ ; RV64I-NEXT: ld a0, 0(a0) ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh3add: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a1 -; RV64B-NEXT: ld a0, 0(a0) -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh3add: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a1 @@ -233,12 +178,6 @@ ; RV64I-NEXT: lh a0, 0(a0) ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh1adduw: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add.uw a0, a0, a1 -; RV64B-NEXT: lh a0, 0(a0) -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh1adduw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add.uw a0, a0, a1 @@ -258,11 +197,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh1adduw_2: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add.uw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh1adduw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add.uw a0, a0, a1 @@ -282,12 +216,6 @@ ; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh2adduw: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add.uw a0, a0, a1 -; RV64B-NEXT: lw a0, 0(a0) -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh2adduw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add.uw a0, a0, a1 @@ -307,11 +235,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh2adduw_2: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add.uw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh2adduw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add.uw a0, a0, a1 @@ -331,12 +254,6 @@ ; RV64I-NEXT: ld a0, 0(a0) ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh3adduw: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add.uw a0, a0, a1 -; RV64B-NEXT: ld a0, 0(a0) -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh3adduw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add.uw a0, a0, a1 @@ -356,11 +273,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh3adduw_2: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add.uw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh3adduw_2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add.uw a0, a0, a1 @@ -386,14 +298,6 @@ ; RV64I-NEXT: mul a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh2add_extra_sext: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a0, a1 -; RV64B-NEXT: sllw a1, a2, a0 -; RV64B-NEXT: sraiw a0, a0, 2 -; RV64B-NEXT: mul a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh2add_extra_sext: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a1 @@ -419,12 +323,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul6: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a0, a0, a0 -; RV64B-NEXT: sh1add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul6: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 @@ -443,12 +341,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul10: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a0, a0 -; RV64B-NEXT: sh1add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul10: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 @@ -467,12 +359,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul12: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a0, a0, a0 -; RV64B-NEXT: sh2add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul12: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 @@ -491,12 +377,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul18: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: sh1add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul18: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 @@ -515,12 +395,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul20: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a0, a0 -; RV64B-NEXT: sh2add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul20: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 @@ -539,12 +413,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul24: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a0, a0, a0 -; RV64B-NEXT: sh3add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul24: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 @@ -563,12 +431,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul36: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: sh2add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul36: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 @@ -587,12 +449,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul40: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a0, a0 -; RV64B-NEXT: sh3add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul40: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 @@ -611,12 +467,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addmul72: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: sh3add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addmul72: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 @@ -634,12 +484,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul96: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a0, a0, a0 -; RV64B-NEXT: slli a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul96: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 @@ -656,12 +500,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul160: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a0, a0 -; RV64B-NEXT: slli a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul160: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 @@ -678,12 +516,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul288: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: slli a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul288: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 @@ -700,12 +532,6 @@ ; RV64I-NEXT: addi a0, a0, 5 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh1add_imm: -; RV64B: # %bb.0: -; RV64B-NEXT: slli a0, a0, 1 -; RV64B-NEXT: addi a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh1add_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a0, a0, 1 @@ -723,12 +549,6 @@ ; RV64I-NEXT: addi a0, a0, -6 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh2add_imm: -; RV64B: # %bb.0: -; RV64B-NEXT: slli a0, a0, 2 -; RV64B-NEXT: addi a0, a0, -6 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh2add_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a0, a0, 2 @@ -746,12 +566,6 @@ ; RV64I-NEXT: ori a0, a0, 7 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh3add_imm: -; RV64B: # %bb.0: -; RV64B-NEXT: slli a0, a0, 3 -; RV64B-NEXT: ori a0, a0, 7 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh3add_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a0, a0, 3 @@ -770,12 +584,6 @@ ; RV64I-NEXT: addi a0, a0, 11 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh1adduw_imm: -; RV64B: # %bb.0: -; RV64B-NEXT: slli.uw a0, a0, 1 -; RV64B-NEXT: addi a0, a0, 11 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh1adduw_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli.uw a0, a0, 1 @@ -795,12 +603,6 @@ ; RV64I-NEXT: addi a0, a0, -12 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh2adduw_imm: -; RV64B: # %bb.0: -; RV64B-NEXT: slli.uw a0, a0, 2 -; RV64B-NEXT: addi a0, a0, -12 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh2adduw_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli.uw a0, a0, 2 @@ -820,12 +622,6 @@ ; RV64I-NEXT: addi a0, a0, 13 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sh3adduw_imm: -; RV64B: # %bb.0: -; RV64B-NEXT: slli.uw a0, a0, 3 -; RV64B-NEXT: addi a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: sh3adduw_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli.uw a0, a0, 3 @@ -845,12 +641,6 @@ ; RV64I-NEXT: addi a0, a0, 5 ; RV64I-NEXT: ret ; -; RV64B-LABEL: adduw_imm: -; RV64B: # %bb.0: -; RV64B-NEXT: zext.w a0, a0 -; RV64B-NEXT: addi a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: adduw_imm: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: zext.w a0, a0 @@ -868,12 +658,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul258: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a1, zero, 258 -; RV64B-NEXT: mul a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul258: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 258 @@ -890,12 +674,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul260: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a1, zero, 260 -; RV64B-NEXT: mul a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul260: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 260 @@ -912,12 +690,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul264: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a1, zero, 264 -; RV64B-NEXT: mul a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul264: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 264 @@ -935,12 +707,6 @@ ; RV64I-NEXT: addi a0, a0, -2 ; RV64I-NEXT: ret ; -; RV64B-LABEL: imm_zextw: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a0, zero, -2 -; RV64B-NEXT: zext.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: imm_zextw: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a0, zero, -2 @@ -958,13 +724,6 @@ ; RV64I-NEXT: addi a0, a0, -1366 ; RV64I-NEXT: ret ; -; RV64B-LABEL: imm_zextw2: -; RV64B: # %bb.0: -; RV64B-NEXT: lui a0, 699051 -; RV64B-NEXT: addiw a0, a0, -1366 -; RV64B-NEXT: zext.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: imm_zextw2: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: lui a0, 699051 @@ -981,12 +740,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul11: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a1, a0, a0 -; RV64B-NEXT: sh1add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul11: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a1, a0, a0 @@ -1003,12 +756,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul19: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a1, a0, a0 -; RV64B-NEXT: sh1add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul19: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a1, a0, a0 @@ -1025,12 +772,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul13: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a1, a0, a0 -; RV64B-NEXT: sh2add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul13: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a1, a0, a0 @@ -1047,12 +788,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul21: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a1, a0, a0 -; RV64B-NEXT: sh2add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul21: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a1, a0, a0 @@ -1069,12 +804,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul37: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a1, a0, a0 -; RV64B-NEXT: sh2add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul37: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a1, a0, a0 @@ -1091,12 +820,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul25: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a1, a0, a0 -; RV64B-NEXT: sh3add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul25: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a1, a0, a0 @@ -1113,12 +836,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul41: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a1, a0, a0 -; RV64B-NEXT: sh3add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul41: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a1, a0, a0 @@ -1135,12 +852,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul73: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a1, a0, a0 -; RV64B-NEXT: sh3add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul73: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a1, a0, a0 @@ -1157,12 +868,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul27: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: sh1add a0, a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul27: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 @@ -1179,12 +884,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul45: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: sh2add a0, a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul45: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 @@ -1201,12 +900,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul81: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul81: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 @@ -1224,12 +917,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul4098: -; RV64B: # %bb.0: -; RV64B-NEXT: slli a1, a0, 12 -; RV64B-NEXT: sh1add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul4098: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a1, a0, 12 @@ -1247,12 +934,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul4100: -; RV64B: # %bb.0: -; RV64B-NEXT: slli a1, a0, 12 -; RV64B-NEXT: sh2add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul4100: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a1, a0, 12 @@ -1270,12 +951,6 @@ ; RV64I-NEXT: mul a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mul4104: -; RV64B: # %bb.0: -; RV64B-NEXT: slli a1, a0, 12 -; RV64B-NEXT: sh3add a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mul4104: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: slli a1, a0, 12 @@ -1292,12 +967,6 @@ ; RV64I-NEXT: mulw a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mulw192: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a0, a0, a0 -; RV64B-NEXT: slliw a0, a0, 6 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mulw192: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a0, a0 @@ -1314,12 +983,6 @@ ; RV64I-NEXT: mulw a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mulw320: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a0, a0 -; RV64B-NEXT: slliw a0, a0, 6 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mulw320: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a0, a0 @@ -1336,12 +999,6 @@ ; RV64I-NEXT: mulw a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: mulw576: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a0, a0 -; RV64B-NEXT: slliw a0, a0, 6 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: mulw576: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a0, a0 @@ -1359,12 +1016,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: add4104: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a1, zero, 1026 -; RV64B-NEXT: sh2add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: add4104: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 1026 @@ -1382,12 +1033,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: add8208: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a1, zero, 1026 -; RV64B-NEXT: sh3add a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: add8208: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: addi a1, zero, 1026 @@ -1405,12 +1050,6 @@ ; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addshl32_5_6: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a0, a1, a0 -; RV64B-NEXT: slliw a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addshl32_5_6: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a1, a0 @@ -1430,12 +1069,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addshl64_5_6: -; RV64B: # %bb.0: -; RV64B-NEXT: sh1add a0, a1, a0 -; RV64B-NEXT: slli a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addshl64_5_6: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh1add a0, a1, a0 @@ -1455,12 +1088,6 @@ ; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addshl32_5_7: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a1, a0 -; RV64B-NEXT: slliw a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addshl32_5_7: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a1, a0 @@ -1480,12 +1107,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addshl64_5_7: -; RV64B: # %bb.0: -; RV64B-NEXT: sh2add a0, a1, a0 -; RV64B-NEXT: slli a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addshl64_5_7: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh2add a0, a1, a0 @@ -1505,12 +1126,6 @@ ; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addshl32_5_8: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a1, a0 -; RV64B-NEXT: slliw a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addshl32_5_8: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a1, a0 @@ -1530,12 +1145,6 @@ ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: addshl64_5_8: -; RV64B: # %bb.0: -; RV64B-NEXT: sh3add a0, a1, a0 -; RV64B-NEXT: slli a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBA-LABEL: addshl64_5_8: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: sh3add a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll --- a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll @@ -1,17 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBB declare i32 @llvm.riscv.orc.b.i32(i32) define signext i32 @orcb32(i32 signext %a) nounwind { -; RV64B-LABEL: orcb32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 7 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: orcb32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: orc.b a0, a0 @@ -24,11 +17,6 @@ declare i64 @llvm.riscv.orc.b.i64(i64) define i64 @orcb64(i64 %a) nounwind { -; RV64B-LABEL: orcb64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: orcb64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: orc.b a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll --- a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBB ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ @@ -15,11 +13,6 @@ ; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: andn_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: andn a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: andn_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: andn a0, a0, a1 @@ -41,11 +34,6 @@ ; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: andn_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: andn a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: andn_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: andn a0, a0, a1 @@ -67,11 +55,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: orn_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: orn a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: orn_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: orn a0, a0, a1 @@ -93,11 +76,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: orn_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orn a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: orn_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: orn a0, a0, a1 @@ -119,11 +97,6 @@ ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: xnor_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: xnor a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: xnor_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: xnor a0, a0, a1 @@ -145,11 +118,6 @@ ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: xnor_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: xnor a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: xnor_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: xnor a0, a0, a1 @@ -175,11 +143,6 @@ ; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: rol_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: rolw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rol_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rolw a0, a0, a1 @@ -204,12 +167,6 @@ ; RV64I-NEXT: sw a0, 0(a2) ; RV64I-NEXT: ret ; -; RV64B-LABEL: rol_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: rolw a0, a0, a1 -; RV64B-NEXT: sw a0, 0(a2) -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rol_i32_nosext: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rolw a0, a0, a1 @@ -236,12 +193,6 @@ ; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: rol_i32_neg_constant_rhs: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a1, zero, -2 -; RV64B-NEXT: rolw a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rol_i32_neg_constant_rhs: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: addi a1, zero, -2 @@ -268,11 +219,6 @@ ; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: rol_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rol a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rol_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rol a0, a0, a1 @@ -297,11 +243,6 @@ ; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ror_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: rorw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ror_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rorw a0, a0, a1 @@ -326,12 +267,6 @@ ; RV64I-NEXT: sw a0, 0(a2) ; RV64I-NEXT: ret ; -; RV64B-LABEL: ror_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: rorw a0, a0, a1 -; RV64B-NEXT: sw a0, 0(a2) -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ror_i32_nosext: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rorw a0, a0, a1 @@ -358,12 +293,6 @@ ; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ror_i32_neg_constant_rhs: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a1, zero, -2 -; RV64B-NEXT: rorw a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ror_i32_neg_constant_rhs: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: addi a1, zero, -2 @@ -390,11 +319,6 @@ ; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ror_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: ror a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ror_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: ror a0, a0, a1 @@ -416,11 +340,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: rori_i32_fshl: -; RV64B: # %bb.0: -; RV64B-NEXT: roriw a0, a0, 1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rori_i32_fshl: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: roriw a0, a0, 1 @@ -444,12 +363,6 @@ ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; -; RV64B-LABEL: rori_i32_fshl_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: roriw a0, a0, 1 -; RV64B-NEXT: sw a0, 0(a1) -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rori_i32_fshl_nosext: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: roriw a0, a0, 1 @@ -474,11 +387,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: rori_i32_fshr: -; RV64B: # %bb.0: -; RV64B-NEXT: roriw a0, a0, 31 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rori_i32_fshr: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: roriw a0, a0, 31 @@ -502,12 +410,6 @@ ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; -; RV64B-LABEL: rori_i32_fshr_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: roriw a0, a0, 31 -; RV64B-NEXT: sw a0, 0(a1) -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rori_i32_fshr_nosext: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: roriw a0, a0, 31 @@ -535,13 +437,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: not_rori_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: slliw a0, a0, 31 -; RV64B-NEXT: srliw a1, a1, 1 -; RV64B-NEXT: or a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: not_rori_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: slliw a0, a0, 31 @@ -575,16 +470,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: roriw_bug: -; RV64B: # %bb.0: -; RV64B-NEXT: slli a1, a0, 31 -; RV64B-NEXT: andi a0, a0, -2 -; RV64B-NEXT: srli a2, a0, 1 -; RV64B-NEXT: or a1, a1, a2 -; RV64B-NEXT: sext.w a1, a1 -; RV64B-NEXT: xor a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: roriw_bug: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: slli a1, a0, 31 @@ -622,11 +507,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: rori_i64_fshl: -; RV64B: # %bb.0: -; RV64B-NEXT: rori a0, a0, 1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rori_i64_fshl: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rori a0, a0, 1 @@ -648,11 +528,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: rori_i64_fshr: -; RV64B: # %bb.0: -; RV64B-NEXT: rori a0, a0, 63 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: rori_i64_fshr: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rori a0, a0, 63 @@ -673,12 +548,6 @@ ; RV64I-NEXT: srli a0, a0, 6 ; RV64I-NEXT: ret ; -; RV64B-LABEL: srli_i8: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a0, a0, 192 -; RV64B-NEXT: srli a0, a0, 6 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: srli_i8: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: andi a0, a0, 192 @@ -701,12 +570,6 @@ ; RV64I-NEXT: srai a0, a0, 61 ; RV64I-NEXT: ret ; -; RV64B-LABEL: srai_i8: -; RV64B: # %bb.0: -; RV64B-NEXT: sext.b a0, a0 -; RV64B-NEXT: srai a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: srai_i8: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.b a0, a0 @@ -729,12 +592,6 @@ ; RV64I-NEXT: srli a0, a0, 54 ; RV64I-NEXT: ret ; -; RV64B-LABEL: srli_i16: -; RV64B: # %bb.0: -; RV64B-NEXT: zext.h a0, a0 -; RV64B-NEXT: srli a0, a0, 6 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: srli_i16: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: zext.h a0, a0 @@ -757,12 +614,6 @@ ; RV64I-NEXT: srai a0, a0, 57 ; RV64I-NEXT: ret ; -; RV64B-LABEL: srai_i16: -; RV64B: # %bb.0: -; RV64B-NEXT: sext.h a0, a0 -; RV64B-NEXT: srai a0, a0, 9 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: srai_i16: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.h a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll --- a/llvm/test/CodeGen/RISCV/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBB @@ -80,11 +78,6 @@ ; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ctlz_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: clzw a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ctlz_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: clzw a0, a0 @@ -168,13 +161,6 @@ ; RV64I-NEXT: sub a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: log2_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: clzw a0, a0 -; RV64B-NEXT: addi a1, zero, 31 -; RV64B-NEXT: sub a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: log2_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: clzw a0, a0 @@ -262,14 +248,6 @@ ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64B-LABEL: log2_ceil_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: addiw a0, a0, -1 -; RV64B-NEXT: clzw a0, a0 -; RV64B-NEXT: addi a1, zero, 32 -; RV64B-NEXT: sub a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: log2_ceil_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: addiw a0, a0, -1 @@ -359,14 +337,6 @@ ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64B-LABEL: findLastSet_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: clzw a1, a0 -; RV64B-NEXT: xori a1, a1, 31 -; RV64B-NEXT: addi a2, zero, -1 -; RV64B-NEXT: cmov a0, a0, a1, a2 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: findLastSet_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: mv a1, a0 @@ -457,12 +427,6 @@ ; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ctlz_lshr_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: srliw a0, a0, 1 -; RV64B-NEXT: clzw a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ctlz_lshr_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: srliw a0, a0, 1 @@ -544,11 +508,6 @@ ; RV64I-NEXT: addi a0, zero, 64 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ctlz_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: clz a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ctlz_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: clz a0, a0 @@ -618,11 +577,6 @@ ; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: ret ; -; RV64B-LABEL: cttz_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: ctzw a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: cttz_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: ctzw a0, a0 @@ -685,11 +639,6 @@ ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64B-LABEL: cttz_zero_undef_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: ctzw a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: cttz_zero_undef_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: ctzw a0, a0 @@ -760,13 +709,6 @@ ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64B-LABEL: findFirstSet_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: ctzw a1, a0 -; RV64B-NEXT: addi a2, zero, -1 -; RV64B-NEXT: cmov a0, a0, a1, a2 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: findFirstSet_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: mv a1, a0 @@ -845,13 +787,6 @@ ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ffs_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: ctzw a1, a0 -; RV64B-NEXT: addi a1, a1, 1 -; RV64B-NEXT: cmov a0, a0, a1, zero -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ffs_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: mv a1, a0 @@ -930,11 +865,6 @@ ; RV64I-NEXT: addi a0, zero, 64 ; RV64I-NEXT: ret ; -; RV64B-LABEL: cttz_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: ctz a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: cttz_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: ctz a0, a0 @@ -992,11 +922,6 @@ ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ctpop_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: cpopw a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ctpop_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: cpopw a0, a0 @@ -1051,12 +976,6 @@ ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ctpop_i32_load: -; RV64B: # %bb.0: -; RV64B-NEXT: lwu a0, 0(a0) -; RV64B-NEXT: cpopw a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ctpop_i32_load: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: lwu a0, 0(a0) @@ -1120,11 +1039,6 @@ ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; -; RV64B-LABEL: ctpop_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: cpop a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: ctpop_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: cpop a0, a0 @@ -1140,11 +1054,6 @@ ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sextb_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: sext.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: sextb_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.b a0, a0 @@ -1161,11 +1070,6 @@ ; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sextb_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: sext.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: sextb_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.b a0, a0 @@ -1182,11 +1086,6 @@ ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sexth_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: sext.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: sexth_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.h a0, a0 @@ -1203,11 +1102,6 @@ ; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sexth_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: sext.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: sexth_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.h a0, a0 @@ -1226,11 +1120,6 @@ ; RV64I-NEXT: .LBB18_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: min_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: min a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: min_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: min a0, a0, a1 @@ -1249,11 +1138,6 @@ ; RV64I-NEXT: .LBB19_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: min_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: min a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: min_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: min a0, a0, a1 @@ -1272,11 +1156,6 @@ ; RV64I-NEXT: .LBB20_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: max_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: max a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: max_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: max a0, a0, a1 @@ -1295,11 +1174,6 @@ ; RV64I-NEXT: .LBB21_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: max_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: max a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: max_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: max a0, a0, a1 @@ -1318,11 +1192,6 @@ ; RV64I-NEXT: .LBB22_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: minu_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: minu a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: minu_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: minu a0, a0, a1 @@ -1341,11 +1210,6 @@ ; RV64I-NEXT: .LBB23_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: minu_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: minu a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: minu_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: minu a0, a0, a1 @@ -1364,11 +1228,6 @@ ; RV64I-NEXT: .LBB24_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: maxu_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: maxu a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: maxu_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: maxu a0, a0, a1 @@ -1387,11 +1246,6 @@ ; RV64I-NEXT: .LBB25_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: maxu_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: maxu a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: maxu_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: maxu a0, a0, a1 @@ -1412,13 +1266,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: abs_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: sext.w a0, a0 -; RV64B-NEXT: neg a1, a0 -; RV64B-NEXT: max a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: abs_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.w a0, a0 @@ -1439,12 +1286,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: abs_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: neg a1, a0 -; RV64B-NEXT: max a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: abs_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: neg a1, a0 @@ -1462,11 +1303,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: zexth_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: zext.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: zexth_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: zext.h a0, a0 @@ -1483,11 +1319,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: zexth_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: zext.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: zexth_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: zext.h a0, a0 @@ -1515,11 +1346,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 24 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: bswap_i32: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rev8 a0, a0 @@ -1548,12 +1374,6 @@ ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 24 -; RV64B-NEXT: sw a0, 0(a1) -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: bswap_i32_nosext: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rev8 a0, a0 @@ -1600,11 +1420,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev8 a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBB-LABEL: bswap_i64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: rev8 a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll --- a/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll @@ -1,17 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBC declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b) define i64 @clmul64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: clmul64: -; RV64B: # %bb.0: -; RV64B-NEXT: clmul a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBC-LABEL: clmul64: ; RV64ZBC: # %bb.0: ; RV64ZBC-NEXT: clmul a0, a0, a1 @@ -23,11 +16,6 @@ declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b) define i64 @clmul64h(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: clmul64h: -; RV64B: # %bb.0: -; RV64B-NEXT: clmulh a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBC-LABEL: clmul64h: ; RV64ZBC: # %bb.0: ; RV64ZBC-NEXT: clmulh a0, a0, a1 @@ -39,11 +27,6 @@ declare i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b) define i64 @clmul64r(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: clmul64r: -; RV64B: # %bb.0: -; RV64B-NEXT: clmulr a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBC-LABEL: clmul64r: ; RV64ZBC: # %bb.0: ; RV64ZBC-NEXT: clmulr a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll --- a/llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll @@ -1,17 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBE declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b) define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind { -; RV64B-LABEL: bcompress32: -; RV64B: # %bb.0: -; RV64B-NEXT: bcompressw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBE-LABEL: bcompress32: ; RV64ZBE: # %bb.0: ; RV64ZBE-NEXT: bcompressw a0, a0, a1 @@ -21,13 +14,6 @@ } define signext i32 @bcompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { -; RV64B-LABEL: bcompress32_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: add a0, a0, a1 -; RV64B-NEXT: add a1, a2, a3 -; RV64B-NEXT: bcompressw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBE-LABEL: bcompress32_demandedbits: ; RV64ZBE: # %bb.0: ; RV64ZBE-NEXT: add a0, a0, a1 @@ -43,11 +29,6 @@ declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b) define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind { -; RV64B-LABEL: bdecompress32: -; RV64B: # %bb.0: -; RV64B-NEXT: bdecompressw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBE-LABEL: bdecompress32: ; RV64ZBE: # %bb.0: ; RV64ZBE-NEXT: bdecompressw a0, a0, a1 @@ -57,13 +38,6 @@ } define signext i32 @bdecompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { -; RV64B-LABEL: bdecompress32_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: add a0, a0, a1 -; RV64B-NEXT: add a1, a2, a3 -; RV64B-NEXT: bdecompressw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBE-LABEL: bdecompress32_demandedbits: ; RV64ZBE: # %bb.0: ; RV64ZBE-NEXT: add a0, a0, a1 @@ -79,11 +53,6 @@ declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b) define i64 @bcompress64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: bcompress64: -; RV64B: # %bb.0: -; RV64B-NEXT: bcompress a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBE-LABEL: bcompress64: ; RV64ZBE: # %bb.0: ; RV64ZBE-NEXT: bcompress a0, a0, a1 @@ -95,11 +64,6 @@ declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b) define i64 @bdecompress64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: bdecompress64: -; RV64B: # %bb.0: -; RV64B-NEXT: bdecompress a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBE-LABEL: bdecompress64: ; RV64ZBE: # %bb.0: ; RV64ZBE-NEXT: bdecompress a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll --- a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll @@ -1,17 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBP declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind { -; RV64B-LABEL: grev32: -; RV64B: # %bb.0: -; RV64B-NEXT: grevw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: grevw a0, a0, a1 @@ -21,12 +14,6 @@ } define signext i32 @grev32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { -; RV64B-LABEL: grev32_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: add a0, a0, a1 -; RV64B-NEXT: grevw a0, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev32_demandedbits: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: add a0, a0, a1 @@ -41,11 +28,6 @@ declare i32 @llvm.riscv.grevi.i32(i32 %a) define signext i32 @grevi32(i32 signext %a) nounwind { -; RV64B-LABEL: grevi32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grevi32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 13 @@ -57,11 +39,6 @@ declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind { -; RV64B-LABEL: gorc32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorcw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorcw a0, a0, a1 @@ -71,12 +48,6 @@ } define signext i32 @gorc32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { -; RV64B-LABEL: gorc32_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: add a0, a0, a1 -; RV64B-NEXT: gorcw a0, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc32_demandedbits: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: add a0, a0, a1 @@ -89,11 +60,6 @@ } define signext i32 @gorci32(i32 signext %a) nounwind { -; RV64B-LABEL: gorci32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorci32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 13 @@ -105,11 +71,6 @@ declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b) define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind { -; RV64B-LABEL: shfl32: -; RV64B: # %bb.0: -; RV64B-NEXT: shflw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: shflw a0, a0, a1 @@ -119,12 +80,6 @@ } define signext i32 @shfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { -; RV64B-LABEL: shfl32_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: add a0, a0, a1 -; RV64B-NEXT: shflw a0, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl32_demandedbits: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: add a0, a0, a1 @@ -137,11 +92,6 @@ } define signext i32 @shfli32(i32 signext %a) nounwind { -; RV64B-LABEL: shfli32: -; RV64B: # %bb.0: -; RV64B-NEXT: shfli a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfli32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: shfli a0, a0, 13 @@ -153,11 +103,6 @@ declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b) define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind { -; RV64B-LABEL: unshfl32: -; RV64B: # %bb.0: -; RV64B-NEXT: unshflw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: unshfl32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: unshflw a0, a0, a1 @@ -167,12 +112,6 @@ } define signext i32 @unshfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { -; RV64B-LABEL: unshfl32_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: add a0, a0, a1 -; RV64B-NEXT: unshflw a0, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: unshfl32_demandedbits: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: add a0, a0, a1 @@ -185,11 +124,6 @@ } define signext i32 @unshfli32(i32 signext %a) nounwind { -; RV64B-LABEL: unshfli32: -; RV64B: # %bb.0: -; RV64B-NEXT: unshfli a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: unshfli32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: unshfli a0, a0, 13 @@ -201,11 +135,6 @@ declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b) define i64 @grev64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: grev64: -; RV64B: # %bb.0: -; RV64B-NEXT: grev a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: grev a0, a0, a1 @@ -215,11 +144,6 @@ } define i64 @grev64_demandedbits(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: grev64_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: grev a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev64_demandedbits: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: grev a0, a0, a1 @@ -230,11 +154,6 @@ } define i64 @grevi64(i64 %a) nounwind { -; RV64B-LABEL: grevi64: -; RV64B: # %bb.0: -; RV64B-NEXT: grevi a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grevi64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: grevi a0, a0, 13 @@ -246,11 +165,6 @@ declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b) define i64 @gorc64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: gorc64: -; RV64B: # %bb.0: -; RV64B-NEXT: gorc a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorc a0, a0, a1 @@ -260,11 +174,6 @@ } define i64 @gorc64_demandedbits(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: gorc64_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: gorc a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc64_demandedbits: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorc a0, a0, a1 @@ -277,11 +186,6 @@ declare i64 @llvm.riscv.gorci.i64(i64 %a) define i64 @gorci64(i64 %a) nounwind { -; RV64B-LABEL: gorci64: -; RV64B: # %bb.0: -; RV64B-NEXT: gorci a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorci64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorci a0, a0, 13 @@ -293,11 +197,6 @@ declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b) define i64 @shfl64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: shfl64: -; RV64B: # %bb.0: -; RV64B-NEXT: shfl a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: shfl a0, a0, a1 @@ -307,11 +206,6 @@ } define i64 @shfl64_demandedbits(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: shfl64_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: shfl a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl64_demandedbits: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: shfl a0, a0, a1 @@ -322,11 +216,6 @@ } define i64 @shfli64(i64 %a) nounwind { -; RV64B-LABEL: shfli64: -; RV64B: # %bb.0: -; RV64B-NEXT: shfli a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfli64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: shfli a0, a0, 13 @@ -338,11 +227,6 @@ declare i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b) define i64 @unshfl64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: unshfl64: -; RV64B: # %bb.0: -; RV64B-NEXT: unshfl a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: unshfl64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: unshfl a0, a0, a1 @@ -352,11 +236,6 @@ } define i64 @unshfl64_demandedbits(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: unshfl64_demandedbits: -; RV64B: # %bb.0: -; RV64B-NEXT: unshfl a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: unshfl64_demandedbits: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: unshfl a0, a0, a1 @@ -367,11 +246,6 @@ } define i64 @unshfli64(i64 %a) nounwind { -; RV64B-LABEL: unshfli64: -; RV64B: # %bb.0: -; RV64B-NEXT: unshfli a0, a0, 13 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: unshfli64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: unshfli a0, a0, 13 @@ -383,11 +257,6 @@ declare i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b) define i64 @xpermn64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: xpermn64: -; RV64B: # %bb.0: -; RV64B-NEXT: xperm.n a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: xpermn64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: xperm.n a0, a0, a1 @@ -399,11 +268,6 @@ declare i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b) define i64 @xpermb64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: xpermb64: -; RV64B: # %bb.0: -; RV64B-NEXT: xperm.b a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: xpermb64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: xperm.b a0, a0, a1 @@ -415,11 +279,6 @@ declare i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b) define i64 @xpermh64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: xpermh64: -; RV64B: # %bb.0: -; RV64B-NEXT: xperm.h a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: xpermh64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: xperm.h a0, a0, a1 @@ -431,11 +290,6 @@ declare i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b) define i64 @xpermw64(i64 %a, i64 %b) nounwind { -; RV64B-LABEL: xpermw64: -; RV64B: # %bb.0: -; RV64B-NEXT: xperm.w a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: xpermw64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: xperm.w a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/rv64zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbp.ll --- a/llvm/test/CodeGen/RISCV/rv64zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbp.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBP @@ -21,11 +19,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc1_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc1_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 1 @@ -66,11 +59,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc1_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc.p a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc1_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc.p a0, a0 @@ -99,11 +87,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc2_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 2 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc2_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 2 @@ -144,11 +127,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc2_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc2.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc2_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc2.n a0, a0 @@ -187,11 +165,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc3_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 3 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc3_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 3 @@ -260,11 +233,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc3_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc3_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc.n a0, a0 @@ -299,11 +267,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc4_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 4 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc4_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 4 @@ -344,11 +307,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc4_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc4.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc4_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc4.b a0, a0 @@ -387,11 +345,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc5_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc5_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 5 @@ -460,11 +413,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc5_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: gorci a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc5_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorci a0, a0, 5 @@ -509,11 +457,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc6_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 6 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc6_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 6 @@ -582,11 +525,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc6_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc2.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc6_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc2.b a0, a0 @@ -642,11 +580,6 @@ ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc7_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 7 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc7_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 7 @@ -743,11 +676,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc7_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc7_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc.b a0, a0 @@ -788,11 +716,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc8_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 8 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc8_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 8 @@ -829,11 +752,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc8_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc8.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc8_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc8.h a0, a0 @@ -856,11 +774,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc16_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 16 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc16_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 16 @@ -881,11 +794,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc16_rotl_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 16 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc16_rotl_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 16 @@ -904,11 +812,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc16_rotr_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 16 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc16_rotr_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 16 @@ -936,11 +839,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc16_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc16.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc16_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc16.w a0, a0 @@ -963,11 +861,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc32: -; RV64B: # %bb.0: -; RV64B-NEXT: orc32 a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc32 a0, a0 @@ -1001,11 +894,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc2b_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 2 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc2b_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 2 @@ -1059,11 +947,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc2b_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc2.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc2b_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc2.n a0, a0 @@ -1116,11 +999,6 @@ ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc3b_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: gorciw a0, a0, 3 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc3b_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: gorciw a0, a0, 3 @@ -1202,11 +1080,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc3b_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: orc.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc3b_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc.n a0, a0 @@ -1241,11 +1114,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc32_rotl: -; RV64B: # %bb.0: -; RV64B-NEXT: orc32 a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc32_rotl: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc32 a0, a0 @@ -1264,11 +1132,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: gorc32_rotr: -; RV64B: # %bb.0: -; RV64B-NEXT: orc32 a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: gorc32_rotr: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: orc32 a0, a0 @@ -1292,11 +1155,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev1_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev1_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 1 @@ -1335,11 +1193,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev1_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev.p a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev1_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev.p a0, a0 @@ -1366,11 +1219,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev2_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 2 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev2_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 2 @@ -1409,11 +1257,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev2_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev2.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev2_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev2.n a0, a0 @@ -1449,11 +1292,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev3_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 3 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev3_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 3 @@ -1518,11 +1356,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev3_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev3_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev.n a0, a0 @@ -1554,11 +1387,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev4_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 4 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev4_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 4 @@ -1597,11 +1425,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev4_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev4.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev4_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev4.b a0, a0 @@ -1637,11 +1460,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev5_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev5_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 5 @@ -1706,11 +1524,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev5_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: grevi a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev5_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: grevi a0, a0, 5 @@ -1752,11 +1565,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev6_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 6 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev6_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 6 @@ -1821,11 +1629,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev6_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev2.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev6_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev2.b a0, a0 @@ -1875,11 +1678,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev7_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 7 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev7_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 7 @@ -1970,11 +1768,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev7_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev7_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev.b a0, a0 @@ -2011,11 +1804,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev8_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 8 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev8_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 8 @@ -2050,11 +1838,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev8_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev8.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev8_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev8.h a0, a0 @@ -2075,11 +1858,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev16_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 16 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev16_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 16 @@ -2101,11 +1879,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev16_i32_fshl: -; RV64B: # %bb.0: -; RV64B-NEXT: roriw a0, a0, 16 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev16_i32_fshl: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: roriw a0, a0, 16 @@ -2122,11 +1895,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev16_i32_fshr: -; RV64B: # %bb.0: -; RV64B-NEXT: roriw a0, a0, 16 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev16_i32_fshr: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: roriw a0, a0, 16 @@ -2152,11 +1920,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev16_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev16.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev16_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev16.w a0, a0 @@ -2177,11 +1940,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev32: -; RV64B: # %bb.0: -; RV64B-NEXT: rori a0, a0, 32 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rori a0, a0, 32 @@ -2215,11 +1973,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev3b_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 3 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev3b_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 3 @@ -2284,11 +2037,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev3b_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev3b_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev.n a0, a0 @@ -2335,11 +2083,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev2b_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 2 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev2b_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 2 @@ -2415,11 +2158,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev2b_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev2.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev2b_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev2.n a0, a0 @@ -2476,10 +2214,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev0_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev0_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: ret @@ -2564,10 +2298,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev0_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev0_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: ret @@ -2605,11 +2335,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev32_fshl: -; RV64B: # %bb.0: -; RV64B-NEXT: rori a0, a0, 32 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev32_fshl: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rori a0, a0, 32 @@ -2626,11 +2351,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: grev32_fshr: -; RV64B: # %bb.0: -; RV64B-NEXT: rori a0, a0, 32 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: grev32_fshr: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rori a0, a0, 32 @@ -2652,11 +2372,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_i16: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 8 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bswap_i16: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 8 @@ -2684,11 +2399,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 24 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bswap_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 24 @@ -2716,12 +2426,6 @@ ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 24 -; RV64B-NEXT: sw a0, 0(a1) -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bswap_i32_nosext: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 24 @@ -2767,11 +2471,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev8 a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bswap_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev8 a0, a0 @@ -2801,11 +2500,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bitreverse_i8: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 7 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bitreverse_i8: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 7 @@ -2845,11 +2539,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bitreverse_i16: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 15 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bitreverse_i16: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 15 @@ -2898,11 +2587,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bitreverse_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 31 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bitreverse_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 31 @@ -2951,12 +2635,6 @@ ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; -; RV64B-LABEL: bitreverse_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 31 -; RV64B-NEXT: sw a0, 0(a1) -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bitreverse_i32_nosext: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 31 @@ -3041,11 +2719,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bitreverse_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bitreverse_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev a0, a0 @@ -3071,11 +2744,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_rotr_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 8 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bswap_rotr_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 8 @@ -3102,11 +2770,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bswap_rotl_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 8 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bswap_rotl_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 8 @@ -3163,11 +2826,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bitreverse_bswap_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: greviw a0, a0, 7 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bitreverse_bswap_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: greviw a0, a0, 7 @@ -3270,11 +2928,6 @@ ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: ret ; -; RV64B-LABEL: bitreverse_bswap_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: rev.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: bitreverse_bswap_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: rev.b a0, a0 @@ -3302,11 +2955,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl1_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: zip.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl1_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip.n a0, a0 @@ -3351,11 +2999,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl1_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: zip.n a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl1_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip.n a0, a0 @@ -3388,11 +3031,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl2_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: zip2.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl2_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip2.b a0, a0 @@ -3438,11 +3076,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl2_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: zip2.b a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl2_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip2.b a0, a0 @@ -3475,11 +3108,6 @@ ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl4_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: zip4.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl4_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip4.h a0, a0 @@ -3526,11 +3154,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl4_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: zip4.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl4_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip4.h a0, a0 @@ -3562,11 +3185,6 @@ ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl8_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: zip8.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl8_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip8.w a0, a0 @@ -3606,11 +3224,6 @@ ; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl8_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: zip8.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl8_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip8.w a0, a0 @@ -3644,11 +3257,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: shfl16: -; RV64B: # %bb.0: -; RV64B-NEXT: zip16 a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: shfl16: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zip16 a0, a0 @@ -3673,11 +3281,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: pack_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: packw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: pack_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: packw a0, a0, a1 @@ -3697,11 +3300,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: pack_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: pack a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: pack_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: pack a0, a0, a1 @@ -3721,11 +3319,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: packu_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: packuw a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: packu_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: packuw a0, a0, a1 @@ -3746,11 +3339,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: packu_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: packu a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: packu_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: packu a0, a0, a1 @@ -3770,11 +3358,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: packh_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: packh a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: packh_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: packh a0, a0, a1 @@ -3795,11 +3378,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: packh_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: packh a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: packh_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: packh a0, a0, a1 @@ -3819,11 +3397,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: zexth_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: zext.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: zexth_i32: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zext.h a0, a0 @@ -3840,11 +3413,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: zexth_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: zext.h a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBP-LABEL: zexth_i64: ; RV64ZBP: # %bb.0: ; RV64ZBP-NEXT: zext.h a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll --- a/llvm/test/CodeGen/RISCV/rv64zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBS @@ -15,13 +13,6 @@ ; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclr_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: andn a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclr_i32: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: addi a2, zero, 1 @@ -45,13 +36,6 @@ ; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclr_i32_no_mask: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: andn a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclr_i32_no_mask: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: addi a2, zero, 1 @@ -76,15 +60,6 @@ ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclr_i32_load: -; RV64B: # %bb.0: -; RV64B-NEXT: lw a0, 0(a0) -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: andn a0, a0, a1 -; RV64B-NEXT: sext.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclr_i32_load: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: lw a0, 0(a0) @@ -110,11 +85,6 @@ ; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclr_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: bclr a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclr_i64: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclr a0, a0, a1 @@ -135,11 +105,6 @@ ; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclr_i64_no_mask: -; RV64B: # %bb.0: -; RV64B-NEXT: bclr a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclr_i64_no_mask: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclr a0, a0, a1 @@ -158,13 +123,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbset_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: or a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbset_i32: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: addi a2, zero, 1 @@ -185,13 +143,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbset_i32_no_mask: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: or a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbset_i32_no_mask: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: addi a2, zero, 1 @@ -213,15 +164,6 @@ ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbset_i32_load: -; RV64B: # %bb.0: -; RV64B-NEXT: lw a0, 0(a0) -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: or a0, a1, a0 -; RV64B-NEXT: sext.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbset_i32_load: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: lw a0, 0(a0) @@ -244,12 +186,6 @@ ; RV64I-NEXT: sllw a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbset_i32_zero: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a1, zero, 1 -; RV64B-NEXT: sllw a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbset_i32_zero: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: addi a1, zero, 1 @@ -267,11 +203,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbset_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: bset a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbset_i64: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bset a0, a0, a1 @@ -290,11 +221,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbset_i64_no_mask: -; RV64B: # %bb.0: -; RV64B-NEXT: bset a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbset_i64_no_mask: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bset a0, a0, a1 @@ -312,11 +238,6 @@ ; RV64I-NEXT: sll a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbset_i64_zero: -; RV64B: # %bb.0: -; RV64B-NEXT: bset a0, zero, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbset_i64_zero: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bset a0, zero, a0 @@ -333,13 +254,6 @@ ; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinv_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: xor a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinv_i32: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: addi a2, zero, 1 @@ -360,13 +274,6 @@ ; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinv_i32_no_mask: -; RV64B: # %bb.0: -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: xor a0, a1, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinv_i32_no_mask: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: addi a2, zero, 1 @@ -388,15 +295,6 @@ ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinv_i32_load: -; RV64B: # %bb.0: -; RV64B-NEXT: lw a0, 0(a0) -; RV64B-NEXT: addi a2, zero, 1 -; RV64B-NEXT: sllw a1, a2, a1 -; RV64B-NEXT: xor a0, a1, a0 -; RV64B-NEXT: sext.w a0, a0 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinv_i32_load: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: lw a0, 0(a0) @@ -419,11 +317,6 @@ ; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinv_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: binv a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinv_i64: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binv a0, a0, a1 @@ -442,11 +335,6 @@ ; RV64I-NEXT: xor a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinv_i64_no_mask: -; RV64B: # %bb.0: -; RV64B-NEXT: binv a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinv_i64_no_mask: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binv a0, a0, a1 @@ -463,12 +351,6 @@ ; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbext_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: srlw a0, a0, a1 -; RV64B-NEXT: andi a0, a0, 1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbext_i32: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: srlw a0, a0, a1 @@ -487,12 +369,6 @@ ; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbext_i32_no_mask: -; RV64B: # %bb.0: -; RV64B-NEXT: srlw a0, a0, a1 -; RV64B-NEXT: andi a0, a0, 1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbext_i32_no_mask: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: srlw a0, a0, a1 @@ -510,11 +386,6 @@ ; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbext_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: bext a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbext_i64: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bext a0, a0, a1 @@ -532,11 +403,6 @@ ; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbext_i64_no_mask: -; RV64B: # %bb.0: -; RV64B-NEXT: bext a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbext_i64_no_mask: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bext a0, a0, a1 @@ -553,11 +419,6 @@ ; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbexti_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: bexti a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbexti_i32: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bexti a0, a0, 5 @@ -574,11 +435,6 @@ ; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbexti_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: bexti a0, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbexti_i64: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bexti a0, a0, 5 @@ -594,11 +450,6 @@ ; RV64I-NEXT: andi a0, a0, -1025 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i32_10: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a0, a0, -1025 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i32_10: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: andi a0, a0, -1025 @@ -615,11 +466,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i32_11: -; RV64B: # %bb.0: -; RV64B-NEXT: bclri a0, a0, 11 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i32_11: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclri a0, a0, 11 @@ -636,11 +482,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i32_30: -; RV64B: # %bb.0: -; RV64B-NEXT: bclri a0, a0, 30 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i32_30: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclri a0, a0, 30 @@ -657,13 +498,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i32_31: -; RV64B: # %bb.0: -; RV64B-NEXT: lui a1, 524288 -; RV64B-NEXT: addiw a1, a1, -1 -; RV64B-NEXT: and a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i32_31: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: lui a1, 524288 @@ -680,11 +514,6 @@ ; RV64I-NEXT: andi a0, a0, -1025 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i64_10: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a0, a0, -1025 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i64_10: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: andi a0, a0, -1025 @@ -701,11 +530,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i64_11: -; RV64B: # %bb.0: -; RV64B-NEXT: bclri a0, a0, 11 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i64_11: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclri a0, a0, 11 @@ -722,11 +546,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i64_30: -; RV64B: # %bb.0: -; RV64B-NEXT: bclri a0, a0, 30 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i64_30: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclri a0, a0, 30 @@ -744,11 +563,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i64_31: -; RV64B: # %bb.0: -; RV64B-NEXT: bclri a0, a0, 31 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i64_31: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclri a0, a0, 31 @@ -766,11 +580,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i64_62: -; RV64B: # %bb.0: -; RV64B-NEXT: bclri a0, a0, 62 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i64_62: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclri a0, a0, 62 @@ -787,11 +596,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i64_63: -; RV64B: # %bb.0: -; RV64B-NEXT: bclri a0, a0, 63 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i64_63: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclri a0, a0, 63 @@ -808,12 +612,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i64_large0: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a0, a0, -256 -; RV64B-NEXT: bclri a0, a0, 24 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i64_large0: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: andi a0, a0, -256 @@ -831,12 +629,6 @@ ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbclri_i64_large1: -; RV64B: # %bb.0: -; RV64B-NEXT: bclri a0, a0, 16 -; RV64B-NEXT: bclri a0, a0, 24 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbclri_i64_large1: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bclri a0, a0, 16 @@ -852,11 +644,6 @@ ; RV64I-NEXT: ori a0, a0, 1024 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i32_10: -; RV64B: # %bb.0: -; RV64B-NEXT: ori a0, a0, 1024 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i32_10: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: ori a0, a0, 1024 @@ -873,11 +660,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i32_11: -; RV64B: # %bb.0: -; RV64B-NEXT: bseti a0, a0, 11 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i32_11: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bseti a0, a0, 11 @@ -893,11 +675,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i32_30: -; RV64B: # %bb.0: -; RV64B-NEXT: bseti a0, a0, 30 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i32_30: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bseti a0, a0, 30 @@ -913,12 +690,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i32_31: -; RV64B: # %bb.0: -; RV64B-NEXT: lui a1, 524288 -; RV64B-NEXT: or a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i32_31: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: lui a1, 524288 @@ -934,11 +705,6 @@ ; RV64I-NEXT: ori a0, a0, 1024 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i64_10: -; RV64B: # %bb.0: -; RV64B-NEXT: ori a0, a0, 1024 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i64_10: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: ori a0, a0, 1024 @@ -955,11 +721,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i64_11: -; RV64B: # %bb.0: -; RV64B-NEXT: bseti a0, a0, 11 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i64_11: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bseti a0, a0, 11 @@ -975,11 +736,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i64_30: -; RV64B: # %bb.0: -; RV64B-NEXT: bseti a0, a0, 30 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i64_30: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bseti a0, a0, 30 @@ -996,11 +752,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i64_31: -; RV64B: # %bb.0: -; RV64B-NEXT: bseti a0, a0, 31 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i64_31: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bseti a0, a0, 31 @@ -1017,11 +768,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i64_62: -; RV64B: # %bb.0: -; RV64B-NEXT: bseti a0, a0, 62 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i64_62: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bseti a0, a0, 62 @@ -1038,11 +784,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbseti_i64_63: -; RV64B: # %bb.0: -; RV64B-NEXT: bseti a0, a0, 63 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbseti_i64_63: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bseti a0, a0, 63 @@ -1057,11 +798,6 @@ ; RV64I-NEXT: xori a0, a0, 1024 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i32_10: -; RV64B: # %bb.0: -; RV64B-NEXT: xori a0, a0, 1024 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i32_10: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: xori a0, a0, 1024 @@ -1078,11 +814,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i32_11: -; RV64B: # %bb.0: -; RV64B-NEXT: binvi a0, a0, 11 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i32_11: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binvi a0, a0, 11 @@ -1098,11 +829,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i32_30: -; RV64B: # %bb.0: -; RV64B-NEXT: binvi a0, a0, 30 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i32_30: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binvi a0, a0, 30 @@ -1118,12 +844,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i32_31: -; RV64B: # %bb.0: -; RV64B-NEXT: lui a1, 524288 -; RV64B-NEXT: xor a0, a0, a1 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i32_31: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: lui a1, 524288 @@ -1139,11 +859,6 @@ ; RV64I-NEXT: xori a0, a0, 1024 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i64_10: -; RV64B: # %bb.0: -; RV64B-NEXT: xori a0, a0, 1024 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i64_10: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: xori a0, a0, 1024 @@ -1160,11 +875,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i64_11: -; RV64B: # %bb.0: -; RV64B-NEXT: binvi a0, a0, 11 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i64_11: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binvi a0, a0, 11 @@ -1180,11 +890,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i64_30: -; RV64B: # %bb.0: -; RV64B-NEXT: binvi a0, a0, 30 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i64_30: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binvi a0, a0, 30 @@ -1201,11 +906,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i64_31: -; RV64B: # %bb.0: -; RV64B-NEXT: binvi a0, a0, 31 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i64_31: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binvi a0, a0, 31 @@ -1222,11 +922,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i64_62: -; RV64B: # %bb.0: -; RV64B-NEXT: binvi a0, a0, 62 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i64_62: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binvi a0, a0, 62 @@ -1243,11 +938,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: sbinvi_i64_63: -; RV64B: # %bb.0: -; RV64B-NEXT: binvi a0, a0, 63 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: sbinvi_i64_63: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binvi a0, a0, 63 @@ -1265,12 +955,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: xor_i64_large: -; RV64B: # %bb.0: -; RV64B-NEXT: binvi a0, a0, 0 -; RV64B-NEXT: binvi a0, a0, 32 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: xor_i64_large: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: binvi a0, a0, 0 @@ -1288,12 +972,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: xor_i64_4099: -; RV64B: # %bb.0: -; RV64B-NEXT: xori a0, a0, 3 -; RV64B-NEXT: binvi a0, a0, 12 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: xor_i64_4099: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: xori a0, a0, 3 @@ -1309,11 +987,6 @@ ; RV64I-NEXT: xori a0, a0, 96 ; RV64I-NEXT: ret ; -; RV64B-LABEL: xor_i64_96: -; RV64B: # %bb.0: -; RV64B-NEXT: xori a0, a0, 96 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: xor_i64_96: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: xori a0, a0, 96 @@ -1331,12 +1004,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: or_i64_large: -; RV64B: # %bb.0: -; RV64B-NEXT: bseti a0, a0, 0 -; RV64B-NEXT: bseti a0, a0, 32 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: or_i64_large: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: bseti a0, a0, 0 @@ -1354,12 +1021,6 @@ ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: xor_i64_66901: -; RV64B: # %bb.0: -; RV64B-NEXT: xori a0, a0, 1365 -; RV64B-NEXT: binvi a0, a0, 16 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: xor_i64_66901: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: xori a0, a0, 1365 @@ -1377,12 +1038,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: or_i64_4099: -; RV64B: # %bb.0: -; RV64B-NEXT: ori a0, a0, 3 -; RV64B-NEXT: bseti a0, a0, 12 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: or_i64_4099: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: ori a0, a0, 3 @@ -1398,11 +1053,6 @@ ; RV64I-NEXT: ori a0, a0, 96 ; RV64I-NEXT: ret ; -; RV64B-LABEL: or_i64_96: -; RV64B: # %bb.0: -; RV64B-NEXT: ori a0, a0, 96 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: or_i64_96: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: ori a0, a0, 96 @@ -1419,12 +1069,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: or_i64_66901: -; RV64B: # %bb.0: -; RV64B-NEXT: ori a0, a0, 1365 -; RV64B-NEXT: bseti a0, a0, 16 -; RV64B-NEXT: ret -; ; RV64ZBS-LABEL: or_i64_66901: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: ori a0, a0, 1365 diff --git a/llvm/test/CodeGen/RISCV/rv64zbt.ll b/llvm/test/CodeGen/RISCV/rv64zbt.ll --- a/llvm/test/CodeGen/RISCV/rv64zbt.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbt.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I -; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=RV64B ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZBT @@ -15,11 +13,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmix_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: cmix a0, a1, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmix_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: cmix a0, a1, a0, a2 @@ -40,11 +33,6 @@ ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmix_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: cmix a0, a1, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmix_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: cmix a0, a1, a0, a2 @@ -66,11 +54,6 @@ ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: cmov a0, a1, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: cmov a0, a1, a0, a2 @@ -89,12 +72,6 @@ ; RV64I-NEXT: .LBB3_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_sle_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: slt a1, a2, a1 -; RV64B-NEXT: cmov a0, a1, a3, a0 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_sle_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: slt a1, a2, a1 @@ -114,12 +91,6 @@ ; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_sge_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: slt a1, a1, a2 -; RV64B-NEXT: cmov a0, a1, a3, a0 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_sge_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: slt a1, a1, a2 @@ -139,12 +110,6 @@ ; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_ule_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: sltu a1, a2, a1 -; RV64B-NEXT: cmov a0, a1, a3, a0 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_ule_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: sltu a1, a2, a1 @@ -164,12 +129,6 @@ ; RV64I-NEXT: .LBB6_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_uge_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: sltu a1, a1, a2 -; RV64B-NEXT: cmov a0, a1, a3, a0 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_uge_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: sltu a1, a1, a2 @@ -190,11 +149,6 @@ ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: cmov a0, a1, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: cmov a0, a1, a0, a2 @@ -213,12 +167,6 @@ ; RV64I-NEXT: .LBB8_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_sle_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: slt a1, a2, a1 -; RV64B-NEXT: cmov a0, a1, a3, a0 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_sle_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: slt a1, a2, a1 @@ -238,12 +186,6 @@ ; RV64I-NEXT: .LBB9_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_sge_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: slt a1, a1, a2 -; RV64B-NEXT: cmov a0, a1, a3, a0 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_sge_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: slt a1, a1, a2 @@ -263,12 +205,6 @@ ; RV64I-NEXT: .LBB10_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_ule_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: sltu a1, a2, a1 -; RV64B-NEXT: cmov a0, a1, a3, a0 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_ule_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: sltu a1, a2, a1 @@ -288,12 +224,6 @@ ; RV64I-NEXT: .LBB11_2: ; RV64I-NEXT: ret ; -; RV64B-LABEL: cmov_uge_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: sltu a1, a1, a2 -; RV64B-NEXT: cmov a0, a1, a3, a0 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: cmov_uge_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: sltu a1, a1, a2 @@ -318,12 +248,6 @@ ; RV64I-NEXT: srai a0, a0, 32 ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshl_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a2, a2, 31 -; RV64B-NEXT: fslw a0, a0, a1, a2 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshl_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: andi a2, a2, 31 @@ -347,13 +271,6 @@ ; RV64I-NEXT: sw a0, 0(a3) ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshl_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a2, a2, 31 -; RV64B-NEXT: fslw a0, a0, a1, a2 -; RV64B-NEXT: sw a0, 0(a3) -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshl_i32_nosext: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: andi a2, a2, 31 @@ -377,12 +294,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshl_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a2, a2, 63 -; RV64B-NEXT: fsl a0, a0, a1, a2 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshl_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: andi a2, a2, 63 @@ -406,12 +317,6 @@ ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshr_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a2, a2, 31 -; RV64B-NEXT: fsrw a0, a1, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshr_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: andi a2, a2, 31 @@ -434,13 +339,6 @@ ; RV64I-NEXT: sw a0, 0(a3) ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshr_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a2, a2, 31 -; RV64B-NEXT: fsrw a0, a1, a0, a2 -; RV64B-NEXT: sw a0, 0(a3) -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshr_i32_nosext: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: andi a2, a2, 31 @@ -464,12 +362,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshr_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: andi a2, a2, 63 -; RV64B-NEXT: fsr a0, a1, a0, a2 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshr_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: andi a2, a2, 63 @@ -488,11 +380,6 @@ ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshri_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: fsriw a0, a1, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshri_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: fsriw a0, a1, a0, 5 @@ -511,12 +398,6 @@ ; RV64I-NEXT: sw a0, 0(a2) ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshri_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: fsriw a0, a1, a0, 5 -; RV64B-NEXT: sw a0, 0(a2) -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshri_i32_nosext: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: fsriw a0, a1, a0, 5 @@ -535,11 +416,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshri_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: fsri a0, a1, a0, 5 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshri_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: fsri a0, a1, a0, 5 @@ -557,11 +433,6 @@ ; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshli_i32: -; RV64B: # %bb.0: -; RV64B-NEXT: fsriw a0, a1, a0, 27 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshli_i32: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: fsriw a0, a1, a0, 27 @@ -580,12 +451,6 @@ ; RV64I-NEXT: sw a0, 0(a2) ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshli_i32_nosext: -; RV64B: # %bb.0: -; RV64B-NEXT: fsriw a0, a1, a0, 27 -; RV64B-NEXT: sw a0, 0(a2) -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshli_i32_nosext: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: fsriw a0, a1, a0, 27 @@ -604,11 +469,6 @@ ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; -; RV64B-LABEL: fshli_i64: -; RV64B: # %bb.0: -; RV64B-NEXT: fsri a0, a1, a0, 59 -; RV64B-NEXT: ret -; ; RV64ZBT-LABEL: fshli_i64: ; RV64ZBT: # %bb.0: ; RV64ZBT-NEXT: fsri a0, a1, a0, 59 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -36,9 +36,6 @@ .attribute arch, "rv32ima2p_fdc" # CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" -.attribute arch, "rv32ib" -# CHECK: attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93" - .attribute arch, "rv32iv" # CHECK: attribute 5, "rv32i2p0_v0p10" diff --git a/llvm/test/MC/RISCV/rv32zba-valid.s b/llvm/test/MC/RISCV/rv32zba-valid.s --- a/llvm/test/MC/RISCV/rv32zba-valid.s +++ b/llvm/test/MC/RISCV/rv32zba-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip base extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zba -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbb-aliases-valid.s b/llvm/test/MC/RISCV/rv32zbb-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zbb-aliases-valid.s @@ -0,0 +1,32 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbb < %s \ +# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbb - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbb < %s \ +# RUN: | llvm-objdump -d -r --mattr=+experimental-zbb - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s + +# The following check prefixes are used in this test: +# CHECK-S-OBJ Match both the .s and objdumped object output with +# aliases enabled +# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with +# aliases disabled + +# CHECK-S-OBJ-NOALIAS: zext.h t0, t1 +# CHECK-S-OBJ: zext.h t0, t1 +zext.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: rev8 t0, t1 +# CHECK-S-OBJ: rev8 t0, t1 +rev8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: orc.b t0, t1 +# CHECK-S-OBJ: orc.b t0, t1 +orc.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8 +# CHECK-S-OBJ: rori t0, t1, 8 +ror x5, x6, 8 diff --git a/llvm/test/MC/RISCV/rv32zbb-valid.s b/llvm/test/MC/RISCV/rv32zbb-valid.s --- a/llvm/test/MC/RISCV/rv32zbb-valid.s +++ b/llvm/test/MC/RISCV/rv32zbb-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip base extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbbp-only-valid.s b/llvm/test/MC/RISCV/rv32zbbp-only-valid.s --- a/llvm/test/MC/RISCV/rv32zbbp-only-valid.s +++ b/llvm/test/MC/RISCV/rv32zbbp-only-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip base extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbbp-valid.s b/llvm/test/MC/RISCV/rv32zbbp-valid.s --- a/llvm/test/MC/RISCV/rv32zbbp-valid.s +++ b/llvm/test/MC/RISCV/rv32zbbp-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip base extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbc-valid.s b/llvm/test/MC/RISCV/rv32zbc-valid.s --- a/llvm/test/MC/RISCV/rv32zbc-valid.s +++ b/llvm/test/MC/RISCV/rv32zbc-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip carry-less multiply extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbc -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbe-valid.s b/llvm/test/MC/RISCV/rv32zbe-valid.s --- a/llvm/test/MC/RISCV/rv32zbe-valid.s +++ b/llvm/test/MC/RISCV/rv32zbe-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip extract/deposit extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbe -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbf-valid.s b/llvm/test/MC/RISCV/rv32zbf-valid.s --- a/llvm/test/MC/RISCV/rv32zbf-valid.s +++ b/llvm/test/MC/RISCV/rv32zbf-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bit-Field extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbf -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32b-aliases-valid.s b/llvm/test/MC/RISCV/rv32zbp-aliases-valid.s rename from llvm/test/MC/RISCV/rv32b-aliases-valid.s rename to llvm/test/MC/RISCV/rv32zbp-aliases-valid.s --- a/llvm/test/MC/RISCV/rv32b-aliases-valid.s +++ b/llvm/test/MC/RISCV/rv32zbp-aliases-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -riscv-no-aliases \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -riscv-no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-b - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbp < %s \ +# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbp - \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump -d -r --mattr=+experimental-b - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbp < %s \ +# RUN: | llvm-objdump -d -r --mattr=+experimental-zbp - \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s # The following check prefixes are used in this test: @@ -15,10 +15,6 @@ # CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with # aliases disabled -# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255 -# CHECK-S-OBJ: andi t0, t1, 255 -zext.b x5, x6 - # CHECK-S-OBJ-NOALIAS: zext.h t0, t1 # CHECK-S-OBJ: zext.h t0, t1 zext.h x5, x6 @@ -227,22 +223,6 @@ # CHECK-S-OBJ: rori t0, t1, 8 ror x5, x6, 8 -# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8 -# CHECK-S-OBJ: bseti t0, t1, 8 -bset x5, x6, 8 - -# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8 -# CHECK-S-OBJ: bclri t0, t1, 8 -bclr x5, x6, 8 - -# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8 -# CHECK-S-OBJ: binvi t0, t1, 8 -binv x5, x6, 8 - -# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8 -# CHECK-S-OBJ: bexti t0, t1, 8 -bext x5, x6, 8 - # CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13 # CHECK-S-OBJ: grevi t0, t1, 13 grev x5, x6, 13 diff --git a/llvm/test/MC/RISCV/rv32zbp-only-valid.s b/llvm/test/MC/RISCV/rv32zbp-only-valid.s --- a/llvm/test/MC/RISCV/rv32zbp-only-valid.s +++ b/llvm/test/MC/RISCV/rv32zbp-only-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefix=CHECK-ASM %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-OBJ %s - # With Bitmanip permutation extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \ # RUN: | FileCheck -check-prefix=CHECK-ASM %s diff --git a/llvm/test/MC/RISCV/rv32zbp-valid.s b/llvm/test/MC/RISCV/rv32zbp-valid.s --- a/llvm/test/MC/RISCV/rv32zbp-valid.s +++ b/llvm/test/MC/RISCV/rv32zbp-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s - # With Bitmanip permutation extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbr-valid.s b/llvm/test/MC/RISCV/rv32zbr-valid.s --- a/llvm/test/MC/RISCV/rv32zbr-valid.s +++ b/llvm/test/MC/RISCV/rv32zbr-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip CRC extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbr -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbs-aliases-valid.s b/llvm/test/MC/RISCV/rv32zbs-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zbs-aliases-valid.s @@ -0,0 +1,32 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -riscv-no-aliases \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbs < %s \ +# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbs - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbs < %s \ +# RUN: | llvm-objdump -d -r --mattr=+experimental-zbs - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s + +# The following check prefixes are used in this test: +# CHECK-S-OBJ Match both the .s and objdumped object output with +# aliases enabled +# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with +# aliases disabled + +# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8 +# CHECK-S-OBJ: bseti t0, t1, 8 +bset x5, x6, 8 + +# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8 +# CHECK-S-OBJ: bclri t0, t1, 8 +bclr x5, x6, 8 + +# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8 +# CHECK-S-OBJ: binvi t0, t1, 8 +binv x5, x6, 8 + +# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8 +# CHECK-S-OBJ: bexti t0, t1, 8 +bext x5, x6, 8 diff --git a/llvm/test/MC/RISCV/rv32zbs-invalid.s b/llvm/test/MC/RISCV/rv32zbs-invalid.s --- a/llvm/test/MC/RISCV/rv32zbs-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbs-invalid.s @@ -28,10 +28,3 @@ # Immediate operand out of range bexti t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] bexti t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] -bclrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bsetw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -binvw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bextw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bclriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bsetiw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -binviw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rv32zbs-valid.s b/llvm/test/MC/RISCV/rv32zbs-valid.s --- a/llvm/test/MC/RISCV/rv32zbs-valid.s +++ b/llvm/test/MC/RISCV/rv32zbs-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip single bit extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32zbt-valid.s b/llvm/test/MC/RISCV/rv32zbt-valid.s --- a/llvm/test/MC/RISCV/rv32zbt-valid.s +++ b/llvm/test/MC/RISCV/rv32zbt-valid.s @@ -1,15 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip ternary extension: # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbt -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64zba-aliases-valid.s b/llvm/test/MC/RISCV/rv64zba-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zba-aliases-valid.s @@ -0,0 +1,34 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -riscv-no-aliases \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zba < %s \ +# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zba - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zba < %s \ +# RUN: | llvm-objdump -d -r --mattr=+experimental-zba - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s + +# The following check prefixes are used in this test: +# CHECK-S-OBJ Match both the .s and objdumped object output with +# aliases enabled +# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with +# aliases disabled + +# CHECK-S-OBJ-NOALIAS: add.uw t0, t1, zero +# CHECK-S-OBJ: zext.w t0, t1 +zext.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: addi t1, zero, -2 +# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t1, t1, zero +# CHECK-S-OBJ: addi t1, zero, -2 +# CHECK-S-OBJ-NEXT: zext.w t1, t1 +li x6, 0xfffffffe + +# CHECK-S-OBJ-NOALIAS: lui t2, 699051 +# CHECK-S-OBJ-NOALIAS-NEXT: addiw t2, t2, -1366 +# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t2, t2, zero +# CHECK-S-OBJ: lui t2, 699051 +# CHECK-S-OBJ-NEXT: addiw t2, t2, -1366 +# CHECK-S-OBJ-NEXT: zext.w t2, t2 +li x7, 0xaaaaaaaa diff --git a/llvm/test/MC/RISCV/rv64zba-valid.s b/llvm/test/MC/RISCV/rv64zba-valid.s --- a/llvm/test/MC/RISCV/rv64zba-valid.s +++ b/llvm/test/MC/RISCV/rv64zba-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip base extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64zbb-aliases-valid.s b/llvm/test/MC/RISCV/rv64zbb-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zbb-aliases-valid.s @@ -0,0 +1,36 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbb < %s \ +# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbb - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbb < %s \ +# RUN: | llvm-objdump -d -r --mattr=+experimental-zbb - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s + +# The following check prefixes are used in this test: +# CHECK-S-OBJ Match both the .s and objdumped object output with +# aliases enabled +# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with +# aliases disabled + +# CHECK-S-OBJ-NOALIAS: zext.h t0, t1 +# CHECK-S-OBJ: zext.h t0, t1 +zext.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: rev8 t0, t1 +# CHECK-S-OBJ: rev8 t0, t1 +rev8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: orc.b t0, t1 +# CHECK-S-OBJ: orc.b t0, t1 +orc.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8 +# CHECK-S-OBJ: rori t0, t1, 8 +ror x5, x6, 8 + +# CHECK-S-OBJ-NOALIAS: roriw t0, t1, 8 +# CHECK-S-OBJ: roriw t0, t1, 8 +rorw x5, x6, 8 diff --git a/llvm/test/MC/RISCV/rv64zbb-valid.s b/llvm/test/MC/RISCV/rv64zbb-valid.s --- a/llvm/test/MC/RISCV/rv64zbb-valid.s +++ b/llvm/test/MC/RISCV/rv64zbb-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip base extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64zbbp-valid.s b/llvm/test/MC/RISCV/rv64zbbp-valid.s --- a/llvm/test/MC/RISCV/rv64zbbp-valid.s +++ b/llvm/test/MC/RISCV/rv64zbbp-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip base extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64zbe-valid.s b/llvm/test/MC/RISCV/rv64zbe-valid.s --- a/llvm/test/MC/RISCV/rv64zbe-valid.s +++ b/llvm/test/MC/RISCV/rv64zbe-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip extract/deposit extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64zbf-valid.s b/llvm/test/MC/RISCV/rv64zbf-valid.s --- a/llvm/test/MC/RISCV/rv64zbf-valid.s +++ b/llvm/test/MC/RISCV/rv64zbf-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bit-Field extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbf -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64zbm-valid.s b/llvm/test/MC/RISCV/rv64zbm-valid.s --- a/llvm/test/MC/RISCV/rv64zbm-valid.s +++ b/llvm/test/MC/RISCV/rv64zbm-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip matix extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbm -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64b-aliases-valid.s b/llvm/test/MC/RISCV/rv64zbp-aliases-valid.s rename from llvm/test/MC/RISCV/rv64b-aliases-valid.s rename to llvm/test/MC/RISCV/rv64zbp-aliases-valid.s --- a/llvm/test/MC/RISCV/rv64b-aliases-valid.s +++ b/llvm/test/MC/RISCV/rv64zbp-aliases-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -riscv-no-aliases \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -riscv-no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-b - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbp < %s \ +# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbp - \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump -d -r --mattr=+experimental-b - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbp < %s \ +# RUN: | llvm-objdump -d -r --mattr=+experimental-zbp - \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s # The following check prefixes are used in this test: @@ -15,18 +15,10 @@ # CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with # aliases disabled -# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255 -# CHECK-S-OBJ: andi t0, t1, 255 -zext.b x5, x6 - # CHECK-S-OBJ-NOALIAS: zext.h t0, t1 # CHECK-S-OBJ: zext.h t0, t1 zext.h x5, x6 -# CHECK-S-OBJ-NOALIAS: add.uw t0, t1, zero -# CHECK-S-OBJ: zext.w t0, t1 -zext.w x5, x6 - # CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1 # CHECK-S-OBJ: rev.p t0, t1 rev.p x5, x6 @@ -323,22 +315,6 @@ # CHECK-S-OBJ: roriw t0, t1, 8 rorw x5, x6, 8 -# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8 -# CHECK-S-OBJ: bseti t0, t1, 8 -bset x5, x6, 8 - -# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8 -# CHECK-S-OBJ: bclri t0, t1, 8 -bclr x5, x6, 8 - -# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8 -# CHECK-S-OBJ: binvi t0, t1, 8 -binv x5, x6, 8 - -# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8 -# CHECK-S-OBJ: bexti t0, t1, 8 -bext x5, x6, 8 - # CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13 # CHECK-S-OBJ: grevi t0, t1, 13 grev x5, x6, 13 @@ -362,17 +338,3 @@ # CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13 # CHECK-S-OBJ: gorciw t0, t1, 13 gorcw x5, x6, 13 - -# CHECK-S-OBJ-NOALIAS: addi t1, zero, -2 -# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t1, t1, zero -# CHECK-S-OBJ: addi t1, zero, -2 -# CHECK-S-OBJ-NEXT: zext.w t1, t1 -li x6, 0xfffffffe - -# CHECK-S-OBJ-NOALIAS: lui t2, 699051 -# CHECK-S-OBJ-NOALIAS-NEXT: addiw t2, t2, -1366 -# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t2, t2, zero -# CHECK-S-OBJ: lui t2, 699051 -# CHECK-S-OBJ-NEXT: addiw t2, t2, -1366 -# CHECK-S-OBJ-NEXT: zext.w t2, t2 -li x7, 0xaaaaaaaa diff --git a/llvm/test/MC/RISCV/rv64zbp-valid.s b/llvm/test/MC/RISCV/rv64zbp-valid.s --- a/llvm/test/MC/RISCV/rv64zbp-valid.s +++ b/llvm/test/MC/RISCV/rv64zbp-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s - # With Bitmanip permutation extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64zbr-valid.s b/llvm/test/MC/RISCV/rv64zbr-valid.s --- a/llvm/test/MC/RISCV/rv64zbr-valid.s +++ b/llvm/test/MC/RISCV/rv64zbr-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip CRC extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbr -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/rv64zbs-aliases-valid.s b/llvm/test/MC/RISCV/rv64zbs-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zbs-aliases-valid.s @@ -0,0 +1,32 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -riscv-no-aliases \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbs < %s \ +# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbs - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbs < %s \ +# RUN: | llvm-objdump -d -r --mattr=+experimental-zbs - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s + +# The following check prefixes are used in this test: +# CHECK-S-OBJ Match both the .s and objdumped object output with +# aliases enabled +# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with +# aliases disabled + +# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8 +# CHECK-S-OBJ: bseti t0, t1, 8 +bset x5, x6, 8 + +# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8 +# CHECK-S-OBJ: bclri t0, t1, 8 +bclr x5, x6, 8 + +# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8 +# CHECK-S-OBJ: binvi t0, t1, 8 +binv x5, x6, 8 + +# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8 +# CHECK-S-OBJ: bexti t0, t1, 8 +bext x5, x6, 8 diff --git a/llvm/test/MC/RISCV/rv64zbs-invalid.s b/llvm/test/MC/RISCV/rv64zbs-invalid.s deleted file mode 100644 --- a/llvm/test/MC/RISCV/rv64zbs-invalid.s +++ /dev/null @@ -1,25 +0,0 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbs < %s 2>&1 | FileCheck %s - -# Too few operands -bclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -binvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Immediate operand out of range -bclriw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -bclriw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -# Too few operands -bsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Immediate operand out of range -bsetiw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -bsetiw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -# Too few operands -binviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Immediate operand out of range -binviw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -binviw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] diff --git a/llvm/test/MC/RISCV/rv64zbs-valid.s b/llvm/test/MC/RISCV/rv64zbs-valid.s deleted file mode 100644 --- a/llvm/test/MC/RISCV/rv64zbs-valid.s +++ /dev/null @@ -1,35 +0,0 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# With Bitmanip single bit extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbs < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: bclrw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48] -bclrw t0, t1, t2 -# CHECK-ASM-AND-OBJ: bsetw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28] -bsetw t0, t1, t2 -# CHECK-ASM-AND-OBJ: binvw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68] -binvw t0, t1, t2 -# CHECK-ASM-AND-OBJ: bextw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48] -bextw t0, t1, t2 -# CHECK-ASM-AND-OBJ: bclriw t0, t1, 0 -# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48] -bclriw t0, t1, 0 -# CHECK-ASM-AND-OBJ: bsetiw t0, t1, 0 -# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28] -bsetiw t0, t1, 0 -# CHECK-ASM-AND-OBJ: binviw t0, t1, 0 -# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68] -binviw t0, t1, 0 diff --git a/llvm/test/MC/RISCV/rv64zbt-valid.s b/llvm/test/MC/RISCV/rv64zbt-valid.s --- a/llvm/test/MC/RISCV/rv64zbt-valid.s +++ b/llvm/test/MC/RISCV/rv64zbt-valid.s @@ -1,10 +1,3 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - # With Bitmanip ternary extension: # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbt -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/Transforms/LoopIdiom/RISCV/popcnt.ll b/llvm/test/Transforms/LoopIdiom/RISCV/popcnt.ll --- a/llvm/test/Transforms/LoopIdiom/RISCV/popcnt.ll +++ b/llvm/test/Transforms/LoopIdiom/RISCV/popcnt.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -loop-idiom -mtriple=riscv32 -mattr=+experimental-zbb -S < %s | FileCheck %s --check-prefixes=CPOP ; RUN: opt -loop-idiom -mtriple=riscv64 -mattr=+experimental-zbb -S < %s | FileCheck %s --check-prefixes=CPOP -; RUN: opt -loop-idiom -mtriple=riscv32 -mattr=+experimental-b -S < %s | FileCheck %s --check-prefixes=CPOP -; RUN: opt -loop-idiom -mtriple=riscv64 -mattr=+experimental-b -S < %s | FileCheck %s --check-prefixes=CPOP ; RUN: opt -loop-idiom -mtriple=riscv32 -S < %s | FileCheck %s --check-prefixes=NOCPOP ; RUN: opt -loop-idiom -mtriple=riscv64 -S < %s | FileCheck %s --check-prefixes=NOCPOP