Index: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1046,7 +1046,7 @@
     // Insert the spill to the stack frame.
     Register Reg = CS.getReg();
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
-    TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);
+    TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(), RC, TRI);
   }
 
   return true;
Index: llvm/test/CodeGen/RISCV/live_sp.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/live_sp.ll
@@ -0,0 +1,24 @@
+; RUN: llc --stop-after=prologepilog < %s | FileCheck %s
+; https://reviews.llvm.org/D111285
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "riscv64-unknown-unknown-elf"
+
+declare void @vararg(i32 signext, ...)
+
+define void @test1() {
+entry:
+  %a = alloca i32, align 4
+  %0 = call i8* @llvm.returnaddress(i32 0)
+  %1 = ptrtoint i8* %0 to i64
+  %conv = trunc i64 %1 to i32
+  store i32 %conv, i32* %a, align 4
+  %2 = load i32, i32* %a, align 4
+  call void (i32, ...) @vararg(i32 signext 0, i32 signext %2)
+  ret void
+}
+
+; CHECK:    SD $x1, $x2, 8 :: (store (s64) into %stack.1)
+
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.returnaddress(i32 immarg)