Index: clang/lib/Basic/Targets/RISCV.cpp =================================================================== --- clang/lib/Basic/Targets/RISCV.cpp +++ clang/lib/Basic/Targets/RISCV.cpp @@ -187,13 +187,13 @@ } if (HasZba) - Builder.defineMacro("__riscv_zba", "93000"); + Builder.defineMacro("__riscv_zba", "1000000"); if (HasZbb) - Builder.defineMacro("__riscv_zbb", "93000"); + Builder.defineMacro("__riscv_zbb", "1000000"); if (HasZbc) - Builder.defineMacro("__riscv_zbc", "93000"); + Builder.defineMacro("__riscv_zbc", "1000000"); if (HasZbe) Builder.defineMacro("__riscv_zbe", "93000"); @@ -211,7 +211,7 @@ Builder.defineMacro("__riscv_zbr", "93000"); if (HasZbs) - Builder.defineMacro("__riscv_zbs", "93000"); + Builder.defineMacro("__riscv_zbs", "1000000"); if (HasZbt) Builder.defineMacro("__riscv_zbt", "93000"); Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp =================================================================== --- clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -58,9 +58,11 @@ // extension that the compiler currently supports. static Optional isExperimentalExtension(StringRef Ext) { - if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" || + if (Ext == "zba" || Ext == "zbb" || Ext == "zbc" || Ext == "zbs") + return RISCVExtensionVersion{"1", "0"}; + if (Ext == "b" || Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || - Ext == "zbr" || Ext == "zbs" || Ext == "zbt") + Ext == "zbr" || Ext == "zbt") return RISCVExtensionVersion{"0", "93"}; if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg") return RISCVExtensionVersion{"0", "10"}; Index: clang/test/Driver/riscv-arch.c =================================================================== --- clang/test/Driver/riscv-arch.c +++ clang/test/Driver/riscv-arch.c @@ -406,20 +406,20 @@ // RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb' // RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions' -// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s // RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb" -// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93_zbp0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0_zbp0p93 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb" // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp" -// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93zbp0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s -// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb0p93zbp0p93', multi-character extensions must be separated by underscores +// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores -// RUN: %clang -target riscv32-unknown-elf -march=rv32izba0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba" Index: clang/test/Preprocessor/riscv-target-features.c =================================================================== --- clang/test/Preprocessor/riscv-target-features.c +++ clang/test/Preprocessor/riscv-target-features.c @@ -107,43 +107,43 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s // CHECK-B-EXT: __riscv_b 93000 // CHECK-B-EXT: __riscv_bitmanip 1 -// CHECK-B-EXT: __riscv_zba 93000 -// CHECK-B-EXT: __riscv_zbb 93000 -// CHECK-B-EXT: __riscv_zbc 93000 +// CHECK-B-EXT: __riscv_zba 1000000{{$}} +// CHECK-B-EXT: __riscv_zbb 1000000{{$}} +// CHECK-B-EXT: __riscv_zbc 1000000{{$}} // CHECK-B-EXT: __riscv_zbe 93000 // CHECK-B-EXT: __riscv_zbf 93000 // CHECK-B-EXT: __riscv_zbm 93000 // CHECK-B-EXT: __riscv_zbp 93000 // CHECK-B-EXT: __riscv_zbr 93000 -// CHECK-B-EXT: __riscv_zbs 93000 +// CHECK-B-EXT: __riscv_zbs 1000000{{$}} // CHECK-B-EXT: __riscv_zbt 93000 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izba0p93 -x c -E -dM %s \ +// RUN: -march=rv32izba1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izba0p93 -x c -E -dM %s \ +// RUN: -march=rv64izba1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s // CHECK-ZBA-NOT: __riscv_b -// CHECK-ZBA-EXT: __riscv_zba 93000 +// CHECK-ZBA-EXT: __riscv_zba 1000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbb0p93 -x c -E -dM %s \ +// RUN: -march=rv32izbb1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbb0p93 -x c -E -dM %s \ +// RUN: -march=rv64izbb1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s // CHECK-ZBB-NOT: __riscv_b -// CHECK-ZBB-EXT: __riscv_zbb 93000 +// CHECK-ZBB-EXT: __riscv_zbb 1000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbc0p93 -x c -E -dM %s \ +// RUN: -march=rv32izbc1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbc0p93 -x c -E -dM %s \ +// RUN: -march=rv64izbc1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s // CHECK-ZBC-NOT: __riscv_b -// CHECK-ZBC-EXT: __riscv_zbc 93000 +// CHECK-ZBC-EXT: __riscv_zbc 1000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ // RUN: -march=rv32izbe0p93 -x c -E -dM %s \ @@ -191,13 +191,13 @@ // CHECK-ZBR-EXT: __riscv_zbr 93000 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbs0p93 -x c -E -dM %s \ +// RUN: -march=rv32izbs1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbs0p93 -x c -E -dM %s \ +// RUN: -march=rv64izbs1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s // CHECK-ZBS-NOT: __riscv_b -// CHECK-ZBS-EXT: __riscv_zbs 93000 +// CHECK-ZBS-EXT: __riscv_zbs 1000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ // RUN: -march=rv32izbt0p93 -x c -E -dM %s \ Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2189,11 +2189,11 @@ if (getFeatureBits(RISCV::FeatureStdExtZfh)) formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str(); if (getFeatureBits(RISCV::FeatureStdExtZba)) - formalArchStr = (Twine(formalArchStr) + "_zba0p93").str(); + formalArchStr = (Twine(formalArchStr) + "_zba1p0").str(); if (getFeatureBits(RISCV::FeatureStdExtZbb)) - formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str(); + formalArchStr = (Twine(formalArchStr) + "_zbb1p0").str(); if (getFeatureBits(RISCV::FeatureStdExtZbc)) - formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str(); + formalArchStr = (Twine(formalArchStr) + "_zbc1p0").str(); if (getFeatureBits(RISCV::FeatureStdExtZbe)) formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str(); if (getFeatureBits(RISCV::FeatureStdExtZbf)) @@ -2205,7 +2205,7 @@ if (getFeatureBits(RISCV::FeatureStdExtZbr)) formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str(); if (getFeatureBits(RISCV::FeatureStdExtZbs)) - formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str(); + formalArchStr = (Twine(formalArchStr) + "_zbs1p0").str(); if (getFeatureBits(RISCV::FeatureStdExtZbt)) formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str(); if (getFeatureBits(RISCV::FeatureStdExtZvamo)) Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -67,11 +67,11 @@ if (STI.hasFeature(RISCV::FeatureStdExtZfh)) Arch += "_zfh0p1"; if (STI.hasFeature(RISCV::FeatureStdExtZba)) - Arch += "_zba0p93"; + Arch += "_zba1p0"; if (STI.hasFeature(RISCV::FeatureStdExtZbb)) - Arch += "_zbb0p93"; + Arch += "_zbb1p0"; if (STI.hasFeature(RISCV::FeatureStdExtZbc)) - Arch += "_zbc0p93"; + Arch += "_zbc1p0"; if (STI.hasFeature(RISCV::FeatureStdExtZbe)) Arch += "_zbe0p93"; if (STI.hasFeature(RISCV::FeatureStdExtZbf)) @@ -83,7 +83,7 @@ if (STI.hasFeature(RISCV::FeatureStdExtZbr)) Arch += "_zbr0p93"; if (STI.hasFeature(RISCV::FeatureStdExtZbs)) - Arch += "_zbs0p93"; + Arch += "_zbs1p0"; if (STI.hasFeature(RISCV::FeatureStdExtZbt)) Arch += "_zbt0p93"; if (STI.hasFeature(RISCV::FeatureStdExtZvamo)) Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -6,9 +6,19 @@ // //===----------------------------------------------------------------------===// // -// This file describes the RISC-V instructions from the standard 'B' Bitmanip -// extension, version 0.93. -// This version is still experimental as the 'B' extension hasn't been +// This file describes the RISC-V instructions from the standard Bitmanip +// extensions, versions: +// Zba - 1.0 +// Zbb - 1.0 +// Zbc - 1.0 +// Zbs - 1.0 +// Zbe - 0.93 +// Zbf - 0.93 +// Zbm - 0.93 +// Zbp - 0.93 +// Zbr - 0.93 +// Zbt - 0.93 +// This version is still experimental as the Bitmanip extensions haven't been // ratified yet. // //===----------------------------------------------------------------------===// @@ -485,15 +495,6 @@ Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>; } // Predicates = [HasStdExtZbbOrZbp, IsRV64] -let Predicates = [HasStdExtZbs, IsRV64] in { -// NOTE: These instructions have been removed from the 0.94 spec. As a result -// we have no isel patterns for them. -def BCLRW : ALUW_rr<0b0100100, 0b001, "bclrw">, Sched<[]>; -def BSETW : ALUW_rr<0b0010100, 0b001, "bsetw">, Sched<[]>; -def BINVW : ALUW_rr<0b0110100, 0b001, "binvw">, Sched<[]>; -def BEXTW : ALUW_rr<0b0100100, 0b101, "bextw">, Sched<[]>; -} // Predicates = [HasStdExtZbs, IsRV64] - let Predicates = [HasStdExtZbp, IsRV64] in { def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>; def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>; @@ -507,17 +508,6 @@ def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, Sched<[WriteRotateImm32, ReadRotateImm32]>; -let Predicates = [HasStdExtZbs, IsRV64] in { -// NOTE: These instructions have been removed from the 0.94 spec. As a result -// we have no isel patterns for them. -def BCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "bclriw">, - Sched<[]>; -def BSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "bsetiw">, - Sched<[]>; -def BINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "binviw">, - Sched<[]>; -} // Predicates = [HasStdExtZbs, IsRV64] - let Predicates = [HasStdExtZbp, IsRV64] in { def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>; def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>; @@ -615,8 +605,6 @@ //===----------------------------------------------------------------------===// let Predicates = [HasStdExtZba, IsRV64] in { -// NOTE: The 0.93 spec shows zext.w as an alias of pack/packw. It has been -// changed to add.uw in a draft after 0.94. def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>; } Index: llvm/test/CodeGen/RISCV/attributes.ll =================================================================== --- llvm/test/CodeGen/RISCV/attributes.ll +++ llvm/test/CodeGen/RISCV/attributes.ll @@ -44,40 +44,40 @@ ; RV32F: .attribute 5, "rv32i2p0_f2p0" ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32C: .attribute 5, "rv32i2p0_c2p0" -; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93" +; RV32B: .attribute 5, "rv32i2p0_b0p93_zba1p0_zbb1p0_zbc1p0_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs1p0_zbt0p93" ; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1" -; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93" -; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93" -; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93" +; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0" +; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0" +; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0" ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93" ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93" ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93" ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93" ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" -; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93" +; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" -; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10" +; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64A: .attribute 5, "rv64i2p0_a2p0" ; RV64F: .attribute 5, "rv64i2p0_f2p0" ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64C: .attribute 5, "rv64i2p0_c2p0" -; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93" +; RV64B: .attribute 5, "rv64i2p0_b0p93_zba1p0_zbb1p0_zbc1p0_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs1p0_zbt0p93" ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1" -; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93" -; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93" -; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93" +; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0" +; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0" +; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0" ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93" ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93" ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93" ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93" ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" -; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93" +; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10" -; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10" +; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10" define i32 @addi(i32 %a) { Index: llvm/test/MC/RISCV/attribute-arch.s =================================================================== --- llvm/test/MC/RISCV/attribute-arch.s +++ llvm/test/MC/RISCV/attribute-arch.s @@ -37,19 +37,19 @@ # CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" .attribute arch, "rv32ib" -# CHECK: attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93" +# CHECK: attribute 5, "rv32i2p0_b0p93_zba1p0_zbb1p0_zbc1p0_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs1p0_zbt0p93" .attribute arch, "rv32iv" # CHECK: attribute 5, "rv32i2p0_v0p10" .attribute arch, "rv32izba" -# CHECK: attribute 5, "rv32i2p0_zba0p93" +# CHECK: attribute 5, "rv32i2p0_zba1p0" .attribute arch, "rv32izbb" -# CHECK: attribute 5, "rv32i2p0_zbb0p93" +# CHECK: attribute 5, "rv32i2p0_zbb1p0" .attribute arch, "rv32izbc" -# CHECK: attribute 5, "rv32i2p0_zbc0p93" +# CHECK: attribute 5, "rv32i2p0_zbc1p0" .attribute arch, "rv32izbe" # CHECK: attribute 5, "rv32i2p0_zbe0p93" @@ -67,7 +67,7 @@ # CHECK: attribute 5, "rv32i2p0_zbr0p93" .attribute arch, "rv32izbs" -# CHECK: attribute 5, "rv32i2p0_zbs0p93" +# CHECK: attribute 5, "rv32i2p0_zbs1p0" .attribute arch, "rv32izbt" # CHECK: attribute 5, "rv32i2p0_zbt0p93" Index: llvm/test/MC/RISCV/rv32zbs-invalid.s =================================================================== --- llvm/test/MC/RISCV/rv32zbs-invalid.s +++ llvm/test/MC/RISCV/rv32zbs-invalid.s @@ -28,10 +28,3 @@ # Immediate operand out of range bexti t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] bexti t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] -bclrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bsetw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -binvw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bextw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bclriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bsetiw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -binviw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set Index: llvm/test/MC/RISCV/rv64zbs-invalid.s =================================================================== --- llvm/test/MC/RISCV/rv64zbs-invalid.s +++ /dev/null @@ -1,25 +0,0 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbs < %s 2>&1 | FileCheck %s - -# Too few operands -bclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -binvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Too few operands -bclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Immediate operand out of range -bclriw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -bclriw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -# Too few operands -bsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Immediate operand out of range -bsetiw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -bsetiw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -# Too few operands -binviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -# Immediate operand out of range -binviw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] -binviw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31] Index: llvm/test/MC/RISCV/rv64zbs-valid.s =================================================================== --- llvm/test/MC/RISCV/rv64zbs-valid.s +++ /dev/null @@ -1,35 +0,0 @@ -# With B extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ -# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# With Bitmanip single bit extension: -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbs < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: bclrw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48] -bclrw t0, t1, t2 -# CHECK-ASM-AND-OBJ: bsetw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28] -bsetw t0, t1, t2 -# CHECK-ASM-AND-OBJ: binvw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68] -binvw t0, t1, t2 -# CHECK-ASM-AND-OBJ: bextw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48] -bextw t0, t1, t2 -# CHECK-ASM-AND-OBJ: bclriw t0, t1, 0 -# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48] -bclriw t0, t1, 0 -# CHECK-ASM-AND-OBJ: bsetiw t0, t1, 0 -# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28] -bsetiw t0, t1, 0 -# CHECK-ASM-AND-OBJ: binviw t0, t1, 0 -# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68] -binviw t0, t1, 0