Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5469,12 +5469,15 @@ // \brief Some Thumb1 instructions have two operand forms that are not // available as three operand, convert to two operand form if possible. +// For most Thumb2 cases we just generate the 3 operand form and +// reduce it in processInstruction, but for ADD involving PC the the 3 +// operand form won't accept PC so we do the transformation here. // // FIXME: We would really like to be able to tablegen'erate this. void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting, OperandVector &Operands) { - if (Operands.size() != 6 || !isThumbOne()) + if (Operands.size() != 6) return; ARMOperand &Op3 = static_cast(*Operands[3]); @@ -5483,6 +5486,13 @@ return; ARMOperand &Op5 = static_cast(*Operands[5]); + if (isThumbTwo()) { + if (Mnemonic != "add" || + !(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC || + (Op5.isReg() && Op5.getReg() == ARM::PC))) + return; + } else if (!isThumbOne()) + return; // If first 2 operands of a 3 operand instruction are the same // then transform to 2 operand version of the same instruction Index: test/MC/ARM/thumb2-narrow-dp.ll =================================================================== --- test/MC/ARM/thumb2-narrow-dp.ll +++ test/MC/ARM/thumb2-narrow-dp.ll @@ -65,6 +65,10 @@ ADD r3, r3, r1 // T2 // CHECK: add r3, r1 @ encoding: [0x0b,0x44] + ADD r4, r4, pc // T2 +// CHECK: add r4, pc @ encoding: [0x7c,0x44] + ADD pc, pc, r2 // T2 +// CHECK: add pc, r2 @ encoding: [0x97,0x44] // ADD (SP plus immediate) A8.8.9 ADD sp, sp, #20 // T2