Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45450,8 +45450,8 @@
 }
 
 /// If both input operands of a logic op are being cast from floating point
-/// types, try to convert this into a floating point logic node to avoid
-/// unnecessary moves from SSE to integer registers.
+/// types or FP compares, try to convert this into a floating-point logic node
+/// to avoid unnecessary moves from SSE to integer registers.
 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
                                         TargetLowering::DAGCombinerInfo &DCI,
                                         const X86Subtarget &Subtarget) {
@@ -45460,10 +45460,8 @@
   SDValue N1 = N->getOperand(1);
   SDLoc DL(N);
 
-  if (N0.getOpcode() != ISD::BITCAST || N1.getOpcode() != ISD::BITCAST)
-    return SDValue();
-
-  if (DCI.isBeforeLegalizeOps())
+  if (!((N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) ||
+        (N0.getOpcode() == ISD::SETCC && N1.getOpcode() == ISD::SETCC)))
     return SDValue();
 
   SDValue N00 = N0.getOperand(0);
@@ -45477,9 +45475,46 @@
                               (Subtarget.hasFP16() && N00Type == MVT::f16)))
     return SDValue();
 
-  unsigned FPOpcode = convertIntLogicToFPLogicOpcode(N->getOpcode());
-  SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
-  return DAG.getBitcast(VT, FPLogic);
+  if (N0.getOpcode() == ISD::BITCAST && !DCI.isBeforeLegalizeOps()) {
+    unsigned FPOpcode = convertIntLogicToFPLogicOpcode(N->getOpcode());
+    SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
+    return DAG.getBitcast(VT, FPLogic);
+  }
+
+  // The vector ISA for FP predicates is incomplete before AVX, so converting
+  // COMIS* to CMPS* may not be a win before AVX.
+  // TODO: Check types/predicates to see if they are available with SSE/SSE2.
+  if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse() || !N1.hasOneUse() ||
+      !Subtarget.hasAVX())
+    return SDValue();
+
+  // Convert scalar FP compares and logic to vector compares (COMIS* to CMPS*)
+  // and vector logic:
+  // logic (setcc N00, N01), (setcc N10, N11) -->
+  // setcc0 = (setcc (inselt undef, N00, 0), (inselt undef, N01, 0))
+  // setcc1 = (setcc (inselt undef, N10, 0), (inselt undef, N11, 0))
+  // extelt (logic setcc0, setcc1), 0
+  unsigned NumElts = 128 / N00Type.getSizeInBits();
+  EVT VecVT = EVT::getVectorVT(*DAG.getContext(), N00Type, NumElts);
+  EVT BoolVecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElts);
+  SDValue BaseVec = DAG.getUNDEF(VecVT);
+  SDValue ZeroIndex = DAG.getVectorIdxConstant(0, DL);
+  SDValue N01 = N0.getOperand(1);
+  SDValue N11 = N1.getOperand(1);
+  SDValue InsN00 =
+      DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecVT, BaseVec, N00, ZeroIndex);
+  SDValue InsN01 =
+      DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecVT, BaseVec, N01, ZeroIndex);
+  SDValue InsN10 =
+      DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecVT, BaseVec, N10, ZeroIndex);
+  SDValue InsN11 =
+      DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecVT, BaseVec, N11, ZeroIndex);
+  SDValue Setcc0 = DAG.getSetCC(DL, BoolVecVT, InsN00, InsN01,
+                                cast<CondCodeSDNode>(N0.getOperand(2))->get());
+  SDValue Setcc1 = DAG.getSetCC(DL, BoolVecVT, InsN10, InsN11,
+                                cast<CondCodeSDNode>(N1.getOperand(2))->get());
+  SDValue Logic = DAG.getNode(N->getOpcode(), DL, BoolVecVT, Setcc0, Setcc1);
+  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Logic, ZeroIndex);
 }
 
 // Attempt to fold BITOP(MOVMSK(X),MOVMSK(Y)) -> MOVMSK(BITOP(X,Y))
Index: llvm/test/CodeGen/X86/fcmp-logic.ll
===================================================================
--- llvm/test/CodeGen/X86/fcmp-logic.ll
+++ llvm/test/CodeGen/X86/fcmp-logic.ll
@@ -14,11 +14,11 @@
 ;
 ; AVX-LABEL: olt_ole_and_f32:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vucomiss %xmm0, %xmm1
-; AVX-NEXT:    seta %cl
-; AVX-NEXT:    vucomiss %xmm2, %xmm3
-; AVX-NEXT:    setae %al
-; AVX-NEXT:    andb %cl, %al
+; AVX-NEXT:    vcmpleps %xmm3, %xmm2, %xmm2
+; AVX-NEXT:    vcmpltps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vandps %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-NEXT:    retq
   %f1 = fcmp olt float %w, %x
   %f2 = fcmp ole float %y, %z
@@ -40,13 +40,11 @@
 ;
 ; AVX-LABEL: oge_oeq_or_f32:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vucomiss %xmm1, %xmm0
-; AVX-NEXT:    setae %cl
-; AVX-NEXT:    vucomiss %xmm3, %xmm2
-; AVX-NEXT:    setnp %dl
-; AVX-NEXT:    sete %al
-; AVX-NEXT:    andb %dl, %al
-; AVX-NEXT:    orb %cl, %al
+; AVX-NEXT:    vcmpeqps %xmm3, %xmm2, %xmm2
+; AVX-NEXT:    vcmpleps %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vorps %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-NEXT:    retq
   %f1 = fcmp oge float %w, %x
   %f2 = fcmp oeq float %y, %z
@@ -66,11 +64,11 @@
 ;
 ; AVX-LABEL: ord_one_xor_f32:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vucomiss %xmm1, %xmm0
-; AVX-NEXT:    setnp %cl
-; AVX-NEXT:    vucomiss %xmm3, %xmm2
-; AVX-NEXT:    setne %al
-; AVX-NEXT:    xorb %cl, %al
+; AVX-NEXT:    vcmpneq_oqps %xmm3, %xmm2, %xmm2
+; AVX-NEXT:    vcmpordps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vxorps %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-NEXT:    retq
   %f1 = fcmp ord float %w, %x
   %f2 = fcmp one float %y, %z
@@ -92,13 +90,11 @@
 ;
 ; AVX-LABEL: une_ugt_and_f64:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vucomisd %xmm1, %xmm0
-; AVX-NEXT:    setp %al
-; AVX-NEXT:    setne %cl
-; AVX-NEXT:    orb %al, %cl
-; AVX-NEXT:    vucomisd %xmm2, %xmm3
-; AVX-NEXT:    setb %al
-; AVX-NEXT:    andb %cl, %al
+; AVX-NEXT:    vcmpnlepd %xmm3, %xmm2, %xmm2
+; AVX-NEXT:    vcmpneqpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vandpd %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-NEXT:    retq
   %f1 = fcmp une double %w, %x
   %f2 = fcmp ugt double %y, %z
@@ -118,11 +114,11 @@
 ;
 ; AVX-LABEL: ult_uge_or_f64:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vucomisd %xmm1, %xmm0
-; AVX-NEXT:    setb %cl
-; AVX-NEXT:    vucomisd %xmm2, %xmm3
-; AVX-NEXT:    setbe %al
-; AVX-NEXT:    orb %cl, %al
+; AVX-NEXT:    vcmpnltpd %xmm3, %xmm2, %xmm2
+; AVX-NEXT:    vcmpnlepd %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vorpd %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-NEXT:    retq
   %f1 = fcmp ult double %w, %x
   %f2 = fcmp uge double %y, %z
@@ -144,13 +140,11 @@
 ;
 ; AVX-LABEL: une_uno_xor_f64:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vucomisd %xmm1, %xmm0
-; AVX-NEXT:    setp %al
-; AVX-NEXT:    setne %cl
-; AVX-NEXT:    orb %al, %cl
-; AVX-NEXT:    vucomisd %xmm3, %xmm2
-; AVX-NEXT:    setp %al
-; AVX-NEXT:    xorb %cl, %al
+; AVX-NEXT:    vcmpunordpd %xmm3, %xmm2, %xmm2
+; AVX-NEXT:    vcmpneqpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vxorpd %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX-NEXT:    retq
   %f1 = fcmp une double %w, %x
   %f2 = fcmp uno double %y, %z
@@ -158,6 +152,8 @@
   ret i1 %r
 }
 
+; This uses ucomis because the types do not match.
+
 define i1 @olt_olt_and_f32_f64(float %w, float %x, double %y, double %z) {
 ; SSE-LABEL: olt_olt_and_f32_f64:
 ; SSE:       # %bb.0:
@@ -182,6 +178,8 @@
   ret i1 %r
 }
 
+; This uses ucomis because of extra uses.
+
 define i1 @une_uno_xor_f64_use1(double %w, double %x, double %y, double %z, i1* %p) {
 ; SSE-LABEL: une_uno_xor_f64_use1:
 ; SSE:       # %bb.0:
@@ -213,6 +211,8 @@
   ret i1 %r
 }
 
+; This uses ucomis because of extra uses.
+
 define i1 @une_uno_xor_f64_use2(double %w, double %x, double %y, double %z, i1* %p) {
 ; SSE-LABEL: une_uno_xor_f64_use2:
 ; SSE:       # %bb.0:
Index: llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll
===================================================================
--- llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll
+++ llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll
@@ -322,12 +322,11 @@
 ; ALL-LABEL: test_zext_cmp11:
 ; ALL:       # %bb.0: # %entry
 ; ALL-NEXT:    vxorpd %xmm2, %xmm2, %xmm2
-; ALL-NEXT:    vucomisd %xmm2, %xmm0
-; ALL-NEXT:    sete %al
-; ALL-NEXT:    vucomisd %xmm2, %xmm1
-; ALL-NEXT:    sete %cl
-; ALL-NEXT:    orb %al, %cl
-; ALL-NEXT:    movzbl %cl, %eax
+; ALL-NEXT:    vcmpeqpd %xmm2, %xmm1, %xmm1
+; ALL-NEXT:    vcmpeqpd %xmm2, %xmm0, %xmm0
+; ALL-NEXT:    vorpd %xmm1, %xmm0, %xmm0
+; ALL-NEXT:    vmovd %xmm0, %eax
+; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
 entry:
   %cmp = fcmp fast oeq double %a, 0.000000e+00