diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -625,6 +625,12 @@ /// gen prepare. virtual bool preferZeroCompareBranch() const { return false; } + /// Flip comparison conditions to optimize for fallthroughs. + /// It is recommended to disable this as it hurts canonicalization; instead + /// implement TargetInstrInfo::analyzeBranch so branches get optimized after + /// instruction selection. + virtual bool optimizeFallthroughsEarly() const { return false; } + /// Return true if it is safe to transform an integer-domain bitwise operation /// into the equivalent floating-point operation. This should be set to true /// if the target has IEEE-754-compliant fabs/fneg operations for the input diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2512,7 +2512,7 @@ // If the lhs block is the next block, invert the condition so that we can // fall through to the lhs instead of the rhs block. - if (CB.TrueBB == NextBlock(SwitchBB)) { + if (TLI.optimizeFallthroughsEarly() && CB.TrueBB == NextBlock(SwitchBB)) { std::swap(CB.TrueBB, CB.FalseBB); SDValue True = DAG.getConstant(1, dl, Cond.getValueType()); Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -768,6 +768,12 @@ bool preferIncOfAddToSubOfNot(EVT VT) const override; + bool optimizeFallthroughsEarly() const override { + // Enabled because AArch64ConditionOptimizer does not consistently optimize + // lit tests. + return true; + } + bool hasBitPreservingFPLogic(EVT VT) const override { // FIXME: Is this always true? It should be true for vectors at least. return VT == MVT::f32 || VT == MVT::f64; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -188,6 +188,7 @@ bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override; bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCtlz() const override; + bool optimizeFallthroughsEarly() const override; bool isSDNodeAlwaysUniform(const SDNode *N) const override; static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -836,6 +836,8 @@ return true; } +bool AMDGPUTargetLowering::optimizeFallthroughsEarly() const { return true; } + bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const { switch (N->getOpcode()) { case ISD::EntryToken: diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -591,8 +591,13 @@ bool preferZeroCompareBranch() const override { return true; } - bool - isShuffleMaskLegal(ArrayRef M, EVT VT) const override; + bool optimizeFallthroughsEarly() const override { + // IfConversion pass only recognizes patterns when fallthroughs are used + // so we currently cannot disable this. + return true; + } + + bool isShuffleMaskLegal(ArrayRef M, EVT VT) const override; bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; /// isFPImmLegal - Returns true if the target can instruction select the diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h --- a/llvm/lib/Target/AVR/AVRISelLowering.h +++ b/llvm/lib/Target/AVR/AVRISelLowering.h @@ -141,6 +141,8 @@ return false; } + bool optimizeFallthroughsEarly() const override { return true; } + private: SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc, SelectionDAG &DAG, SDLoc dl) const; diff --git a/llvm/lib/Target/BPF/BPFISelLowering.h b/llvm/lib/Target/BPF/BPFISelLowering.h --- a/llvm/lib/Target/BPF/BPFISelLowering.h +++ b/llvm/lib/Target/BPF/BPFISelLowering.h @@ -66,6 +66,8 @@ MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; + bool optimizeFallthroughsEarly() const override; + private: // Control Instruction Selection Features bool HasAlu32; diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -859,3 +859,9 @@ EVT VT) const { return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64; } + +bool BPFTargetLowering::optimizeFallthroughsEarly() const { + // Cannot disable this until BPFInstrInfo::analyzeBranch can optimize + // fallthroughs. + return true; +} diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -135,6 +135,7 @@ bool isCheapToSpeculateCttz() const override { return true; } bool isCheapToSpeculateCtlz() const override { return true; } bool isCtlzFast() const override { return true; } + bool optimizeFallthroughsEarly() const override { return true; } bool hasBitTest(SDValue X, SDValue Y) const override; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h --- a/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/llvm/lib/Target/Mips/MipsISelLowering.h @@ -282,6 +282,7 @@ bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCtlz() const override; + bool optimizeFallthroughsEarly() const override; bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -1191,6 +1191,8 @@ return Subtarget.hasMips32(); } +bool MipsTargetLowering::optimizeFallthroughsEarly() const { return true; } + bool MipsTargetLowering::shouldFoldConstantShiftPairToMask( const SDNode *N, CombineLevel Level) const { if (N->getOperand(0).getValueType().isVector()) diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h @@ -551,6 +551,8 @@ // instruction, so we say that ctlz is cheap to speculate. bool isCheapToSpeculateCtlz() const override { return true; } + bool optimizeFallthroughsEarly() const override { return true; } + private: const NVPTXSubtarget &STI; // cache the subtarget here SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -779,6 +779,10 @@ return false; } + bool optimizeFallthroughsEarly() const override { + return true; + } + bool hasAndNotCompare(SDValue) const override { return true; } diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h --- a/llvm/lib/Target/Sparc/SparcISelLowering.h +++ b/llvm/lib/Target/Sparc/SparcISelLowering.h @@ -58,6 +58,8 @@ bool useSoftFloat() const override; + bool optimizeFallthroughsEarly() const override; + /// computeKnownBitsForTargetNode - Determine which of the bits specified /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1826,6 +1826,8 @@ return Subtarget->useSoftFloat(); } +bool SparcTargetLowering::optimizeFallthroughsEarly() const { return true; } + const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { switch ((SPISD::NodeType)Opcode) { case SPISD::FIRST_NUMBER: break; diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h @@ -433,6 +433,7 @@ } bool isCheapToSpeculateCtlz() const override { return true; } bool preferZeroCompareBranch() const override { return true; } + bool optimizeFallthroughsEarly() const override { return true; } bool hasBitPreservingFPLogic(EVT VT) const override { EVT ScVT = VT.getScalarType(); return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h @@ -94,6 +94,7 @@ StringRef Constraint, MVT VT) const override; bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCtlz() const override; + bool optimizeFallthroughsEarly() const override; bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I = nullptr) const override; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -721,6 +721,12 @@ return true; } +bool WebAssemblyTargetLowering::optimizeFallthroughsEarly() const { + // Cannot disable this until WebAssemblyInstrInfo::analyzeBranch can optimize + // fallthroughs. + return true; +} + bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, diff --git a/llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll b/llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll --- a/llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll +++ b/llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll @@ -154,8 +154,8 @@ ; CHECK-NEXT: or %r3, lo(t), %r3 ; CHECK-NEXT: ld 0[%r3], %r3 ; CHECK-NEXT: sub %r3, 0x11, %r3 -; CHECK-NEXT: sub.f %r3, 0x1, %r0 -; CHECK-NEXT: blt .LBB6_2 +; CHECK-NEXT: sub.f %r3, 0x0, %r0 +; CHECK-NEXT: ble .LBB6_2 ; CHECK-NEXT: sub %sp, 0x10, %sp ; CHECK-NEXT: .LBB6_1: ! %if.then ; CHECK-NEXT: add %pc, 0x10, %rca diff --git a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll --- a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll +++ b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll @@ -60,9 +60,9 @@ ; RV32I-SMALL-NEXT: addi sp, sp, -16 ; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0) ; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0) -; RV32I-SMALL-NEXT: addi a2, zero, 101 +; RV32I-SMALL-NEXT: addi a2, zero, 100 ; RV32I-SMALL-NEXT: sw a1, 8(sp) -; RV32I-SMALL-NEXT: blt a0, a2, .LBB2_3 +; RV32I-SMALL-NEXT: bge a2, a0, .LBB2_3 ; RV32I-SMALL-NEXT: # %bb.1: # %if.then ; RV32I-SMALL-NEXT: lw a0, 8(sp) ; RV32I-SMALL-NEXT: jr a0 @@ -83,9 +83,9 @@ ; RV32I-MEDIUM-NEXT: # Label of block must be emitted ; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0) ; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_4) -; RV32I-MEDIUM-NEXT: addi a2, zero, 101 +; RV32I-MEDIUM-NEXT: addi a2, zero, 100 ; RV32I-MEDIUM-NEXT: sw a1, 8(sp) -; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3 +; RV32I-MEDIUM-NEXT: bge a2, a0, .LBB2_3 ; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then ; RV32I-MEDIUM-NEXT: lw a0, 8(sp) ; RV32I-MEDIUM-NEXT: jr a0 diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll --- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll @@ -10,8 +10,7 @@ define void @br_fcmp_false(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_false: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: addi a0, zero, 1 -; RV32IFD-NEXT: bnez a0, .LBB0_2 +; RV32IFD-NEXT: beqz zero, .LBB0_2 ; RV32IFD-NEXT: # %bb.1: # %if.then ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB0_2: # %if.else @@ -21,8 +20,7 @@ ; ; RV64IFD-LABEL: br_fcmp_false: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: addi a0, zero, 1 -; RV64IFD-NEXT: bnez a0, .LBB0_2 +; RV64IFD-NEXT: beqz zero, .LBB0_2 ; RV64IFD-NEXT: # %bb.1: # %if.then ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB0_2: # %if.else diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -19,7 +19,7 @@ ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: mv a0, zero -; RV32IFD-NEXT: call test +; RV32IFD-NEXT: call test@plt ; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: fld ft0, 0(sp) @@ -28,11 +28,9 @@ ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0) ; RV32IFD-NEXT: flt.d a0, ft0, ft1 -; RV32IFD-NEXT: not a0, a0 ; RV32IFD-NEXT: flt.d a1, ft2, ft0 -; RV32IFD-NEXT: xori a1, a1, 1 -; RV32IFD-NEXT: and a0, a0, a1 -; RV32IFD-NEXT: bnez a0, .LBB1_2 +; RV32IFD-NEXT: or a0, a0, a1 +; RV32IFD-NEXT: beqz a0, .LBB1_2 ; RV32IFD-NEXT: # %bb.1: # %if.then ; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: .LBB1_2: # %if.end diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll @@ -11,8 +11,7 @@ define void @br_fcmp_false(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_false: ; RV32IF: # %bb.0: -; RV32IF-NEXT: addi a0, zero, 1 -; RV32IF-NEXT: bnez a0, .LBB0_2 +; RV32IF-NEXT: beqz zero, .LBB0_2 ; RV32IF-NEXT: # %bb.1: # %if.then ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB0_2: # %if.else @@ -22,8 +21,7 @@ ; ; RV64IF-LABEL: br_fcmp_false: ; RV64IF: # %bb.0: -; RV64IF-NEXT: addi a0, zero, 1 -; RV64IF-NEXT: bnez a0, .LBB0_2 +; RV64IF-NEXT: beqz zero, .LBB0_2 ; RV64IF-NEXT: # %bb.1: # %if.then ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB0_2: # %if.else diff --git a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll --- a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll @@ -11,8 +11,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_false: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi a0, zero, 1 -; RV32IZFH-NEXT: bnez a0, .LBB0_2 +; RV32IZFH-NEXT: beqz zero, .LBB0_2 ; RV32IZFH-NEXT: # %bb.1: # %if.then ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB0_2: # %if.else @@ -22,8 +21,7 @@ ; ; RV64IZFH-LABEL: br_fcmp_false: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: addi a0, zero, 1 -; RV64IZFH-NEXT: bnez a0, .LBB0_2 +; RV64IZFH-NEXT: beqz zero, .LBB0_2 ; RV64IZFH-NEXT: # %bb.1: # %if.then ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB0_2: # %if.else diff --git a/llvm/test/CodeGen/RISCV/jumptable.ll b/llvm/test/CodeGen/RISCV/jumptable.ll --- a/llvm/test/CodeGen/RISCV/jumptable.ll +++ b/llvm/test/CodeGen/RISCV/jumptable.ll @@ -11,8 +11,8 @@ define void @below_threshold(i32 %in, i32* %out) nounwind { ; RV32I-SMALL-LABEL: below_threshold: ; RV32I-SMALL: # %bb.0: # %entry -; RV32I-SMALL-NEXT: addi a2, zero, 2 -; RV32I-SMALL-NEXT: blt a2, a0, .LBB0_4 +; RV32I-SMALL-NEXT: addi a2, zero, 3 +; RV32I-SMALL-NEXT: bge a0, a2, .LBB0_4 ; RV32I-SMALL-NEXT: # %bb.1: # %entry ; RV32I-SMALL-NEXT: addi a2, zero, 1 ; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_7 @@ -23,7 +23,6 @@ ; RV32I-SMALL-NEXT: addi a0, zero, 3 ; RV32I-SMALL-NEXT: j .LBB0_9 ; RV32I-SMALL-NEXT: .LBB0_4: # %entry -; RV32I-SMALL-NEXT: addi a2, zero, 3 ; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_8 ; RV32I-SMALL-NEXT: # %bb.5: # %entry ; RV32I-SMALL-NEXT: addi a2, zero, 4 @@ -43,8 +42,8 @@ ; ; RV32I-MEDIUM-LABEL: below_threshold: ; RV32I-MEDIUM: # %bb.0: # %entry -; RV32I-MEDIUM-NEXT: addi a2, zero, 2 -; RV32I-MEDIUM-NEXT: blt a2, a0, .LBB0_4 +; RV32I-MEDIUM-NEXT: addi a2, zero, 3 +; RV32I-MEDIUM-NEXT: bge a0, a2, .LBB0_4 ; RV32I-MEDIUM-NEXT: # %bb.1: # %entry ; RV32I-MEDIUM-NEXT: addi a2, zero, 1 ; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_7 @@ -55,7 +54,6 @@ ; RV32I-MEDIUM-NEXT: addi a0, zero, 3 ; RV32I-MEDIUM-NEXT: j .LBB0_9 ; RV32I-MEDIUM-NEXT: .LBB0_4: # %entry -; RV32I-MEDIUM-NEXT: addi a2, zero, 3 ; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_8 ; RV32I-MEDIUM-NEXT: # %bb.5: # %entry ; RV32I-MEDIUM-NEXT: addi a2, zero, 4 @@ -76,8 +74,8 @@ ; RV64I-SMALL-LABEL: below_threshold: ; RV64I-SMALL: # %bb.0: # %entry ; RV64I-SMALL-NEXT: sext.w a0, a0 -; RV64I-SMALL-NEXT: addi a2, zero, 2 -; RV64I-SMALL-NEXT: blt a2, a0, .LBB0_4 +; RV64I-SMALL-NEXT: addi a2, zero, 3 +; RV64I-SMALL-NEXT: bge a0, a2, .LBB0_4 ; RV64I-SMALL-NEXT: # %bb.1: # %entry ; RV64I-SMALL-NEXT: addi a2, zero, 1 ; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_7 @@ -88,7 +86,6 @@ ; RV64I-SMALL-NEXT: addi a0, zero, 3 ; RV64I-SMALL-NEXT: j .LBB0_9 ; RV64I-SMALL-NEXT: .LBB0_4: # %entry -; RV64I-SMALL-NEXT: addi a2, zero, 3 ; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_8 ; RV64I-SMALL-NEXT: # %bb.5: # %entry ; RV64I-SMALL-NEXT: addi a2, zero, 4 @@ -109,8 +106,8 @@ ; RV64I-MEDIUM-LABEL: below_threshold: ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: sext.w a0, a0 -; RV64I-MEDIUM-NEXT: addi a2, zero, 2 -; RV64I-MEDIUM-NEXT: blt a2, a0, .LBB0_4 +; RV64I-MEDIUM-NEXT: addi a2, zero, 3 +; RV64I-MEDIUM-NEXT: bge a0, a2, .LBB0_4 ; RV64I-MEDIUM-NEXT: # %bb.1: # %entry ; RV64I-MEDIUM-NEXT: addi a2, zero, 1 ; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_7 @@ -121,7 +118,6 @@ ; RV64I-MEDIUM-NEXT: addi a0, zero, 3 ; RV64I-MEDIUM-NEXT: j .LBB0_9 ; RV64I-MEDIUM-NEXT: .LBB0_4: # %entry -; RV64I-MEDIUM-NEXT: addi a2, zero, 3 ; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_8 ; RV64I-MEDIUM-NEXT: # %bb.5: # %entry ; RV64I-MEDIUM-NEXT: addi a2, zero, 4 diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap.ll b/llvm/test/CodeGen/RISCV/shrinkwrap.ll --- a/llvm/test/CodeGen/RISCV/shrinkwrap.ll +++ b/llvm/test/CodeGen/RISCV/shrinkwrap.ll @@ -15,8 +15,8 @@ ; RV32I-SW-NO: # %bb.0: ; RV32I-SW-NO-NEXT: addi sp, sp, -16 ; RV32I-SW-NO-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-SW-NO-NEXT: addi a1, zero, 32 -; RV32I-SW-NO-NEXT: bgeu a1, a0, .LBB0_2 +; RV32I-SW-NO-NEXT: addi a1, zero, 33 +; RV32I-SW-NO-NEXT: bltu a0, a1, .LBB0_2 ; RV32I-SW-NO-NEXT: # %bb.1: # %if.end ; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-SW-NO-NEXT: addi sp, sp, 16 @@ -26,8 +26,8 @@ ; ; RV32I-SW-LABEL: eliminate_restore: ; RV32I-SW: # %bb.0: -; RV32I-SW-NEXT: addi a1, zero, 32 -; RV32I-SW-NEXT: bgeu a1, a0, .LBB0_2 +; RV32I-SW-NEXT: addi a1, zero, 33 +; RV32I-SW-NEXT: bltu a0, a1, .LBB0_2 ; RV32I-SW-NEXT: # %bb.1: # %if.end ; RV32I-SW-NEXT: ret ; RV32I-SW-NEXT: .LBB0_2: # %if.then @@ -37,8 +37,8 @@ ; ; RV32I-SW-SR-LABEL: eliminate_restore: ; RV32I-SW-SR: # %bb.0: -; RV32I-SW-SR-NEXT: addi a1, zero, 32 -; RV32I-SW-SR-NEXT: bgeu a1, a0, .LBB0_2 +; RV32I-SW-SR-NEXT: addi a1, zero, 33 +; RV32I-SW-SR-NEXT: bltu a0, a1, .LBB0_2 ; RV32I-SW-SR-NEXT: # %bb.1: # %if.end ; RV32I-SW-SR-NEXT: ret ; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then @@ -48,8 +48,8 @@ ; RV64I-SW-LABEL: eliminate_restore: ; RV64I-SW: # %bb.0: ; RV64I-SW-NEXT: sext.w a0, a0 -; RV64I-SW-NEXT: addi a1, zero, 32 -; RV64I-SW-NEXT: bgeu a1, a0, .LBB0_2 +; RV64I-SW-NEXT: addi a1, zero, 33 +; RV64I-SW-NEXT: bltu a0, a1, .LBB0_2 ; RV64I-SW-NEXT: # %bb.1: # %if.end ; RV64I-SW-NEXT: ret ; RV64I-SW-NEXT: .LBB0_2: # %if.then @@ -76,8 +76,8 @@ ; RV32I-SW-NO-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-SW-NO-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-SW-NO-NEXT: addi s0, sp, 16 -; RV32I-SW-NO-NEXT: addi a1, zero, 32 -; RV32I-SW-NO-NEXT: bltu a1, a0, .LBB1_2 +; RV32I-SW-NO-NEXT: addi a1, zero, 33 +; RV32I-SW-NO-NEXT: bgeu a0, a1, .LBB1_2 ; RV32I-SW-NO-NEXT: # %bb.1: # %if.then ; RV32I-SW-NO-NEXT: addi a0, a0, 15 ; RV32I-SW-NO-NEXT: andi a0, a0, -16 @@ -93,8 +93,8 @@ ; ; RV32I-SW-LABEL: conditional_alloca: ; RV32I-SW: # %bb.0: -; RV32I-SW-NEXT: addi a1, zero, 32 -; RV32I-SW-NEXT: bltu a1, a0, .LBB1_2 +; RV32I-SW-NEXT: addi a1, zero, 33 +; RV32I-SW-NEXT: bgeu a0, a1, .LBB1_2 ; RV32I-SW-NEXT: # %bb.1: # %if.then ; RV32I-SW-NEXT: addi sp, sp, -16 ; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill @@ -114,8 +114,8 @@ ; ; RV32I-SW-SR-LABEL: conditional_alloca: ; RV32I-SW-SR: # %bb.0: -; RV32I-SW-SR-NEXT: addi a1, zero, 32 -; RV32I-SW-SR-NEXT: bltu a1, a0, .LBB1_2 +; RV32I-SW-SR-NEXT: addi a1, zero, 33 +; RV32I-SW-SR-NEXT: bgeu a0, a1, .LBB1_2 ; RV32I-SW-SR-NEXT: # %bb.1: # %if.then ; RV32I-SW-SR-NEXT: call t0, __riscv_save_1 ; RV32I-SW-SR-NEXT: addi s0, sp, 16 @@ -132,8 +132,8 @@ ; RV64I-SW-LABEL: conditional_alloca: ; RV64I-SW: # %bb.0: ; RV64I-SW-NEXT: sext.w a1, a0 -; RV64I-SW-NEXT: addi a2, zero, 32 -; RV64I-SW-NEXT: bltu a2, a1, .LBB1_2 +; RV64I-SW-NEXT: addi a2, zero, 33 +; RV64I-SW-NEXT: bgeu a1, a2, .LBB1_2 ; RV64I-SW-NEXT: # %bb.1: # %if.then ; RV64I-SW-NEXT: addi sp, sp, -16 ; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill diff --git a/llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll b/llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll --- a/llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll +++ b/llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll @@ -11,8 +11,8 @@ ; CHECK-NEXT: .LBB0_1: # %cond_true ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: incl %eax -; CHECK-NEXT: cmpl $40, %ecx -; CHECK-NEXT: jl .LBB0_1 +; CHECK-NEXT: cmpl $39, %ecx +; CHECK-NEXT: jle .LBB0_1 ; CHECK-NEXT: # %bb.2: # %bb12 ; CHECK-NEXT: retl entry: diff --git a/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll b/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll --- a/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll +++ b/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll @@ -6,8 +6,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl 0, %eax ; CHECK-NEXT: decl %eax -; CHECK-NEXT: cmpl $1, %eax -; CHECK-NEXT: ja .LBB0_2 +; CHECK-NEXT: cmpl $2, %eax +; CHECK-NEXT: jae .LBB0_2 ; CHECK-NEXT: # %bb.1: # %bb77 ; CHECK-NEXT: movb 0, %al ; CHECK-NEXT: movb 0, %al diff --git a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll --- a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll +++ b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll @@ -16,7 +16,7 @@ ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: movslq (%rdi), %rdi ; CHECK-NEXT: movslq (%rsi), %r8 -; CHECK-NEXT: movslq (%rdx), %r10 +; CHECK-NEXT: movslq (%rdx), %rax ; CHECK-NEXT: movl (%rcx), %esi ; CHECK-NEXT: movq %rsp, %rcx ; CHECK-NEXT: subl %edi, %r8d @@ -33,9 +33,9 @@ ; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: je .LBB0_13 ; CHECK-NEXT: .LBB0_14: # %b85 -; CHECK-NEXT: movb $1, %al -; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_1 +; CHECK-NEXT: xorl %edi, %edi +; CHECK-NEXT: testb %dil, %dil +; CHECK-NEXT: je .LBB0_1 ; CHECK-NEXT: # %bb.15: ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: .p2align 4, 0x90 @@ -44,13 +44,12 @@ ; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: je .LBB0_16 ; CHECK-NEXT: .LBB0_1: # %a29b -; CHECK-NEXT: cmpl %r10d, %esi +; CHECK-NEXT: cmpl %eax, %esi ; CHECK-NEXT: js .LBB0_10 ; CHECK-NEXT: # %bb.2: # %b158 ; CHECK-NEXT: movslq (%r9), %rsi ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: movb $1, %r9b ; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_9: # %b1606 @@ -87,8 +86,8 @@ ; CHECK-NEXT: je .LBB0_37 ; CHECK-NEXT: .LBB0_18: # %b188 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 -; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: testb %dil, %dil +; CHECK-NEXT: je .LBB0_4 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_19: # %a30b294 ; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 @@ -97,19 +96,19 @@ ; CHECK-NEXT: je .LBB0_19 ; CHECK-NEXT: .LBB0_4: # %a33b ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 -; CHECK-NEXT: movl %esi, %r10d -; CHECK-NEXT: orl %r8d, %r10d +; CHECK-NEXT: movl %esi, %r9d +; CHECK-NEXT: orl %r8d, %r9d ; CHECK-NEXT: jns .LBB0_20 ; CHECK-NEXT: .LBB0_5: # %a50b ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 -; CHECK-NEXT: shrl $31, %r10d +; CHECK-NEXT: shrl $31, %r9d ; CHECK-NEXT: movl %r8d, %eax ; CHECK-NEXT: orl %esi, %eax ; CHECK-NEXT: jns .LBB0_26 ; CHECK-NEXT: .LBB0_6: # %a57b ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: shrl $31, %eax -; CHECK-NEXT: testb %r10b, %r10b +; CHECK-NEXT: testb %r9b, %r9b ; CHECK-NEXT: je .LBB0_30 ; CHECK-NEXT: .LBB0_7: # %a66b ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 @@ -183,8 +182,8 @@ ; CHECK-NEXT: je .LBB0_38 ; CHECK-NEXT: .LBB0_27: # %b879 ; CHECK-NEXT: # in Loop: Header=BB0_26 Depth=2 -; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: jne .LBB0_28 +; CHECK-NEXT: testb %dil, %dil +; CHECK-NEXT: je .LBB0_28 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_29: # %a53b1019 ; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 diff --git a/llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll b/llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll --- a/llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll +++ b/llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll @@ -4,7 +4,7 @@ define void @test() nounwind { ; CHECK-LABEL: test: ; CHECK: ## %bb.0: ## %test.exit -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: ud2 test.exit: diff --git a/llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll b/llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll --- a/llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll +++ b/llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll @@ -22,7 +22,7 @@ ; CHECK-NEXT: orl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: # %bb.2: # %entry -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: .LBB0_3: # %bb5507 ; CHECK-NEXT: movl %ebp, %esp diff --git a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll --- a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll +++ b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll @@ -23,11 +23,13 @@ ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebx ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebp ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: movw $-2, %si -; CHECK-NEXT: jne LBB0_6 +; CHECK-NEXT: je LBB0_6 ; CHECK-NEXT: ## %bb.4: ## %bb37 ; CHECK-NEXT: movw $0, 40(%edi) -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: leal (,%ecx,4), %ecx ; CHECK-NEXT: leal (,%ebx,4), %edx diff --git a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll --- a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll +++ b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll @@ -75,12 +75,10 @@ ; CHECK-NEXT: jmpl *LJTI0_0(,%eax,4) ; CHECK-NEXT: LBB0_10: ## %bb5809 ; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_25 +; CHECK-NEXT: testb %bh, %bh +; CHECK-NEXT: je LBB0_25 ; CHECK-NEXT: ## %bb.11: ## %bb5809 ; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 -; CHECK-NEXT: testb %bh, %bh ; CHECK-NEXT: je LBB0_25 ; CHECK-NEXT: ## %bb.12: ## %bb91.i8504 ; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 diff --git a/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll --- a/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll +++ b/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll @@ -92,8 +92,8 @@ ; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: .LBB0_3: # %bb502 ; CHECK-NEXT: testb $1, %cl -; CHECK-NEXT: je .LBB0_5 -; CHECK-NEXT: jmp .LBB0_4 +; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: jmp .LBB0_5 ; CHECK-NEXT: .LBB0_4: # %bb507 ; CHECK-NEXT: movl $0, (%esi) ; CHECK-NEXT: jmp .LBB0_5 diff --git a/llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll b/llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll --- a/llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll +++ b/llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s | FileCheck %s ; Check that an overly large immediate created by SROA doesn't crash the ; legalizer. @@ -11,6 +12,52 @@ @a = common global %struct._GtkSheetRow* null, align 8 define void @fn1() nounwind uwtable ssp { +; CHECK-LABEL: fn1: +; CHECK: ## %bb.0: ## %entry +; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset %rbx, -16 +; CHECK-NEXT: movq _a@GOTPCREL(%rip), %rax +; CHECK-NEXT: movq (%rax), %rax +; CHECK-NEXT: movq 64(%rax), %rcx +; CHECK-NEXT: xorl %edx, %edx +; CHECK-NEXT: movl $4294967295, %esi ## imm = 0xFFFFFFFF +; CHECK-NEXT: cmpq %rcx, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: sbbq %rsi, %rsi +; CHECK-NEXT: sbbq %rdx, %rdx +; CHECK-NEXT: jae LBB0_2 +; CHECK-NEXT: ## %bb.1: ## %if.then +; CHECK-NEXT: movq 56(%rax), %r8 +; CHECK-NEXT: movq 48(%rax), %r9 +; CHECK-NEXT: movq 40(%rax), %r10 +; CHECK-NEXT: movq 32(%rax), %r11 +; CHECK-NEXT: movq 24(%rax), %rsi +; CHECK-NEXT: movq 16(%rax), %rdi +; CHECK-NEXT: movq (%rax), %rdx +; CHECK-NEXT: movq 8(%rax), %rbx +; CHECK-NEXT: movq %rdx, (%rax) +; CHECK-NEXT: movq %rbx, 8(%rax) +; CHECK-NEXT: movq %rdi, 16(%rax) +; CHECK-NEXT: movq %rsi, 24(%rax) +; CHECK-NEXT: movq %r11, 32(%rax) +; CHECK-NEXT: movq %r10, 40(%rax) +; CHECK-NEXT: movq %r9, 48(%rax) +; CHECK-NEXT: movq %r8, 56(%rax) +; CHECK-NEXT: movq %rcx, 64(%rax) +; CHECK-NEXT: LBB0_2: ## %if.end +; CHECK-NEXT: popq %rbx +; CHECK-NEXT: retq entry: %0 = load %struct._GtkSheetRow*, %struct._GtkSheetRow** @a, align 8 %1 = bitcast %struct._GtkSheetRow* %0 to i576* @@ -25,6 +72,4 @@ if.end: ; preds = %if.then, %entry ret void -; CHECK-LABEL: fn1: -; CHECK: jb } diff --git a/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll b/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll --- a/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll +++ b/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll @@ -64,7 +64,7 @@ ; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_3 +; CHECK-NEXT: je .LBB1_3 ; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: movw $8, %ax ; CHECK-NEXT: tilezero %tmm0 @@ -126,7 +126,7 @@ ; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB2_2 +; CHECK-NEXT: je .LBB2_2 ; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: incl %edi ; CHECK-NEXT: jmp .LBB2_3 @@ -169,7 +169,7 @@ ; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB3_3 +; CHECK-NEXT: je .LBB3_3 ; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: incl %edi ; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp) @@ -252,7 +252,7 @@ ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB4_3 +; CHECK-NEXT: je .LBB4_3 ; CHECK-NEXT: # %bb.2: # %if.true ; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1 ; CHECK-NEXT: tilezero %tmm0 @@ -317,7 +317,7 @@ ; CHECK-NEXT: .LBB5_1: # %loop.bb1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %r8b, %r8b -; CHECK-NEXT: jne .LBB5_3 +; CHECK-NEXT: je .LBB5_3 ; CHECK-NEXT: # %bb.2: # %if.true ; CHECK-NEXT: # in Loop: Header=BB5_1 Depth=1 ; CHECK-NEXT: incl %esi diff --git a/llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll b/llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll --- a/llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll +++ b/llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll @@ -26,7 +26,7 @@ ; CHECK-NEXT: tileloadd (%rdi,%rax), %tmm3 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: je .LBB0_3 ; CHECK-NEXT: # %bb.1: # %loop.header.preheader ; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: xorl %ebp, %ebp @@ -110,7 +110,7 @@ ; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_3 +; CHECK-NEXT: je .LBB1_3 ; CHECK-NEXT: # %bb.1: # %loop.header.preheader ; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: xorl %ebp, %ebp diff --git a/llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll b/llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll --- a/llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll +++ b/llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll @@ -36,7 +36,7 @@ ; CHECK-NEXT: tileloadd (%r15,%r14), %tmm5 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: movl $buf, %eax ; CHECK-NEXT: movw $8, %cx @@ -135,7 +135,7 @@ ; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_3 +; CHECK-NEXT: je .LBB1_3 ; CHECK-NEXT: # %bb.1: # %loop.header.preheader ; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movl $32, %r14d diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll --- a/llvm/test/CodeGen/X86/atomic-unordered.ll +++ b/llvm/test/CodeGen/X86/atomic-unordered.ll @@ -281,8 +281,8 @@ ; CHECK-O0-NEXT: lock cmpxchg16b (%rsi) ; CHECK-O0-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; CHECK-O0-NEXT: jne .LBB16_1 -; CHECK-O0-NEXT: jmp .LBB16_2 +; CHECK-O0-NEXT: je .LBB16_2 +; CHECK-O0-NEXT: jmp .LBB16_1 ; CHECK-O0-NEXT: .LBB16_2: # %atomicrmw.end ; CHECK-O0-NEXT: popq %rbx ; CHECK-O0-NEXT: .cfi_def_cfa_offset 8 diff --git a/llvm/test/CodeGen/X86/atomic64.ll b/llvm/test/CodeGen/X86/atomic64.ll --- a/llvm/test/CodeGen/X86/atomic64.ll +++ b/llvm/test/CodeGen/X86/atomic64.ll @@ -399,8 +399,8 @@ ; I486-NEXT: testb %dl, %dl ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: je .LBB6_1 -; I486-NEXT: jmp .LBB6_2 +; I486-NEXT: jne .LBB6_2 +; I486-NEXT: jmp .LBB6_1 ; I486-NEXT: .LBB6_2: # %atomicrmw.end ; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: popl %esi @@ -492,8 +492,8 @@ ; I486-NEXT: testb %dl, %dl ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: je .LBB7_1 -; I486-NEXT: jmp .LBB7_2 +; I486-NEXT: jne .LBB7_2 +; I486-NEXT: jmp .LBB7_1 ; I486-NEXT: .LBB7_2: # %atomicrmw.end ; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: popl %esi @@ -585,8 +585,8 @@ ; I486-NEXT: testb %dl, %dl ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: je .LBB8_1 -; I486-NEXT: jmp .LBB8_2 +; I486-NEXT: jne .LBB8_2 +; I486-NEXT: jmp .LBB8_1 ; I486-NEXT: .LBB8_2: # %atomicrmw.end ; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: popl %esi @@ -678,8 +678,8 @@ ; I486-NEXT: testb %dl, %dl ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: je .LBB9_1 -; I486-NEXT: jmp .LBB9_2 +; I486-NEXT: jne .LBB9_2 +; I486-NEXT: jmp .LBB9_1 ; I486-NEXT: .LBB9_2: # %atomicrmw.end ; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: popl %esi diff --git a/llvm/test/CodeGen/X86/atomic6432.ll b/llvm/test/CodeGen/X86/atomic6432.ll --- a/llvm/test/CodeGen/X86/atomic6432.ll +++ b/llvm/test/CodeGen/X86/atomic6432.ll @@ -27,8 +27,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB0_1 -; X32-NEXT: jmp .LBB0_2 +; X32-NEXT: je .LBB0_2 +; X32-NEXT: jmp .LBB0_1 ; X32-NEXT: .LBB0_2: # %atomicrmw.end ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -48,8 +48,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB0_3 -; X32-NEXT: jmp .LBB0_4 +; X32-NEXT: je .LBB0_4 +; X32-NEXT: jmp .LBB0_3 ; X32-NEXT: .LBB0_4: # %atomicrmw.end1 ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -71,8 +71,8 @@ ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB0_5 -; X32-NEXT: jmp .LBB0_6 +; X32-NEXT: je .LBB0_6 +; X32-NEXT: jmp .LBB0_5 ; X32-NEXT: .LBB0_6: # %atomicrmw.end7 ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -94,8 +94,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB0_7 -; X32-NEXT: jmp .LBB0_8 +; X32-NEXT: je .LBB0_8 +; X32-NEXT: jmp .LBB0_7 ; X32-NEXT: .LBB0_8: # %atomicrmw.end13 ; X32-NEXT: addl $72, %esp ; X32-NEXT: popl %esi @@ -133,8 +133,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB1_1 -; X32-NEXT: jmp .LBB1_2 +; X32-NEXT: je .LBB1_2 +; X32-NEXT: jmp .LBB1_1 ; X32-NEXT: .LBB1_2: # %atomicrmw.end ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -154,8 +154,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB1_3 -; X32-NEXT: jmp .LBB1_4 +; X32-NEXT: je .LBB1_4 +; X32-NEXT: jmp .LBB1_3 ; X32-NEXT: .LBB1_4: # %atomicrmw.end1 ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -177,8 +177,8 @@ ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB1_5 -; X32-NEXT: jmp .LBB1_6 +; X32-NEXT: je .LBB1_6 +; X32-NEXT: jmp .LBB1_5 ; X32-NEXT: .LBB1_6: # %atomicrmw.end7 ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -200,8 +200,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB1_7 -; X32-NEXT: jmp .LBB1_8 +; X32-NEXT: je .LBB1_8 +; X32-NEXT: jmp .LBB1_7 ; X32-NEXT: .LBB1_8: # %atomicrmw.end13 ; X32-NEXT: addl $72, %esp ; X32-NEXT: popl %esi @@ -236,8 +236,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB2_1 -; X32-NEXT: jmp .LBB2_2 +; X32-NEXT: je .LBB2_2 +; X32-NEXT: jmp .LBB2_1 ; X32-NEXT: .LBB2_2: # %atomicrmw.end ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -259,8 +259,8 @@ ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB2_3 -; X32-NEXT: jmp .LBB2_4 +; X32-NEXT: je .LBB2_4 +; X32-NEXT: jmp .LBB2_3 ; X32-NEXT: .LBB2_4: # %atomicrmw.end1 ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -282,8 +282,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB2_5 -; X32-NEXT: jmp .LBB2_6 +; X32-NEXT: je .LBB2_6 +; X32-NEXT: jmp .LBB2_5 ; X32-NEXT: .LBB2_6: # %atomicrmw.end7 ; X32-NEXT: addl $52, %esp ; X32-NEXT: popl %esi @@ -317,8 +317,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB3_1 -; X32-NEXT: jmp .LBB3_2 +; X32-NEXT: je .LBB3_2 +; X32-NEXT: jmp .LBB3_1 ; X32-NEXT: .LBB3_2: # %atomicrmw.end ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -340,8 +340,8 @@ ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB3_3 -; X32-NEXT: jmp .LBB3_4 +; X32-NEXT: je .LBB3_4 +; X32-NEXT: jmp .LBB3_3 ; X32-NEXT: .LBB3_4: # %atomicrmw.end1 ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -363,8 +363,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB3_5 -; X32-NEXT: jmp .LBB3_6 +; X32-NEXT: je .LBB3_6 +; X32-NEXT: jmp .LBB3_5 ; X32-NEXT: .LBB3_6: # %atomicrmw.end7 ; X32-NEXT: addl $52, %esp ; X32-NEXT: popl %esi @@ -398,8 +398,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB4_1 -; X32-NEXT: jmp .LBB4_2 +; X32-NEXT: je .LBB4_2 +; X32-NEXT: jmp .LBB4_1 ; X32-NEXT: .LBB4_2: # %atomicrmw.end ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -421,8 +421,8 @@ ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB4_3 -; X32-NEXT: jmp .LBB4_4 +; X32-NEXT: je .LBB4_4 +; X32-NEXT: jmp .LBB4_3 ; X32-NEXT: .LBB4_4: # %atomicrmw.end1 ; X32-NEXT: movl sc64+4, %edx ; X32-NEXT: movl sc64, %eax @@ -444,8 +444,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB4_5 -; X32-NEXT: jmp .LBB4_6 +; X32-NEXT: je .LBB4_6 +; X32-NEXT: jmp .LBB4_5 ; X32-NEXT: .LBB4_6: # %atomicrmw.end7 ; X32-NEXT: addl $52, %esp ; X32-NEXT: popl %esi @@ -492,8 +492,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB5_1 -; X32-NEXT: jmp .LBB5_2 +; X32-NEXT: je .LBB5_2 +; X32-NEXT: jmp .LBB5_1 ; X32-NEXT: .LBB5_2: # %atomicrmw.end ; X32-NEXT: addl $32, %esp ; X32-NEXT: popl %esi @@ -538,8 +538,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB6_1 -; X32-NEXT: jmp .LBB6_2 +; X32-NEXT: je .LBB6_2 +; X32-NEXT: jmp .LBB6_1 ; X32-NEXT: .LBB6_2: # %atomicrmw.end ; X32-NEXT: addl $32, %esp ; X32-NEXT: popl %esi @@ -583,8 +583,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB7_1 -; X32-NEXT: jmp .LBB7_2 +; X32-NEXT: je .LBB7_2 +; X32-NEXT: jmp .LBB7_1 ; X32-NEXT: .LBB7_2: # %atomicrmw.end ; X32-NEXT: addl $32, %esp ; X32-NEXT: popl %esi @@ -628,8 +628,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB8_1 -; X32-NEXT: jmp .LBB8_2 +; X32-NEXT: je .LBB8_2 +; X32-NEXT: jmp .LBB8_1 ; X32-NEXT: .LBB8_2: # %atomicrmw.end ; X32-NEXT: addl $32, %esp ; X32-NEXT: popl %esi @@ -673,8 +673,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB9_1 -; X32-NEXT: jmp .LBB9_2 +; X32-NEXT: je .LBB9_2 +; X32-NEXT: jmp .LBB9_1 ; X32-NEXT: .LBB9_2: # %atomicrmw.end ; X32-NEXT: addl $32, %esp ; X32-NEXT: popl %esi @@ -735,8 +735,8 @@ ; X32-NEXT: lock cmpxchg8b sc64 ; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X32-NEXT: jne .LBB12_1 -; X32-NEXT: jmp .LBB12_2 +; X32-NEXT: je .LBB12_2 +; X32-NEXT: jmp .LBB12_1 ; X32-NEXT: .LBB12_2: # %atomicrmw.end ; X32-NEXT: addl $16, %esp ; X32-NEXT: popl %ebx diff --git a/llvm/test/CodeGen/X86/avoid-sfb.ll b/llvm/test/CodeGen/X86/avoid-sfb.ll --- a/llvm/test/CodeGen/X86/avoid-sfb.ll +++ b/llvm/test/CodeGen/X86/avoid-sfb.ll @@ -13,8 +13,8 @@ define void @test_conditional_block(%struct.S* nocapture noalias %s1 , %struct.S* nocapture noalias %s2, i32 %x, %struct.S* nocapture noalias %s3, %struct.S* nocapture noalias readonly %s4) local_unnamed_addr #0 { ; CHECK-LABEL: test_conditional_block: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB0_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB0_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl %edx, 4(%rdi) ; CHECK-NEXT: .LBB0_2: # %if.end @@ -30,8 +30,8 @@ ; ; DISABLED-LABEL: test_conditional_block: ; DISABLED: # %bb.0: # %entry -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB0_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB0_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movl %edx, 4(%rdi) ; DISABLED-NEXT: .LBB0_2: # %if.end @@ -43,8 +43,8 @@ ; ; CHECK-AVX2-LABEL: test_conditional_block: ; CHECK-AVX2: # %bb.0: # %entry -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB0_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB0_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX2-NEXT: .LBB0_2: # %if.end @@ -60,8 +60,8 @@ ; ; CHECK-AVX512-LABEL: test_conditional_block: ; CHECK-AVX512: # %bb.0: # %entry -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB0_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB0_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX512-NEXT: .LBB0_2: # %if.end @@ -153,13 +153,13 @@ define void @test_nondirect_br(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 { ; CHECK-LABEL: test_nondirect_br: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB2_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB2_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl %edx, 4(%rdi) ; CHECK-NEXT: .LBB2_2: # %if.end -; CHECK-NEXT: cmpl $14, %r9d -; CHECK-NEXT: jl .LBB2_4 +; CHECK-NEXT: cmpl $13, %r9d +; CHECK-NEXT: jle .LBB2_4 ; CHECK-NEXT: # %bb.3: # %if.then2 ; CHECK-NEXT: movl %r9d, 12(%rdi) ; CHECK-NEXT: .LBB2_4: # %if.end3 @@ -175,13 +175,13 @@ ; ; DISABLED-LABEL: test_nondirect_br: ; DISABLED: # %bb.0: # %entry -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB2_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB2_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movl %edx, 4(%rdi) ; DISABLED-NEXT: .LBB2_2: # %if.end -; DISABLED-NEXT: cmpl $14, %r9d -; DISABLED-NEXT: jl .LBB2_4 +; DISABLED-NEXT: cmpl $13, %r9d +; DISABLED-NEXT: jle .LBB2_4 ; DISABLED-NEXT: # %bb.3: # %if.then2 ; DISABLED-NEXT: movl %r9d, 12(%rdi) ; DISABLED-NEXT: .LBB2_4: # %if.end3 @@ -193,13 +193,13 @@ ; ; CHECK-AVX2-LABEL: test_nondirect_br: ; CHECK-AVX2: # %bb.0: # %entry -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB2_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB2_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX2-NEXT: .LBB2_2: # %if.end -; CHECK-AVX2-NEXT: cmpl $14, %r9d -; CHECK-AVX2-NEXT: jl .LBB2_4 +; CHECK-AVX2-NEXT: cmpl $13, %r9d +; CHECK-AVX2-NEXT: jle .LBB2_4 ; CHECK-AVX2-NEXT: # %bb.3: # %if.then2 ; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX2-NEXT: .LBB2_4: # %if.end3 @@ -215,13 +215,13 @@ ; ; CHECK-AVX512-LABEL: test_nondirect_br: ; CHECK-AVX512: # %bb.0: # %entry -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB2_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB2_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX512-NEXT: .LBB2_2: # %if.end -; CHECK-AVX512-NEXT: cmpl $14, %r9d -; CHECK-AVX512-NEXT: jl .LBB2_4 +; CHECK-AVX512-NEXT: cmpl $13, %r9d +; CHECK-AVX512-NEXT: jle .LBB2_4 ; CHECK-AVX512-NEXT: # %bb.3: # %if.then2 ; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX512-NEXT: .LBB2_4: # %if.end3 @@ -267,8 +267,8 @@ ; CHECK-LABEL: test_2preds_block: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl %r9d, 12(%rdi) -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB3_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB3_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl %edx, 4(%rdi) ; CHECK-NEXT: .LBB3_2: # %if.end @@ -287,8 +287,8 @@ ; DISABLED-LABEL: test_2preds_block: ; DISABLED: # %bb.0: # %entry ; DISABLED-NEXT: movl %r9d, 12(%rdi) -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB3_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB3_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movl %edx, 4(%rdi) ; DISABLED-NEXT: .LBB3_2: # %if.end @@ -301,8 +301,8 @@ ; CHECK-AVX2-LABEL: test_2preds_block: ; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi) -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB3_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB3_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX2-NEXT: .LBB3_2: # %if.end @@ -321,8 +321,8 @@ ; CHECK-AVX512-LABEL: test_2preds_block: ; CHECK-AVX512: # %bb.0: # %entry ; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi) -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB3_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB3_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX512-NEXT: .LBB3_2: # %if.end @@ -363,8 +363,8 @@ define void @test_type64(%struct.S2* nocapture noalias %s1, %struct.S2* nocapture %s2, i32 %x, %struct.S2* nocapture %s3, %struct.S2* nocapture readonly %s4) local_unnamed_addr #0 { ; CHECK-LABEL: test_type64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB4_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB4_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movslq %edx, %rax ; CHECK-NEXT: movq %rax, 8(%rdi) @@ -379,8 +379,8 @@ ; ; DISABLED-LABEL: test_type64: ; DISABLED: # %bb.0: # %entry -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB4_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB4_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movslq %edx, %rax ; DISABLED-NEXT: movq %rax, 8(%rdi) @@ -393,8 +393,8 @@ ; ; CHECK-AVX2-LABEL: test_type64: ; CHECK-AVX2: # %bb.0: # %entry -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB4_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB4_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movslq %edx, %rax ; CHECK-AVX2-NEXT: movq %rax, 8(%rdi) @@ -409,8 +409,8 @@ ; ; CHECK-AVX512-LABEL: test_type64: ; CHECK-AVX512: # %bb.0: # %entry -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB4_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB4_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movslq %edx, %rax ; CHECK-AVX512-NEXT: movq %rax, 8(%rdi) @@ -447,8 +447,8 @@ define void @test_mixed_type(%struct.S3* nocapture noalias %s1, %struct.S3* nocapture %s2, i32 %x, %struct.S3* nocapture readnone %s3, %struct.S3* nocapture readnone %s4) local_unnamed_addr #0 { ; CHECK-LABEL: test_mixed_type: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB5_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB5_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movslq %edx, %rax ; CHECK-NEXT: movq %rax, (%rdi) @@ -468,8 +468,8 @@ ; ; DISABLED-LABEL: test_mixed_type: ; DISABLED: # %bb.0: # %entry -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB5_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB5_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movslq %edx, %rax ; DISABLED-NEXT: movq %rax, (%rdi) @@ -481,8 +481,8 @@ ; ; CHECK-AVX2-LABEL: test_mixed_type: ; CHECK-AVX2: # %bb.0: # %entry -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB5_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB5_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movslq %edx, %rax ; CHECK-AVX2-NEXT: movq %rax, (%rdi) @@ -502,8 +502,8 @@ ; ; CHECK-AVX512-LABEL: test_mixed_type: ; CHECK-AVX512: # %bb.0: # %entry -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB5_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB5_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movslq %edx, %rax ; CHECK-AVX512-NEXT: movq %rax, (%rdi) @@ -634,8 +634,8 @@ define void @test_type16(%struct.S5* nocapture noalias %s1, %struct.S5* nocapture %s2, i32 %x, %struct.S5* nocapture %s3, %struct.S5* nocapture readonly %s4) local_unnamed_addr #0 { ; CHECK-LABEL: test_type16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB7_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB7_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movw %dx, 2(%rdi) ; CHECK-NEXT: .LBB7_2: # %if.end @@ -653,8 +653,8 @@ ; ; DISABLED-LABEL: test_type16: ; DISABLED: # %bb.0: # %entry -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB7_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB7_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movw %dx, 2(%rdi) ; DISABLED-NEXT: .LBB7_2: # %if.end @@ -666,8 +666,8 @@ ; ; CHECK-AVX2-LABEL: test_type16: ; CHECK-AVX2: # %bb.0: # %entry -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB7_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB7_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movw %dx, 2(%rdi) ; CHECK-AVX2-NEXT: .LBB7_2: # %if.end @@ -685,8 +685,8 @@ ; ; CHECK-AVX512-LABEL: test_type16: ; CHECK-AVX512: # %bb.0: # %entry -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB7_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB7_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movw %dx, 2(%rdi) ; CHECK-AVX512-NEXT: .LBB7_2: # %if.end @@ -842,8 +842,8 @@ ; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movl %r9d, 12(%rdi) ; CHECK-NEXT: callq bar@PLT -; CHECK-NEXT: cmpl $18, %ebp -; CHECK-NEXT: jl .LBB9_2 +; CHECK-NEXT: cmpl $17, %ebp +; CHECK-NEXT: jle .LBB9_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl %ebp, 4(%rbx) ; CHECK-NEXT: movq %rbx, %rdi @@ -889,8 +889,8 @@ ; DISABLED-NEXT: movq %rdi, %rbx ; DISABLED-NEXT: movl %r9d, 12(%rdi) ; DISABLED-NEXT: callq bar@PLT -; DISABLED-NEXT: cmpl $18, %ebp -; DISABLED-NEXT: jl .LBB9_2 +; DISABLED-NEXT: cmpl $17, %ebp +; DISABLED-NEXT: jle .LBB9_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movl %ebp, 4(%rbx) ; DISABLED-NEXT: movq %rbx, %rdi @@ -936,8 +936,8 @@ ; CHECK-AVX2-NEXT: movq %rdi, %rbx ; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX2-NEXT: callq bar@PLT -; CHECK-AVX2-NEXT: cmpl $18, %ebp -; CHECK-AVX2-NEXT: jl .LBB9_2 +; CHECK-AVX2-NEXT: cmpl $17, %ebp +; CHECK-AVX2-NEXT: jle .LBB9_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movl %ebp, 4(%rbx) ; CHECK-AVX2-NEXT: movq %rbx, %rdi @@ -983,8 +983,8 @@ ; CHECK-AVX512-NEXT: movq %rdi, %rbx ; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi) ; CHECK-AVX512-NEXT: callq bar@PLT -; CHECK-AVX512-NEXT: cmpl $18, %ebp -; CHECK-AVX512-NEXT: jl .LBB9_2 +; CHECK-AVX512-NEXT: cmpl $17, %ebp +; CHECK-AVX512-NEXT: jle .LBB9_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movl %ebp, 4(%rbx) ; CHECK-AVX512-NEXT: movq %rbx, %rdi @@ -1051,8 +1051,8 @@ ; CHECK-NEXT: movq %rsi, %r14 ; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movl %r9d, 12(%rdi) -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB10_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB10_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl %edx, 4(%rbx) ; CHECK-NEXT: movq %rbx, %rdi @@ -1099,8 +1099,8 @@ ; DISABLED-NEXT: movq %rsi, %r12 ; DISABLED-NEXT: movq %rdi, %rbx ; DISABLED-NEXT: movl %r9d, 12(%rdi) -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB10_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB10_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movl %edx, 4(%rbx) ; DISABLED-NEXT: movq %rbx, %rdi @@ -1143,8 +1143,8 @@ ; CHECK-AVX2-NEXT: movq %rsi, %r14 ; CHECK-AVX2-NEXT: movq %rdi, %rbx ; CHECK-AVX2-NEXT: movl %r9d, 12(%rdi) -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB10_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB10_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movl %edx, 4(%rbx) ; CHECK-AVX2-NEXT: movq %rbx, %rdi @@ -1191,8 +1191,8 @@ ; CHECK-AVX512-NEXT: movq %rsi, %r14 ; CHECK-AVX512-NEXT: movq %rdi, %rbx ; CHECK-AVX512-NEXT: movl %r9d, 12(%rdi) -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB10_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB10_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movl %edx, 4(%rbx) ; CHECK-AVX512-NEXT: movq %rbx, %rdi @@ -1249,8 +1249,8 @@ define void @test_conditional_block_float(%struct.S7* nocapture noalias %s1, %struct.S7* nocapture %s2, i32 %x, %struct.S7* nocapture %s3, %struct.S7* nocapture readonly %s4, float %y) local_unnamed_addr #0 { ; CHECK-LABEL: test_conditional_block_float: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB11_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB11_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; CHECK-NEXT: .LBB11_2: # %if.end @@ -1270,8 +1270,8 @@ ; ; DISABLED-LABEL: test_conditional_block_float: ; DISABLED: # %bb.0: # %entry -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB11_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB11_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; DISABLED-NEXT: .LBB11_2: # %if.end @@ -1287,8 +1287,8 @@ ; ; CHECK-AVX2-LABEL: test_conditional_block_float: ; CHECK-AVX2: # %bb.0: # %entry -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB11_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB11_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; CHECK-AVX2-NEXT: .LBB11_2: # %if.end @@ -1307,8 +1307,8 @@ ; ; CHECK-AVX512-LABEL: test_conditional_block_float: ; CHECK-AVX512: # %bb.0: # %entry -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB11_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB11_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; CHECK-AVX512-NEXT: .LBB11_2: # %if.end @@ -1349,8 +1349,8 @@ define void @test_conditional_block_ymm(%struct.S8* nocapture noalias %s1, %struct.S8* nocapture %s2, i32 %x, %struct.S8* nocapture %s3, %struct.S8* nocapture readonly %s4) local_unnamed_addr #0 { ; CHECK-LABEL: test_conditional_block_ymm: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmpl $18, %edx -; CHECK-NEXT: jl .LBB12_2 +; CHECK-NEXT: cmpl $17, %edx +; CHECK-NEXT: jle .LBB12_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movq $1, 8(%rdi) ; CHECK-NEXT: .LBB12_2: # %if.end @@ -1368,8 +1368,8 @@ ; ; DISABLED-LABEL: test_conditional_block_ymm: ; DISABLED: # %bb.0: # %entry -; DISABLED-NEXT: cmpl $18, %edx -; DISABLED-NEXT: jl .LBB12_2 +; DISABLED-NEXT: cmpl $17, %edx +; DISABLED-NEXT: jle .LBB12_2 ; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: movq $1, 8(%rdi) ; DISABLED-NEXT: .LBB12_2: # %if.end @@ -1385,8 +1385,8 @@ ; ; CHECK-AVX2-LABEL: test_conditional_block_ymm: ; CHECK-AVX2: # %bb.0: # %entry -; CHECK-AVX2-NEXT: cmpl $18, %edx -; CHECK-AVX2-NEXT: jl .LBB12_2 +; CHECK-AVX2-NEXT: cmpl $17, %edx +; CHECK-AVX2-NEXT: jle .LBB12_2 ; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: movq $1, 8(%rdi) ; CHECK-AVX2-NEXT: .LBB12_2: # %if.end @@ -1403,8 +1403,8 @@ ; ; CHECK-AVX512-LABEL: test_conditional_block_ymm: ; CHECK-AVX512: # %bb.0: # %entry -; CHECK-AVX512-NEXT: cmpl $18, %edx -; CHECK-AVX512-NEXT: jl .LBB12_2 +; CHECK-AVX512-NEXT: cmpl $17, %edx +; CHECK-AVX512-NEXT: jle .LBB12_2 ; CHECK-AVX512-NEXT: # %bb.1: # %if.then ; CHECK-AVX512-NEXT: movq $1, 8(%rdi) ; CHECK-AVX512-NEXT: .LBB12_2: # %if.end diff --git a/llvm/test/CodeGen/X86/avx-cmp.ll b/llvm/test/CodeGen/X86/avx-cmp.ll --- a/llvm/test/CodeGen/X86/avx-cmp.ll +++ b/llvm/test/CodeGen/X86/avx-cmp.ll @@ -26,28 +26,26 @@ define void @render(double %a0) nounwind { ; CHECK-LABEL: render: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: pushq %rbx -; CHECK-NEXT: pushq %rax -; CHECK-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill +; CHECK-NEXT: subq $16, %rsp +; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB2_6 +; CHECK-NEXT: je .LBB2_6 ; CHECK-NEXT: # %bb.1: # %for.cond5.preheader ; CHECK-NEXT: xorl %ebx, %ebx -; CHECK-NEXT: movb $1, %bpl ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB2_2: # %for.cond5 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB2_2 +; CHECK-NEXT: je .LBB2_2 ; CHECK-NEXT: # %bb.3: # %for.cond5 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 -; CHECK-NEXT: testb %bpl, %bpl -; CHECK-NEXT: jne .LBB2_2 +; CHECK-NEXT: testb %bl, %bl +; CHECK-NEXT: je .LBB2_2 ; CHECK-NEXT: # %bb.4: # %for.body33.preheader ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 -; CHECK-NEXT: vmovsd (%rsp), %xmm0 # 8-byte Reload +; CHECK-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: jne .LBB2_5 @@ -57,9 +55,8 @@ ; CHECK-NEXT: callq scale@PLT ; CHECK-NEXT: jmp .LBB2_2 ; CHECK-NEXT: .LBB2_6: # %for.end52 -; CHECK-NEXT: addq $8, %rsp +; CHECK-NEXT: addq $16, %rsp ; CHECK-NEXT: popq %rbx -; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq entry: br i1 undef, label %for.cond5, label %for.end52 diff --git a/llvm/test/CodeGen/X86/avx-load-store.ll b/llvm/test/CodeGen/X86/avx-load-store.ll --- a/llvm/test/CodeGen/X86/avx-load-store.ll +++ b/llvm/test/CodeGen/X86/avx-load-store.ll @@ -215,12 +215,12 @@ ; CHECK: # %bb.0: # %allocas ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB9_2 +; CHECK-NEXT: je .LBB9_2 ; CHECK-NEXT: # %bb.1: # %cif_mask_all ; CHECK-NEXT: .LBB9_2: # %cif_mask_mixed ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB9_4 +; CHECK-NEXT: je .LBB9_4 ; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all ; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,0,0,0] ; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax) diff --git a/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll b/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll --- a/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll +++ b/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll @@ -3786,8 +3786,8 @@ ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1} ; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,4) ; CHECK-NEXT: addq $4, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: jg .LBB108_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jge .LBB108_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: retq bb: @@ -3823,8 +3823,8 @@ ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1} ; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,4) ; CHECK-NEXT: addq $8, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: jg .LBB109_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jge .LBB109_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -3861,8 +3861,8 @@ ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1} ; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,4) ; CHECK-NEXT: addq $16, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: jg .LBB110_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jge .LBB110_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -3899,8 +3899,8 @@ ; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1} ; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8) ; CHECK-NEXT: addq $2, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: jg .LBB111_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jge .LBB111_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: retq bb: @@ -3935,8 +3935,8 @@ ; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1} ; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,8) ; CHECK-NEXT: addq $4, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: jg .LBB112_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jge .LBB112_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -3973,8 +3973,8 @@ ; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1} ; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,8) ; CHECK-NEXT: addq $8, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: jg .LBB113_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jge .LBB113_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -4011,8 +4011,8 @@ ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1} ; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,4) ; CHECK-NEXT: addq $4, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: ja .LBB114_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jae .LBB114_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: retq bb: @@ -4048,8 +4048,8 @@ ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1} ; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,4) ; CHECK-NEXT: addq $8, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: ja .LBB115_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jae .LBB115_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -4086,8 +4086,8 @@ ; CHECK-NEXT: vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1} ; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,4) ; CHECK-NEXT: addq $16, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: ja .LBB116_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jae .LBB116_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -4124,8 +4124,8 @@ ; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1} ; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8) ; CHECK-NEXT: addq $2, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: ja .LBB117_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jae .LBB117_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: retq bb: @@ -4160,8 +4160,8 @@ ; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1} ; CHECK-NEXT: vmovdqu %ymm1, (%rdi,%rax,8) ; CHECK-NEXT: addq $4, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: ja .LBB118_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jae .LBB118_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -4198,8 +4198,8 @@ ; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1} ; CHECK-NEXT: vmovdqu64 %zmm1, (%rdi,%rax,8) ; CHECK-NEXT: addq $8, %rax -; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF -; CHECK-NEXT: ja .LBB119_1 +; CHECK-NEXT: cmpq $1024, %rax # imm = 0x400 +; CHECK-NEXT: jae .LBB119_1 ; CHECK-NEXT: # %bb.2: # %bb10 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll b/llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll --- a/llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll +++ b/llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll @@ -28,7 +28,7 @@ ; CHECK-NEXT: leaq (,%rbp,8), %rax ; CHECK-NEXT: leaq global(%rax,%rax,2), %r14 ; CHECK-NEXT: leaq global+4(%rax,%rax,2), %r15 -; CHECK-NEXT: xorl %r13d, %r13d +; CHECK-NEXT: movb $1, %r13b ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_2: # %bb8 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 @@ -41,7 +41,7 @@ ; CHECK-NEXT: movq %r15, %rdi ; CHECK-NEXT: callq hoge@PLT ; CHECK-NEXT: testb %r13b, %r13b -; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: # %bb.3: # %bb15 ; CHECK-NEXT: leaq (%rbp,%rbp,2), %rax ; CHECK-NEXT: movq %rbx, global+16(,%rax,8) diff --git a/llvm/test/CodeGen/X86/cmp-bool.ll b/llvm/test/CodeGen/X86/cmp-bool.ll --- a/llvm/test/CodeGen/X86/cmp-bool.ll +++ b/llvm/test/CodeGen/X86/cmp-bool.ll @@ -25,7 +25,7 @@ define void @bool_ne(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind { ; CHECK-LABEL: bool_ne: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cmpb %sil, %dil +; CHECK-NEXT: xorl %esi, %edi ; CHECK-NEXT: je .LBB1_1 ; CHECK-NEXT: # %bb.2: # %if.then ; CHECK-NEXT: jmpq *%rdx # TAILCALL diff --git a/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll b/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll --- a/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll +++ b/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll @@ -35,14 +35,14 @@ ; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx ; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %esi ; 32-GOOD-RA-NEXT: lock cmpxchg8b (%esi) -; 32-GOOD-RA-NEXT: setne %bl +; 32-GOOD-RA-NEXT: sete %bl ; 32-GOOD-RA-NEXT: subl $8, %esp ; 32-GOOD-RA-NEXT: pushl %edx ; 32-GOOD-RA-NEXT: pushl %eax ; 32-GOOD-RA-NEXT: calll bar@PLT ; 32-GOOD-RA-NEXT: addl $16, %esp ; 32-GOOD-RA-NEXT: testb %bl, %bl -; 32-GOOD-RA-NEXT: jne .LBB0_3 +; 32-GOOD-RA-NEXT: je .LBB0_3 ; 32-GOOD-RA-NEXT: # %bb.1: # %t ; 32-GOOD-RA-NEXT: movl $42, %eax ; 32-GOOD-RA-NEXT: jmp .LBB0_2 @@ -66,14 +66,14 @@ ; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %eax ; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %edx ; 32-FAST-RA-NEXT: lock cmpxchg8b (%esi) -; 32-FAST-RA-NEXT: setne %bl +; 32-FAST-RA-NEXT: sete %bl ; 32-FAST-RA-NEXT: subl $8, %esp ; 32-FAST-RA-NEXT: pushl %edx ; 32-FAST-RA-NEXT: pushl %eax ; 32-FAST-RA-NEXT: calll bar@PLT ; 32-FAST-RA-NEXT: addl $16, %esp ; 32-FAST-RA-NEXT: testb %bl, %bl -; 32-FAST-RA-NEXT: jne .LBB0_3 +; 32-FAST-RA-NEXT: je .LBB0_3 ; 32-FAST-RA-NEXT: # %bb.1: # %t ; 32-FAST-RA-NEXT: movl $42, %eax ; 32-FAST-RA-NEXT: jmp .LBB0_2 @@ -91,11 +91,11 @@ ; 64-ALL-NEXT: pushq %rbx ; 64-ALL-NEXT: movq %rsi, %rax ; 64-ALL-NEXT: lock cmpxchgq %rdx, (%rdi) -; 64-ALL-NEXT: setne %bl +; 64-ALL-NEXT: sete %bl ; 64-ALL-NEXT: movq %rax, %rdi ; 64-ALL-NEXT: callq bar@PLT ; 64-ALL-NEXT: testb %bl, %bl -; 64-ALL-NEXT: jne .LBB0_2 +; 64-ALL-NEXT: je .LBB0_2 ; 64-ALL-NEXT: # %bb.1: # %t ; 64-ALL-NEXT: movl $42, %eax ; 64-ALL-NEXT: popq %rbx diff --git a/llvm/test/CodeGen/X86/copy-eflags.ll b/llvm/test/CodeGen/X86/copy-eflags.ll --- a/llvm/test/CodeGen/X86/copy-eflags.ll +++ b/llvm/test/CodeGen/X86/copy-eflags.ll @@ -95,12 +95,12 @@ ; X32-NEXT: pushl %ebx ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: incl (%eax) -; X32-NEXT: setne %bl +; X32-NEXT: sete %bl ; X32-NEXT: pushl $42 ; X32-NEXT: calll external ; X32-NEXT: addl $4, %esp ; X32-NEXT: testb %bl, %bl -; X32-NEXT: jne .LBB1_2 +; X32-NEXT: je .LBB1_2 ; X32-NEXT: # %bb.1: # %then ; X32-NEXT: movl $64, %eax ; X32-NEXT: popl %ebx @@ -114,11 +114,11 @@ ; X64: # %bb.0: # %entry ; X64-NEXT: pushq %rbx ; X64-NEXT: incl (%rdi) -; X64-NEXT: setne %bl +; X64-NEXT: sete %bl ; X64-NEXT: movl $42, %edi ; X64-NEXT: callq external ; X64-NEXT: testb %bl, %bl -; X64-NEXT: jne .LBB1_2 +; X64-NEXT: je .LBB1_2 ; X64-NEXT: # %bb.1: # %then ; X64-NEXT: movl $64, %eax ; X64-NEXT: popq %rbx @@ -155,22 +155,22 @@ ; X32: # %bb.0: # %entry ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: incl (%eax) -; X32-NEXT: setne %al +; X32-NEXT: sete %al ; X32-NEXT: incb a ; X32-NEXT: sete d ; X32-NEXT: testb %al, %al -; X32-NEXT: jne external_b # TAILCALL +; X32-NEXT: je external_b # TAILCALL ; X32-NEXT: # %bb.1: # %then ; X32-NEXT: jmp external_a # TAILCALL ; ; X64-LABEL: test_tail_call: ; X64: # %bb.0: # %entry ; X64-NEXT: incl (%rdi) -; X64-NEXT: setne %al +; X64-NEXT: sete %al ; X64-NEXT: incb a(%rip) ; X64-NEXT: sete d(%rip) ; X64-NEXT: testb %al, %al -; X64-NEXT: jne external_b # TAILCALL +; X64-NEXT: je external_b # TAILCALL ; X64-NEXT: # %bb.1: # %then ; X64-NEXT: jmp external_a # TAILCALL entry: diff --git a/llvm/test/CodeGen/X86/cse-cmp.ll b/llvm/test/CodeGen/X86/cse-cmp.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/cse-cmp.ll @@ -0,0 +1,37 @@ +; RUN: llc -o - %s | FileCheck %s +; +; We should see 1 cmp instruction used to produce the flags for both +; conditional jumps. This currently happens by means of Machine CSE +; but requires instruction selection to actually select the exact same +; comparison twice. +define i32 @foo(i32 %arg) { +; CHECK-LABEL: foo: +; CHECK: cmpl $1, %edi +; CHECK-NOT: cmpl + %i1 = icmp eq i32 %arg, 1 + br i1 %i1, label %bb5, label %bb2 + +bb2: + %i3 = icmp sgt i32 %arg, 1 + br i1 %i3, label %bb3, label %bb4 + +bb3: + call void @f0() + br label %return + +bb4: + call void @f1() + br label %return + +bb5: + call void @f2() + br label %return + +return: + %v = phi i32 [0, %bb3], [11, %bb4], [22, %bb5] + ret i32 %v +} + +declare void @f0() +declare void @f1() +declare void @f2() diff --git a/llvm/test/CodeGen/X86/fp128-cast.ll b/llvm/test/CodeGen/X86/fp128-cast.ll --- a/llvm/test/CodeGen/X86/fp128-cast.ll +++ b/llvm/test/CodeGen/X86/fp128-cast.ll @@ -1254,8 +1254,8 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind { ; X64-SSE-LABEL: TestTruncCopysign: ; X64-SSE: # %bb.0: # %entry -; X64-SSE-NEXT: cmpl $50001, %edi # imm = 0xC351 -; X64-SSE-NEXT: jl .LBB26_2 +; X64-SSE-NEXT: cmpl $50000, %edi # imm = 0xC350 +; X64-SSE-NEXT: jle .LBB26_2 ; X64-SSE-NEXT: # %bb.1: # %if.then ; X64-SSE-NEXT: pushq %rax ; X64-SSE-NEXT: callq __trunctfdf2@PLT @@ -1276,8 +1276,8 @@ ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %edi ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; X32-NEXT: cmpl $50001, {{[0-9]+}}(%esp) # imm = 0xC351 -; X32-NEXT: jl .LBB26_4 +; X32-NEXT: cmpl $50000, {{[0-9]+}}(%esp) # imm = 0xC350 +; X32-NEXT: jle .LBB26_4 ; X32-NEXT: # %bb.1: # %if.then ; X32-NEXT: pushl %eax ; X32-NEXT: pushl %ecx @@ -1318,8 +1318,8 @@ ; ; X64-AVX-LABEL: TestTruncCopysign: ; X64-AVX: # %bb.0: # %entry -; X64-AVX-NEXT: cmpl $50001, %edi # imm = 0xC351 -; X64-AVX-NEXT: jl .LBB26_2 +; X64-AVX-NEXT: cmpl $50000, %edi # imm = 0xC350 +; X64-AVX-NEXT: jle .LBB26_2 ; X64-AVX-NEXT: # %bb.1: # %if.then ; X64-AVX-NEXT: pushq %rax ; X64-AVX-NEXT: callq __trunctfdf2@PLT diff --git a/llvm/test/CodeGen/X86/fp128-select.ll b/llvm/test/CodeGen/X86/fp128-select.ll --- a/llvm/test/CodeGen/X86/fp128-select.ll +++ b/llvm/test/CodeGen/X86/fp128-select.ll @@ -50,7 +50,7 @@ ; SSE-NEXT: .cfi_offset %rbx, -16 ; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill -; SSE-NEXT: callq __netf2@PLT +; SSE-NEXT: callq __eqtf2@PLT ; SSE-NEXT: movl %eax, %ebx ; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload @@ -77,52 +77,32 @@ ; ; NOSSE-LABEL: test_select_cc: ; NOSSE: # %bb.0: # %BB0 -; NOSSE-NEXT: pushq %rbp +; NOSSE-NEXT: pushq %r14 ; NOSSE-NEXT: .cfi_def_cfa_offset 16 -; NOSSE-NEXT: pushq %r15 +; NOSSE-NEXT: pushq %rbx ; NOSSE-NEXT: .cfi_def_cfa_offset 24 -; NOSSE-NEXT: pushq %r14 +; NOSSE-NEXT: pushq %rax ; NOSSE-NEXT: .cfi_def_cfa_offset 32 -; NOSSE-NEXT: pushq %r12 -; NOSSE-NEXT: .cfi_def_cfa_offset 40 -; NOSSE-NEXT: pushq %rbx -; NOSSE-NEXT: .cfi_def_cfa_offset 48 -; NOSSE-NEXT: .cfi_offset %rbx, -48 -; NOSSE-NEXT: .cfi_offset %r12, -40 -; NOSSE-NEXT: .cfi_offset %r14, -32 -; NOSSE-NEXT: .cfi_offset %r15, -24 -; NOSSE-NEXT: .cfi_offset %rbp, -16 -; NOSSE-NEXT: movq %rcx, %r12 -; NOSSE-NEXT: movq %rdx, %rbx +; NOSSE-NEXT: .cfi_offset %rbx, -24 +; NOSSE-NEXT: .cfi_offset %r14, -16 ; NOSSE-NEXT: movq %rsi, %r14 -; NOSSE-NEXT: movq %rdi, %r15 -; NOSSE-NEXT: callq __netf2@PLT -; NOSSE-NEXT: movl %eax, %ebp -; NOSSE-NEXT: movq %r15, %rdi -; NOSSE-NEXT: movq %r14, %rsi -; NOSSE-NEXT: movq %rbx, %rdx -; NOSSE-NEXT: movq %r12, %rcx +; NOSSE-NEXT: movq %rdi, %rbx ; NOSSE-NEXT: callq __eqtf2@PLT ; NOSSE-NEXT: movl %eax, %ecx ; NOSSE-NEXT: xorl %eax, %eax ; NOSSE-NEXT: testl %ecx, %ecx ; NOSSE-NEXT: movabsq $4611404543450677248, %rdx # imm = 0x3FFF000000000000 ; NOSSE-NEXT: cmovneq %rax, %rdx -; NOSSE-NEXT: testl %ebp, %ebp ; NOSSE-NEXT: je .LBB1_2 ; NOSSE-NEXT: # %bb.1: -; NOSSE-NEXT: movq %r15, %rax +; NOSSE-NEXT: movq %rbx, %rax ; NOSSE-NEXT: movq %r14, %rdx ; NOSSE-NEXT: .LBB1_2: # %BB2 -; NOSSE-NEXT: popq %rbx -; NOSSE-NEXT: .cfi_def_cfa_offset 40 -; NOSSE-NEXT: popq %r12 -; NOSSE-NEXT: .cfi_def_cfa_offset 32 -; NOSSE-NEXT: popq %r14 +; NOSSE-NEXT: addq $8, %rsp ; NOSSE-NEXT: .cfi_def_cfa_offset 24 -; NOSSE-NEXT: popq %r15 +; NOSSE-NEXT: popq %rbx ; NOSSE-NEXT: .cfi_def_cfa_offset 16 -; NOSSE-NEXT: popq %rbp +; NOSSE-NEXT: popq %r14 ; NOSSE-NEXT: .cfi_def_cfa_offset 8 ; NOSSE-NEXT: retq BB0: diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll --- a/llvm/test/CodeGen/X86/jump_sign.ll +++ b/llvm/test/CodeGen/X86/jump_sign.ll @@ -218,11 +218,11 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB12_1 +; CHECK-NEXT: jne .LBB12_1 ; CHECK-NEXT: # %bb.2: # %if.end.i ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB12_5 +; CHECK-NEXT: je .LBB12_5 ; CHECK-NEXT: # %bb.3: # %sw.bb ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al @@ -237,13 +237,13 @@ ; CHECK-NEXT: .LBB12_8: # %if.then44 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB12_9 +; CHECK-NEXT: jne .LBB12_9 ; CHECK-NEXT: # %bb.10: # %if.else.i104 ; CHECK-NEXT: retl ; CHECK-NEXT: .LBB12_5: # %sw.default ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB12_7 +; CHECK-NEXT: je .LBB12_7 ; CHECK-NEXT: # %bb.6: # %if.then.i96 ; CHECK-NEXT: .LBB12_1: # %if.then.i ; CHECK-NEXT: .LBB12_9: # %if.then.i103 diff --git a/llvm/test/CodeGen/X86/lea.ll b/llvm/test/CodeGen/X86/lea.ll --- a/llvm/test/CodeGen/X86/lea.ll +++ b/llvm/test/CodeGen/X86/lea.ll @@ -28,8 +28,8 @@ ; LINUX-LABEL: test2: ; LINUX: # %bb.0: # %entry ; LINUX-NEXT: # kill: def $edi killed $edi def $rdi -; LINUX-NEXT: cmpl $5, %edi -; LINUX-NEXT: jl .LBB1_2 +; LINUX-NEXT: cmpl $4, %edi +; LINUX-NEXT: jle .LBB1_2 ; LINUX-NEXT: # %bb.1: # %bb.nph ; LINUX-NEXT: leal -5(%rdi), %eax ; LINUX-NEXT: andl $-4, %eax @@ -43,8 +43,8 @@ ; WIN-LABEL: test2: ; WIN: # %bb.0: # %entry ; WIN-NEXT: # kill: def $ecx killed $ecx def $rcx -; WIN-NEXT: cmpl $5, %ecx -; WIN-NEXT: jl .LBB1_2 +; WIN-NEXT: cmpl $4, %ecx +; WIN-NEXT: jle .LBB1_2 ; WIN-NEXT: # %bb.1: # %bb.nph ; WIN-NEXT: leal -5(%rcx), %eax ; WIN-NEXT: andl $-4, %eax diff --git a/llvm/test/CodeGen/X86/legalize-shift-64.ll b/llvm/test/CodeGen/X86/legalize-shift-64.ll --- a/llvm/test/CodeGen/X86/legalize-shift-64.ll +++ b/llvm/test/CodeGen/X86/legalize-shift-64.ll @@ -143,9 +143,9 @@ ; CHECK-NEXT: subl $16, %esp ; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB5_3 +; CHECK-NEXT: je .LBB5_3 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: jmp .LBB5_2 diff --git a/llvm/test/CodeGen/X86/loop-blocks.ll b/llvm/test/CodeGen/X86/loop-blocks.ll --- a/llvm/test/CodeGen/X86/loop-blocks.ll +++ b/llvm/test/CodeGen/X86/loop-blocks.ll @@ -85,8 +85,8 @@ ; CHECK-NEXT: jge .LBB2_2 ; CHECK-NEXT: callq bar99 ; CHECK-NEXT: callq get -; CHECK-NEXT: cmpl $2999, %eax -; CHECK-NEXT: jg .LBB2_6 +; CHECK-NEXT: cmpl $3000, %eax +; CHECK-NEXT: jge .LBB2_6 ; CHECK-NEXT: callq block_a_true_func ; CHECK-NEXT: callq block_a_merge_func ; CHECK-NEXT: jmp .LBB2_1 diff --git a/llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll b/llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll --- a/llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll +++ b/llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll @@ -70,7 +70,7 @@ ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm %stack.4.i, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.i)\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; -; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.6, 13, implicit killed $eflags\n}"]; +; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.2, 12, implicit killed $eflags\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{CMP32rm killed renamable $eax, %stack.2.secret_size.addr, 1, $noreg, 0, $noreg, implicit-def $eflags :: (dereferenceable load (s32) from %ir.secret_size.addr)\n}"]; @@ -79,7 +79,7 @@ ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm %stack.4.i, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.i)\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; -; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.4, 5, implicit killed $eflags\n}"]; +; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.3, 4, implicit killed $eflags\n}"]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1]; ; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $rax = MOV64rm %stack.1.secret.addr, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.secret.addr)\n}"]; diff --git a/llvm/test/CodeGen/X86/machine-cse.ll b/llvm/test/CodeGen/X86/machine-cse.ll --- a/llvm/test/CodeGen/X86/machine-cse.ll +++ b/llvm/test/CodeGen/X86/machine-cse.ll @@ -16,7 +16,7 @@ ; CHECK-NEXT: leaq (%rax,%rax,4), %rdi ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: .LBB0_2: # %bb2 @@ -53,12 +53,12 @@ ; CHECK-NEXT: # kill: def $esi killed $esi def $rsi ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: leal -1(%rdi), %eax -; CHECK-NEXT: cmpl $2, %eax -; CHECK-NEXT: ja .LBB1_4 +; CHECK-NEXT: cmpl $3, %eax +; CHECK-NEXT: jae .LBB1_4 ; CHECK-NEXT: # %bb.1: # %sw.bb ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_4 +; CHECK-NEXT: je .LBB1_4 ; CHECK-NEXT: # %bb.2: # %if.end34 ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: imull %edi, %esi diff --git a/llvm/test/CodeGen/X86/masked_compressstore.ll b/llvm/test/CodeGen/X86/masked_compressstore.ll --- a/llvm/test/CodeGen/X86/masked_compressstore.ll +++ b/llvm/test/CodeGen/X86/masked_compressstore.ll @@ -1292,7 +1292,7 @@ ; SSE2-NEXT: pmovmskb %xmm8, %eax ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: orl %ecx, %eax -; SSE2-NEXT: testb $1, %al +; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: jne LBB6_1 ; SSE2-NEXT: ## %bb.2: ## %else ; SSE2-NEXT: testb $2, %al @@ -1616,7 +1616,7 @@ ; SSE42-NEXT: pmovmskb %xmm8, %eax ; SSE42-NEXT: shll $16, %eax ; SSE42-NEXT: orl %ecx, %eax -; SSE42-NEXT: testb $1, %al +; SSE42-NEXT: testb $1, %cl ; SSE42-NEXT: jne LBB6_1 ; SSE42-NEXT: ## %bb.2: ## %else ; SSE42-NEXT: testb $2, %al @@ -1897,7 +1897,7 @@ ; AVX1-NEXT: vpmovmskb %xmm4, %eax ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax -; AVX1-NEXT: testb $1, %al +; AVX1-NEXT: testb $1, %cl ; AVX1-NEXT: jne LBB6_1 ; AVX1-NEXT: ## %bb.2: ## %else ; AVX1-NEXT: testb $2, %al diff --git a/llvm/test/CodeGen/X86/masked_expandload.ll b/llvm/test/CodeGen/X86/masked_expandload.ll --- a/llvm/test/CodeGen/X86/masked_expandload.ll +++ b/llvm/test/CodeGen/X86/masked_expandload.ll @@ -1389,7 +1389,7 @@ ; SSE2-NEXT: pmovmskb %xmm8, %ecx ; SSE2-NEXT: shll $16, %ecx ; SSE2-NEXT: orl %edx, %ecx -; SSE2-NEXT: testb $1, %cl +; SSE2-NEXT: testb $1, %dl ; SSE2-NEXT: jne LBB8_1 ; SSE2-NEXT: ## %bb.2: ## %else ; SSE2-NEXT: testb $2, %cl @@ -1746,7 +1746,7 @@ ; SSE42-NEXT: pmovmskb %xmm8, %ecx ; SSE42-NEXT: shll $16, %ecx ; SSE42-NEXT: orl %edx, %ecx -; SSE42-NEXT: testb $1, %cl +; SSE42-NEXT: testb $1, %dl ; SSE42-NEXT: jne LBB8_1 ; SSE42-NEXT: ## %bb.2: ## %else ; SSE42-NEXT: testb $2, %cl @@ -2043,7 +2043,7 @@ ; AVX1-NEXT: vpmovmskb %xmm4, %eax ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax -; AVX1-NEXT: testb $1, %al +; AVX1-NEXT: testb $1, %cl ; AVX1-NEXT: jne LBB8_1 ; AVX1-NEXT: ## %bb.2: ## %else ; AVX1-NEXT: testb $2, %al diff --git a/llvm/test/CodeGen/X86/masked_load.ll b/llvm/test/CodeGen/X86/masked_load.ll --- a/llvm/test/CodeGen/X86/masked_load.ll +++ b/llvm/test/CodeGen/X86/masked_load.ll @@ -4532,7 +4532,7 @@ ; SSE2-NEXT: pmovmskb %xmm1, %eax ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: orl %ecx, %eax -; SSE2-NEXT: testb $1, %al +; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: jne LBB24_1 ; SSE2-NEXT: ## %bb.2: ## %else ; SSE2-NEXT: testb $2, %al @@ -4951,7 +4951,7 @@ ; SSE42-NEXT: pmovmskb %xmm1, %eax ; SSE42-NEXT: shll $16, %eax ; SSE42-NEXT: orl %ecx, %eax -; SSE42-NEXT: testb $1, %al +; SSE42-NEXT: testb $1, %cl ; SSE42-NEXT: jne LBB24_1 ; SSE42-NEXT: ## %bb.2: ## %else ; SSE42-NEXT: testb $2, %al @@ -5185,7 +5185,7 @@ ; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax -; AVX1-NEXT: testb $1, %al +; AVX1-NEXT: testb $1, %cl ; AVX1-NEXT: jne LBB24_1 ; AVX1-NEXT: ## %bb.2: ## %else ; AVX1-NEXT: testb $2, %al diff --git a/llvm/test/CodeGen/X86/masked_store.ll b/llvm/test/CodeGen/X86/masked_store.ll --- a/llvm/test/CodeGen/X86/masked_store.ll +++ b/llvm/test/CodeGen/X86/masked_store.ll @@ -3250,7 +3250,7 @@ ; SSE2-NEXT: pmovmskb %xmm1, %eax ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: orl %ecx, %eax -; SSE2-NEXT: testb $1, %al +; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: jne LBB16_1 ; SSE2-NEXT: ## %bb.2: ## %else @@ -3458,7 +3458,7 @@ ; SSE4-NEXT: pmovmskb %xmm1, %eax ; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: orl %ecx, %eax -; SSE4-NEXT: testb $1, %al +; SSE4-NEXT: testb $1, %cl ; SSE4-NEXT: jne LBB16_1 ; SSE4-NEXT: ## %bb.2: ## %else ; SSE4-NEXT: testb $2, %al @@ -3693,7 +3693,7 @@ ; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax -; AVX1-NEXT: testb $1, %al +; AVX1-NEXT: testb $1, %cl ; AVX1-NEXT: jne LBB16_1 ; AVX1-NEXT: ## %bb.2: ## %else ; AVX1-NEXT: testb $2, %al diff --git a/llvm/test/CodeGen/X86/masked_store_trunc.ll b/llvm/test/CodeGen/X86/masked_store_trunc.ll --- a/llvm/test/CodeGen/X86/masked_store_trunc.ll +++ b/llvm/test/CodeGen/X86/masked_store_trunc.ll @@ -4437,7 +4437,7 @@ ; SSE2-NEXT: notl %eax ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: orl %ecx, %eax -; SSE2-NEXT: testb $1, %al +; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: jne .LBB15_1 ; SSE2-NEXT: # %bb.2: # %else @@ -4654,7 +4654,7 @@ ; SSE4-NEXT: notl %eax ; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: orl %ecx, %eax -; SSE4-NEXT: testb $1, %al +; SSE4-NEXT: testb $1, %cl ; SSE4-NEXT: jne .LBB15_1 ; SSE4-NEXT: # %bb.2: # %else ; SSE4-NEXT: testb $2, %al @@ -4899,7 +4899,7 @@ ; AVX1-NEXT: notl %eax ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax -; AVX1-NEXT: testb $1, %al +; AVX1-NEXT: testb $1, %cl ; AVX1-NEXT: jne .LBB15_1 ; AVX1-NEXT: # %bb.2: # %else ; AVX1-NEXT: testb $2, %al diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll --- a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll +++ b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll @@ -5418,7 +5418,7 @@ ; SSE2-NEXT: notl %eax ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: orl %ecx, %eax -; SSE2-NEXT: testb $1, %al +; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: jne .LBB15_1 ; SSE2-NEXT: # %bb.2: # %else @@ -5630,7 +5630,7 @@ ; SSE4-NEXT: notl %eax ; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: orl %ecx, %eax -; SSE4-NEXT: testb $1, %al +; SSE4-NEXT: testb $1, %cl ; SSE4-NEXT: jne .LBB15_1 ; SSE4-NEXT: # %bb.2: # %else ; SSE4-NEXT: testb $2, %al @@ -5872,7 +5872,7 @@ ; AVX1-NEXT: notl %eax ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax -; AVX1-NEXT: testb $1, %al +; AVX1-NEXT: testb $1, %cl ; AVX1-NEXT: jne .LBB15_1 ; AVX1-NEXT: # %bb.2: # %else ; AVX1-NEXT: testb $2, %al diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll --- a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll +++ b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll @@ -5204,7 +5204,7 @@ ; SSE2-NEXT: notl %eax ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: orl %ecx, %eax -; SSE2-NEXT: testb $1, %al +; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: jne .LBB15_1 ; SSE2-NEXT: # %bb.2: # %else @@ -5425,7 +5425,7 @@ ; SSE4-NEXT: notl %eax ; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: orl %ecx, %eax -; SSE4-NEXT: testb $1, %al +; SSE4-NEXT: testb $1, %cl ; SSE4-NEXT: jne .LBB15_1 ; SSE4-NEXT: # %bb.2: # %else ; SSE4-NEXT: testb $2, %al @@ -5672,7 +5672,7 @@ ; AVX1-NEXT: notl %eax ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax -; AVX1-NEXT: testb $1, %al +; AVX1-NEXT: testb $1, %cl ; AVX1-NEXT: jne .LBB15_1 ; AVX1-NEXT: # %bb.2: # %else ; AVX1-NEXT: testb $2, %al diff --git a/llvm/test/CodeGen/X86/musttail-varargs.ll b/llvm/test/CodeGen/X86/musttail-varargs.ll --- a/llvm/test/CodeGen/X86/musttail-varargs.ll +++ b/llvm/test/CodeGen/X86/musttail-varargs.ll @@ -327,8 +327,8 @@ define void @h_thunk(%struct.Foo* %this, ...) { ; LINUX-LABEL: h_thunk: ; LINUX: # %bb.0: -; LINUX-NEXT: cmpb $1, (%rdi) -; LINUX-NEXT: jne .LBB2_2 +; LINUX-NEXT: cmpb $0, (%rdi) +; LINUX-NEXT: je .LBB2_2 ; LINUX-NEXT: # %bb.1: # %then ; LINUX-NEXT: movq 8(%rdi), %r11 ; LINUX-NEXT: jmpq *%r11 # TAILCALL @@ -339,8 +339,8 @@ ; ; LINUX-X32-LABEL: h_thunk: ; LINUX-X32: # %bb.0: -; LINUX-X32-NEXT: cmpb $1, (%edi) -; LINUX-X32-NEXT: jne .LBB2_2 +; LINUX-X32-NEXT: cmpb $0, (%edi) +; LINUX-X32-NEXT: je .LBB2_2 ; LINUX-X32-NEXT: # %bb.1: # %then ; LINUX-X32-NEXT: movl 4(%edi), %r11d ; LINUX-X32-NEXT: movl %edi, %edi @@ -353,8 +353,8 @@ ; ; WINDOWS-LABEL: h_thunk: ; WINDOWS: # %bb.0: -; WINDOWS-NEXT: cmpb $1, (%rcx) -; WINDOWS-NEXT: jne .LBB2_2 +; WINDOWS-NEXT: cmpb $0, (%rcx) +; WINDOWS-NEXT: je .LBB2_2 ; WINDOWS-NEXT: # %bb.1: # %then ; WINDOWS-NEXT: movq 8(%rcx), %rax ; WINDOWS-NEXT: rex64 jmpq *%rax # TAILCALL @@ -366,8 +366,8 @@ ; X86-LABEL: h_thunk: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: cmpb $1, (%eax) -; X86-NEXT: jne LBB2_2 +; X86-NEXT: cmpb $0, (%eax) +; X86-NEXT: je LBB2_2 ; X86-NEXT: # %bb.1: # %then ; X86-NEXT: movl 4(%eax), %ecx ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) diff --git a/llvm/test/CodeGen/X86/nobt.ll b/llvm/test/CodeGen/X86/nobt.ll --- a/llvm/test/CodeGen/X86/nobt.ll +++ b/llvm/test/CodeGen/X86/nobt.ll @@ -7,9 +7,9 @@ define void @test2(i32 %x, i32 %n) nounwind { ; CHECK-LABEL: test2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: calll foo@PLT ; CHECK-NEXT: .LBB0_2: # %UnifiedReturnBlock @@ -32,9 +32,9 @@ define void @test3(i32 %x, i32 %n) nounwind { ; CHECK-LABEL: test3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_2 +; CHECK-NEXT: je .LBB1_2 ; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: calll foo@PLT ; CHECK-NEXT: .LBB1_2: # %UnifiedReturnBlock @@ -57,9 +57,9 @@ define void @test4(i32 %x, i32 %n) nounwind { ; CHECK-LABEL: test4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB2_2 +; CHECK-NEXT: je .LBB2_2 ; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: calll foo@PLT ; CHECK-NEXT: .LBB2_2: # %UnifiedReturnBlock @@ -82,9 +82,9 @@ define void @test5(i32 %x, i32 %n) nounwind { ; CHECK-LABEL: test5: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB3_2 +; CHECK-NEXT: je .LBB3_2 ; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: calll foo@PLT ; CHECK-NEXT: .LBB3_2: # %UnifiedReturnBlock diff --git a/llvm/test/CodeGen/X86/optimize-max-0.ll b/llvm/test/CodeGen/X86/optimize-max-0.ll --- a/llvm/test/CodeGen/X86/optimize-max-0.ll +++ b/llvm/test/CodeGen/X86/optimize-max-0.ll @@ -65,8 +65,8 @@ ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload ; CHECK-NEXT: addl %ecx, %eax ; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill -; CHECK-NEXT: cmpl $1, %edi -; CHECK-NEXT: jle LBB0_13 +; CHECK-NEXT: cmpl $2, %edi +; CHECK-NEXT: jl LBB0_13 ; CHECK-NEXT: ## %bb.7: ## %bb.nph5 ; CHECK-NEXT: cmpl $2, %ebp ; CHECK-NEXT: jl LBB0_13 @@ -500,8 +500,8 @@ ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload ; CHECK-NEXT: addl %ecx, %eax ; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill -; CHECK-NEXT: cmpl $1, %ebp -; CHECK-NEXT: jbe LBB1_13 +; CHECK-NEXT: cmpl $2, %ebp +; CHECK-NEXT: jb LBB1_13 ; CHECK-NEXT: ## %bb.7: ## %bb.nph5 ; CHECK-NEXT: cmpl $2, %edi ; CHECK-NEXT: jb LBB1_13 diff --git a/llvm/test/CodeGen/X86/or-branch.ll b/llvm/test/CodeGen/X86/or-branch.ll --- a/llvm/test/CodeGen/X86/or-branch.ll +++ b/llvm/test/CodeGen/X86/or-branch.ll @@ -18,11 +18,11 @@ ; JUMP1-LABEL: foo: ; JUMP1: # %bb.0: # %entry ; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; JUMP1-NEXT: setne %al +; JUMP1-NEXT: sete %al ; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp) -; JUMP1-NEXT: setge %cl -; JUMP1-NEXT: testb %al, %cl -; JUMP1-NEXT: jne .LBB0_1 +; JUMP1-NEXT: setl %cl +; JUMP1-NEXT: orb %al, %cl +; JUMP1-NEXT: je .LBB0_1 ; JUMP1-NEXT: # %bb.2: # %cond_true ; JUMP1-NEXT: jmp bar@PLT # TAILCALL ; JUMP1-NEXT: .LBB0_1: # %UnifiedReturnBlock @@ -48,11 +48,11 @@ ; JUMP2-LABEL: unpredictable: ; JUMP2: # %bb.0: # %entry ; JUMP2-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; JUMP2-NEXT: setne %al +; JUMP2-NEXT: sete %al ; JUMP2-NEXT: cmpl $5, {{[0-9]+}}(%esp) -; JUMP2-NEXT: setge %cl -; JUMP2-NEXT: testb %al, %cl -; JUMP2-NEXT: jne .LBB1_1 +; JUMP2-NEXT: setl %cl +; JUMP2-NEXT: orb %al, %cl +; JUMP2-NEXT: je .LBB1_1 ; JUMP2-NEXT: # %bb.2: # %cond_true ; JUMP2-NEXT: jmp bar@PLT # TAILCALL ; JUMP2-NEXT: .LBB1_1: # %UnifiedReturnBlock @@ -61,11 +61,11 @@ ; JUMP1-LABEL: unpredictable: ; JUMP1: # %bb.0: # %entry ; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; JUMP1-NEXT: setne %al +; JUMP1-NEXT: sete %al ; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp) -; JUMP1-NEXT: setge %cl -; JUMP1-NEXT: testb %al, %cl -; JUMP1-NEXT: jne .LBB1_1 +; JUMP1-NEXT: setl %cl +; JUMP1-NEXT: orb %al, %cl +; JUMP1-NEXT: je .LBB1_1 ; JUMP1-NEXT: # %bb.2: # %cond_true ; JUMP1-NEXT: jmp bar@PLT # TAILCALL ; JUMP1-NEXT: .LBB1_1: # %UnifiedReturnBlock diff --git a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll --- a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll +++ b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll @@ -215,14 +215,14 @@ ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK32-NEXT: lock cmpxchg8b (%esi) -; CHECK32-NEXT: setne %bl +; CHECK32-NEXT: sete %bl ; CHECK32-NEXT: subl $8, %esp ; CHECK32-NEXT: pushl %edx ; CHECK32-NEXT: pushl %eax ; CHECK32-NEXT: calll bar@PLT ; CHECK32-NEXT: addl $16, %esp ; CHECK32-NEXT: testb %bl, %bl -; CHECK32-NEXT: jne .LBB4_3 +; CHECK32-NEXT: je .LBB4_3 ; CHECK32-NEXT: # %bb.1: # %t ; CHECK32-NEXT: movl $42, %eax ; CHECK32-NEXT: jmp .LBB4_2 @@ -240,11 +240,11 @@ ; CHECK64-NEXT: pushq %rbx ; CHECK64-NEXT: movq %rsi, %rax ; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi) -; CHECK64-NEXT: setne %bl +; CHECK64-NEXT: sete %bl ; CHECK64-NEXT: movq %rax, %rdi ; CHECK64-NEXT: callq bar@PLT ; CHECK64-NEXT: testb %bl, %bl -; CHECK64-NEXT: jne .LBB4_2 +; CHECK64-NEXT: je .LBB4_2 ; CHECK64-NEXT: # %bb.1: # %t ; CHECK64-NEXT: movl $42, %eax ; CHECK64-NEXT: popq %rbx @@ -284,7 +284,7 @@ ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK32-NEXT: lock cmpxchg8b (%esi) -; CHECK32-NEXT: setne {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill +; CHECK32-NEXT: sete {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl %ebp, %edx ; CHECK32-NEXT: movl %edi, %ecx @@ -293,7 +293,7 @@ ; CHECK32-NEXT: lock cmpxchg8b (%esi) ; CHECK32-NEXT: sete %al ; CHECK32-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload -; CHECK32-NEXT: jne .LBB5_4 +; CHECK32-NEXT: je .LBB5_4 ; CHECK32-NEXT: # %bb.1: # %entry ; CHECK32-NEXT: testb %al, %al ; CHECK32-NEXT: je .LBB5_4 @@ -315,12 +315,12 @@ ; CHECK64: # %bb.0: # %entry ; CHECK64-NEXT: movq %rsi, %rax ; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi) -; CHECK64-NEXT: setne %dl +; CHECK64-NEXT: sete %dl ; CHECK64-NEXT: movq %r8, %rax ; CHECK64-NEXT: lock cmpxchgq %r9, (%rcx) ; CHECK64-NEXT: sete %al ; CHECK64-NEXT: testb %dl, %dl -; CHECK64-NEXT: jne .LBB5_3 +; CHECK64-NEXT: je .LBB5_3 ; CHECK64-NEXT: # %bb.1: # %entry ; CHECK64-NEXT: testb %al, %al ; CHECK64-NEXT: je .LBB5_3 diff --git a/llvm/test/CodeGen/X86/pr29170.ll b/llvm/test/CodeGen/X86/pr29170.ll --- a/llvm/test/CodeGen/X86/pr29170.ll +++ b/llvm/test/CodeGen/X86/pr29170.ll @@ -11,7 +11,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: je .LBB0_3 ; CHECK-NEXT: # %bb.1: # %go ; CHECK-NEXT: movl $-1, %ecx ; CHECK-NEXT: movsbl b, %edx @@ -27,9 +27,8 @@ ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl entry: - %true = icmp eq i32 0, 0 %const = bitcast i64 -4294967296 to i64 - br i1 %true, label %go, label %if.else + br i1 undef, label %go, label %if.else go: %b = load i16, i16* @b, align 4 diff --git a/llvm/test/CodeGen/X86/pr36602.ll b/llvm/test/CodeGen/X86/pr36602.ll --- a/llvm/test/CodeGen/X86/pr36602.ll +++ b/llvm/test/CodeGen/X86/pr36602.ll @@ -5,9 +5,9 @@ define i32 @fn2() { ; CHECK-LABEL: fn2: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/pr38217.ll b/llvm/test/CodeGen/X86/pr38217.ll --- a/llvm/test/CodeGen/X86/pr38217.ll +++ b/llvm/test/CodeGen/X86/pr38217.ll @@ -6,8 +6,8 @@ define dso_local void @_Z12d2s_bufferedmPc(i64, i8* nocapture) { ; CHECK-LABEL: _Z12d2s_bufferedmPc: ; CHECK: # %bb.0: -; CHECK-NEXT: cmpq $10000, %rdi # imm = 0x2710 -; CHECK-NEXT: jb .LBB0_3 +; CHECK-NEXT: cmpq $9999, %rdi # imm = 0x270F +; CHECK-NEXT: jbe .LBB0_3 ; CHECK-NEXT: # %bb.1: # %.preheader ; CHECK-NEXT: movq %rdi, %r9 ; CHECK-NEXT: xorl %r10d, %r10d diff --git a/llvm/test/CodeGen/X86/pr38795.ll b/llvm/test/CodeGen/X86/pr38795.ll --- a/llvm/test/CodeGen/X86/pr38795.ll +++ b/llvm/test/CodeGen/X86/pr38795.ll @@ -45,7 +45,7 @@ ; CHECK-NEXT: # %bb.2: # %for.cond ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: # %bb.4: # %if.end ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: movl %ecx, %eax @@ -54,8 +54,8 @@ ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload ; CHECK-NEXT: movb %cl, %dh ; CHECK-NEXT: movl $0, h -; CHECK-NEXT: cmpb $8, %dl -; CHECK-NEXT: jg .LBB0_8 +; CHECK-NEXT: cmpb $9, %dl +; CHECK-NEXT: jge .LBB0_8 ; CHECK-NEXT: # %bb.5: # %if.then13 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: movl %eax, %esi @@ -85,7 +85,7 @@ ; CHECK-NEXT: .LBB0_11: # %af ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_12 +; CHECK-NEXT: je .LBB0_12 ; CHECK-NEXT: .LBB0_17: # %if.end39 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testl %eax, %eax @@ -125,7 +125,7 @@ ; CHECK-NEXT: .LBB0_9: # %ae ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_10 +; CHECK-NEXT: je .LBB0_10 ; CHECK-NEXT: # %bb.13: # %if.end26 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: xorl %ecx, %ecx @@ -144,7 +144,7 @@ ; CHECK-NEXT: .LBB0_10: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # implicit-def: $eax ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: je .LBB0_17 +; CHECK-NEXT: jne .LBB0_17 ; CHECK-NEXT: .LBB0_12: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # implicit-def: $edi ; CHECK-NEXT: # implicit-def: $cl diff --git a/llvm/test/CodeGen/X86/pr46585.ll b/llvm/test/CodeGen/X86/pr46585.ll --- a/llvm/test/CodeGen/X86/pr46585.ll +++ b/llvm/test/CodeGen/X86/pr46585.ll @@ -7,9 +7,9 @@ define void @spam() local_unnamed_addr { ; CHECK-LABEL: spam: ; CHECK: ## %bb.0: ## %bb -; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_2 +; CHECK-NEXT: jne LBB0_2 ; CHECK-NEXT: ## %bb.1: ## %bb9 ; CHECK-NEXT: movq _global.1@GOTPCREL(%rip), %rax ; CHECK-NEXT: movq $1, (%rax) diff --git a/llvm/test/CodeGen/X86/pr46827.ll b/llvm/test/CodeGen/X86/pr46827.ll --- a/llvm/test/CodeGen/X86/pr46827.ll +++ b/llvm/test/CodeGen/X86/pr46827.ll @@ -20,8 +20,8 @@ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: $eflags ; CHECK: %2:gr32 = PHI %3, %bb.3, %4, %bb.4 -; CHECK: JCC_1 %bb.2, 5, implicit $eflags -; CHECK: JMP_1 %bb.1 +; CHECK: JCC_1 %bb.1, 4, implicit $eflags +; CHECK: JMP_1 %bb.2 declare i32 @llvm.x86.xbegin() #0 diff --git a/llvm/test/CodeGen/X86/pr50254.ll b/llvm/test/CodeGen/X86/pr50254.ll --- a/llvm/test/CodeGen/X86/pr50254.ll +++ b/llvm/test/CodeGen/X86/pr50254.ll @@ -10,7 +10,7 @@ ; X86-NEXT: movswl d.e, %eax ; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: testb %cl, %cl -; X86-NEXT: jne .LBB0_2 +; X86-NEXT: je .LBB0_2 ; X86-NEXT: # %bb.1: # %for.end ; X86-NEXT: movw %ax, d.e ; X86-NEXT: .LBB0_2: # %for.body.1 @@ -21,7 +21,7 @@ ; X64-NEXT: movswq d.e(%rip), %rax ; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: testb %cl, %cl -; X64-NEXT: jne .LBB0_2 +; X64-NEXT: je .LBB0_2 ; X64-NEXT: # %bb.1: # %for.end ; X64-NEXT: movw %ax, d.e(%rip) ; X64-NEXT: .LBB0_2: # %for.body.1 diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll --- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll +++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll @@ -42,7 +42,7 @@ ; CHECK-NEXT: ## %bb.1: ## %if.end ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_5 +; CHECK-NEXT: je LBB0_5 ; CHECK-NEXT: ## %bb.2: ## %if.then4 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al @@ -93,7 +93,7 @@ ; CHECK-NEXT: movq %rbp, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill ; CHECK-NEXT: xorl %r12d, %r12d ; CHECK-NEXT: testb %r12b, %r12b -; CHECK-NEXT: jne LBB0_11 +; CHECK-NEXT: je LBB0_11 ; CHECK-NEXT: ## %bb.12: ## %while.body200.preheader ; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx @@ -164,7 +164,7 @@ ; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2 ; CHECK-NEXT: leaq 1(%rbp), %rax ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: je LBB0_33 +; CHECK-NEXT: jne LBB0_33 ; CHECK-NEXT: LBB0_29: ## %land.rhs485 ; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 @@ -180,7 +180,7 @@ ; CHECK-NEXT: movl $256, %esi ## imm = 0x100 ; CHECK-NEXT: callq ___maskrune ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne LBB0_32 +; CHECK-NEXT: je LBB0_32 ; CHECK-NEXT: jmp LBB0_34 ; CHECK-NEXT: LBB0_45: ## %sw.bb1134 ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 @@ -230,7 +230,7 @@ ; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne LBB0_38 +; CHECK-NEXT: je LBB0_38 ; CHECK-NEXT: ## %bb.39: ## %for.cond542.preheader ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 ; CHECK-NEXT: testb %bl, %bl @@ -300,7 +300,7 @@ ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload ; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp ## 4-byte Reload -; CHECK-NEXT: jne LBB0_54 +; CHECK-NEXT: je LBB0_54 ; CHECK-NEXT: ## %bb.52: ## %while.body1679.preheader ; CHECK-NEXT: incl %ebp ; CHECK-NEXT: .p2align 4, 0x90 diff --git a/llvm/test/CodeGen/X86/reverse_branches.ll b/llvm/test/CodeGen/X86/reverse_branches.ll --- a/llvm/test/CodeGen/X86/reverse_branches.ll +++ b/llvm/test/CodeGen/X86/reverse_branches.ll @@ -44,8 +44,8 @@ ; CHECK-NEXT: LBB0_1: ## %for.cond ; CHECK-NEXT: ## =>This Loop Header: Depth=1 ; CHECK-NEXT: ## Child Loop BB0_3 Depth 2 -; CHECK-NEXT: cmpl $999, %r12d ## imm = 0x3E7 -; CHECK-NEXT: jg LBB0_7 +; CHECK-NEXT: cmpl $1000, %r12d ## imm = 0x3E8 +; CHECK-NEXT: jge LBB0_7 ; CHECK-NEXT: ## %bb.2: ## %for.cond1.preheader ; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: movl $-1, %ebp @@ -56,8 +56,8 @@ ; CHECK-NEXT: ## Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: incl %ebp -; CHECK-NEXT: cmpl $999, %ebp ## imm = 0x3E7 -; CHECK-NEXT: jg LBB0_6 +; CHECK-NEXT: cmpl $1000, %ebp ## imm = 0x3E8 +; CHECK-NEXT: jge LBB0_6 ; CHECK-NEXT: ## %bb.4: ## %for.body3 ; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=2 ; CHECK-NEXT: addq $1002, %rbx ## imm = 0x3EA @@ -83,8 +83,8 @@ ; CHECK-NEXT: ## =>This Loop Header: Depth=1 ; CHECK-NEXT: ## Child Loop BB0_10 Depth 2 ; CHECK-NEXT: ## Child Loop BB0_12 Depth 3 -; CHECK-NEXT: cmpl $999, %eax ## imm = 0x3E7 -; CHECK-NEXT: jg LBB0_16 +; CHECK-NEXT: cmpl $1000, %eax ## imm = 0x3E8 +; CHECK-NEXT: jge LBB0_16 ; CHECK-NEXT: ## %bb.9: ## %for.cond18.preheader ; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 ; CHECK-NEXT: movq %rcx, %rdx @@ -104,8 +104,8 @@ ; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1 ; CHECK-NEXT: ## => This Loop Header: Depth=2 ; CHECK-NEXT: ## Child Loop BB0_12 Depth 3 -; CHECK-NEXT: cmpl $999, %edi ## imm = 0x3E7 -; CHECK-NEXT: jg LBB0_15 +; CHECK-NEXT: cmpl $1000, %edi ## imm = 0x3E8 +; CHECK-NEXT: jge LBB0_15 ; CHECK-NEXT: ## %bb.11: ## %for.body20 ; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2 ; CHECK-NEXT: movq $-1000, %rbp ## imm = 0xFC18 diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll --- a/llvm/test/CodeGen/X86/select.ll +++ b/llvm/test/CodeGen/X86/select.ll @@ -60,8 +60,8 @@ ; GENERIC-NEXT: testb $1, %al ; GENERIC-NEXT: movl $-3840, %eax ## imm = 0xF100 ; GENERIC-NEXT: cmovnel %ecx, %eax -; GENERIC-NEXT: cmpl $32768, %eax ## imm = 0x8000 -; GENERIC-NEXT: jge LBB1_1 +; GENERIC-NEXT: cmpl $32767, %eax ## imm = 0x7FFF +; GENERIC-NEXT: jg LBB1_1 ; GENERIC-NEXT: ## %bb.2: ## %bb91 ; GENERIC-NEXT: xorl %eax, %eax ; GENERIC-NEXT: popq %rcx @@ -77,8 +77,8 @@ ; ATOM-NEXT: movl $-3840, %edx ## imm = 0xF100 ; ATOM-NEXT: testb $1, %al ; ATOM-NEXT: cmovnel %ecx, %edx -; ATOM-NEXT: cmpl $32768, %edx ## imm = 0x8000 -; ATOM-NEXT: jge LBB1_1 +; ATOM-NEXT: cmpl $32767, %edx ## imm = 0x7FFF +; ATOM-NEXT: jg LBB1_1 ; ATOM-NEXT: ## %bb.2: ## %bb91 ; ATOM-NEXT: xorl %eax, %eax ; ATOM-NEXT: popq %rcx @@ -94,8 +94,8 @@ ; ATHLON-NEXT: testb $1, %al ; ATHLON-NEXT: movl $-3840, %eax ## imm = 0xF100 ; ATHLON-NEXT: cmovnel %ecx, %eax -; ATHLON-NEXT: cmpl $32768, %eax ## imm = 0x8000 -; ATHLON-NEXT: jge LBB1_1 +; ATHLON-NEXT: cmpl $32767, %eax ## imm = 0x7FFF +; ATHLON-NEXT: jg LBB1_1 ; ATHLON-NEXT: ## %bb.2: ## %bb91 ; ATHLON-NEXT: xorl %eax, %eax ; ATHLON-NEXT: addl $12, %esp @@ -112,8 +112,8 @@ ; MCU-NEXT: # %bb.1: # %entry ; MCU-NEXT: movl $-3840, %ecx # imm = 0xF100 ; MCU-NEXT: .LBB1_2: # %entry -; MCU-NEXT: cmpl $32768, %ecx # imm = 0x8000 -; MCU-NEXT: jge .LBB1_3 +; MCU-NEXT: cmpl $32767, %ecx # imm = 0x7FFF +; MCU-NEXT: jg .LBB1_3 ; MCU-NEXT: # %bb.4: # %bb91 ; MCU-NEXT: xorl %eax, %eax ; MCU-NEXT: retl diff --git a/llvm/test/CodeGen/X86/setcc-freeze.ll b/llvm/test/CodeGen/X86/setcc-freeze.ll --- a/llvm/test/CodeGen/X86/setcc-freeze.ll +++ b/llvm/test/CodeGen/X86/setcc-freeze.ll @@ -26,9 +26,9 @@ define i32 @f_false(i16* %p) { ; CHECK-LABEL: f_false: ; CHECK: # %bb.0: -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_2 +; CHECK-NEXT: je .LBB1_2 ; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq @@ -49,9 +49,9 @@ define i32 @f_false2(i16* %p) { ; CHECK-LABEL: f_false2: ; CHECK: # %bb.0: -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB2_2 +; CHECK-NEXT: je .LBB2_2 ; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq @@ -72,9 +72,9 @@ define i32 @f_false3(i16* %p) { ; CHECK-LABEL: f_false3: ; CHECK: # %bb.0: -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB3_2 +; CHECK-NEXT: je .LBB3_2 ; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq @@ -95,9 +95,9 @@ define i32 @f_false4(i16* %p) { ; CHECK-LABEL: f_false4: ; CHECK: # %bb.0: -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB4_2 +; CHECK-NEXT: je .LBB4_2 ; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq @@ -118,9 +118,9 @@ define i32 @f_true(i16* %p) { ; CHECK-LABEL: f_true: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB5_2 +; CHECK-NEXT: je .LBB5_2 ; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq @@ -141,9 +141,9 @@ define i32 @f_true2(i16* %p) { ; CHECK-LABEL: f_true2: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB6_2 +; CHECK-NEXT: je .LBB6_2 ; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq @@ -164,9 +164,9 @@ define i32 @f_true3(i16* %p) { ; CHECK-LABEL: f_true3: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB7_2 +; CHECK-NEXT: je .LBB7_2 ; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq @@ -187,9 +187,9 @@ define i32 @f_true4(i16* %p) { ; CHECK-LABEL: f_true4: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB8_2 +; CHECK-NEXT: je .LBB8_2 ; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll --- a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll +++ b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll @@ -285,9 +285,9 @@ define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind !prof !14 { ; CHECK-LABEL: test_sext_i8_icmp_255: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: jne bar # TAILCALL ; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/shrink-compare.ll b/llvm/test/CodeGen/X86/shrink-compare.ll --- a/llvm/test/CodeGen/X86/shrink-compare.ll +++ b/llvm/test/CodeGen/X86/shrink-compare.ll @@ -285,9 +285,9 @@ define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind minsize { ; CHECK-LABEL: test_sext_i8_icmp_255: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: jne bar # TAILCALL ; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/sibcall.ll b/llvm/test/CodeGen/X86/sibcall.ll --- a/llvm/test/CodeGen/X86/sibcall.ll +++ b/llvm/test/CodeGen/X86/sibcall.ll @@ -123,8 +123,8 @@ ; X86: # %bb.0: ; X86-NEXT: subl $12, %esp ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: cmpl $9, %eax -; X86-NEXT: jg .LBB6_2 +; X86-NEXT: cmpl $10, %eax +; X86-NEXT: jge .LBB6_2 ; X86-NEXT: # %bb.1: # %bb ; X86-NEXT: decl %eax ; X86-NEXT: movl %eax, (%esp) @@ -137,8 +137,8 @@ ; ; X64-LABEL: t6: ; X64: # %bb.0: -; X64-NEXT: cmpl $9, %edi -; X64-NEXT: jg .LBB6_2 +; X64-NEXT: cmpl $10, %edi +; X64-NEXT: jge .LBB6_2 ; X64-NEXT: # %bb.1: # %bb ; X64-NEXT: decl %edi ; X64-NEXT: jmp t6 # TAILCALL @@ -147,8 +147,8 @@ ; ; X32-LABEL: t6: ; X32: # %bb.0: -; X32-NEXT: cmpl $9, %edi -; X32-NEXT: jg .LBB6_2 +; X32-NEXT: cmpl $10, %edi +; X32-NEXT: jge .LBB6_2 ; X32-NEXT: # %bb.1: # %bb ; X32-NEXT: decl %edi ; X32-NEXT: jmp t6 # TAILCALL @@ -988,11 +988,11 @@ ; ; X64-LABEL: t22_non_sret_to_sret: ; X64: # %bb.0: -; X64-NEXT: jmp t22_f_sret@PLT # TAILCALL +; X64-NEXT: jmp t22_f_sret@PLT # TAILCALL ; ; X32-LABEL: t22_non_sret_to_sret: ; X32: # %bb.0: -; X32-NEXT: jmp t22_f_sret@PLT # TAILCALL +; X32-NEXT: jmp t22_f_sret@PLT # TAILCALL tail call ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind ret void } diff --git a/llvm/test/CodeGen/X86/slow-incdec.ll b/llvm/test/CodeGen/X86/slow-incdec.ll --- a/llvm/test/CodeGen/X86/slow-incdec.ll +++ b/llvm/test/CodeGen/X86/slow-incdec.ll @@ -125,11 +125,11 @@ ; INCDEC: # %bb.0: # %entry ; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax ; INCDEC-NEXT: incl (%eax) -; INCDEC-NEXT: setne %al +; INCDEC-NEXT: sete %al ; INCDEC-NEXT: incb a ; INCDEC-NEXT: sete d ; INCDEC-NEXT: testb %al, %al -; INCDEC-NEXT: jne .LBB7_2 +; INCDEC-NEXT: je .LBB7_2 ; INCDEC-NEXT: # %bb.1: # %then ; INCDEC-NEXT: jmp external_a@PLT # TAILCALL ; INCDEC-NEXT: .LBB7_2: # %else @@ -139,11 +139,11 @@ ; ADD: # %bb.0: # %entry ; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax ; ADD-NEXT: addl $1, (%eax) -; ADD-NEXT: setne %al +; ADD-NEXT: sete %al ; ADD-NEXT: addb $1, a ; ADD-NEXT: sete d ; ADD-NEXT: testb %al, %al -; ADD-NEXT: jne .LBB7_2 +; ADD-NEXT: je .LBB7_2 ; ADD-NEXT: # %bb.1: # %then ; ADD-NEXT: jmp external_a@PLT # TAILCALL ; ADD-NEXT: .LBB7_2: # %else diff --git a/llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll b/llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll --- a/llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll +++ b/llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll @@ -42,9 +42,9 @@ ; CHECK-NEXT: lfence ; CHECK-NEXT: movl $4, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: lfence -; CHECK-NEXT: cmpl $3, (%rdi) +; CHECK-NEXT: cmpl $4, (%rdi) ; CHECK-NEXT: lfence -; CHECK-NEXT: jg .LBB1_2 +; CHECK-NEXT: jge .LBB1_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: lfence ; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax @@ -69,8 +69,8 @@ ; X86-ONE-LFENCE-NEXT: lfence ; X86-ONE-LFENCE-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; X86-ONE-LFENCE-NEXT: movl $4, -{{[0-9]+}}(%rsp) -; X86-ONE-LFENCE-NEXT: cmpl $3, (%rdi) -; X86-ONE-LFENCE-NEXT: jg .LBB1_2 +; X86-ONE-LFENCE-NEXT: cmpl $4, (%rdi) +; X86-ONE-LFENCE-NEXT: jge .LBB1_2 ; X86-ONE-LFENCE-NEXT: # %bb.1: # %if.then ; X86-ONE-LFENCE-NEXT: lfence ; X86-ONE-LFENCE-NEXT: movq -{{[0-9]+}}(%rsp), %rax @@ -92,8 +92,8 @@ ; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: movl $4, -{{[0-9]+}}(%rsp) ; X86-OMIT-BR-NEXT: lfence -; X86-OMIT-BR-NEXT: cmpl $3, (%rdi) -; X86-OMIT-BR-NEXT: jg .LBB1_2 +; X86-OMIT-BR-NEXT: cmpl $4, (%rdi) +; X86-OMIT-BR-NEXT: jge .LBB1_2 ; X86-OMIT-BR-NEXT: # %bb.1: # %if.then ; X86-OMIT-BR-NEXT: lfence ; X86-OMIT-BR-NEXT: movq -{{[0-9]+}}(%rsp), %rax @@ -120,9 +120,9 @@ ; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: movl $4, -{{[0-9]+}}(%rsp) ; X86-NON-CONST-NEXT: lfence -; X86-NON-CONST-NEXT: cmpl $3, (%rdi) +; X86-NON-CONST-NEXT: cmpl $4, (%rdi) ; X86-NON-CONST-NEXT: lfence -; X86-NON-CONST-NEXT: jg .LBB1_2 +; X86-NON-CONST-NEXT: jge .LBB1_2 ; X86-NON-CONST-NEXT: # %bb.1: # %if.then ; X86-NON-CONST-NEXT: lfence ; X86-NON-CONST-NEXT: movq -{{[0-9]+}}(%rsp), %rax diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll --- a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll +++ b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll @@ -628,10 +628,10 @@ ; X64-RETPOLINE-NEXT: movq %rsp, %rcx ; X64-RETPOLINE-NEXT: movq $-1, %rax ; X64-RETPOLINE-NEXT: sarq $63, %rcx -; X64-RETPOLINE-NEXT: cmpl $1, %edi -; X64-RETPOLINE-NEXT: jg .LBB7_4 +; X64-RETPOLINE-NEXT: cmpl $2, %edi +; X64-RETPOLINE-NEXT: jge .LBB7_4 ; X64-RETPOLINE-NEXT: # %bb.1: # %entry -; X64-RETPOLINE-NEXT: cmovgq %rax, %rcx +; X64-RETPOLINE-NEXT: cmovgeq %rax, %rcx ; X64-RETPOLINE-NEXT: testl %edi, %edi ; X64-RETPOLINE-NEXT: je .LBB7_7 ; X64-RETPOLINE-NEXT: # %bb.2: # %entry @@ -645,8 +645,7 @@ ; X64-RETPOLINE-NEXT: orq %rcx, %rsp ; X64-RETPOLINE-NEXT: retq ; X64-RETPOLINE-NEXT: .LBB7_4: # %entry -; X64-RETPOLINE-NEXT: cmovleq %rax, %rcx -; X64-RETPOLINE-NEXT: cmpl $2, %edi +; X64-RETPOLINE-NEXT: cmovlq %rax, %rcx ; X64-RETPOLINE-NEXT: je .LBB7_8 ; X64-RETPOLINE-NEXT: # %bb.5: # %entry ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx @@ -813,10 +812,10 @@ ; X64-RETPOLINE-NEXT: movq $-1, %r10 ; X64-RETPOLINE-NEXT: sarq $63, %r9 ; X64-RETPOLINE-NEXT: xorl %eax, %eax -; X64-RETPOLINE-NEXT: cmpl $1, %edi -; X64-RETPOLINE-NEXT: jg .LBB8_5 +; X64-RETPOLINE-NEXT: cmpl $2, %edi +; X64-RETPOLINE-NEXT: jge .LBB8_5 ; X64-RETPOLINE-NEXT: # %bb.1: # %entry -; X64-RETPOLINE-NEXT: cmovgq %r10, %r9 +; X64-RETPOLINE-NEXT: cmovgeq %r10, %r9 ; X64-RETPOLINE-NEXT: testl %edi, %edi ; X64-RETPOLINE-NEXT: je .LBB8_2 ; X64-RETPOLINE-NEXT: # %bb.3: # %entry @@ -827,8 +826,7 @@ ; X64-RETPOLINE-NEXT: cmovneq %r10, %r9 ; X64-RETPOLINE-NEXT: jmp .LBB8_10 ; X64-RETPOLINE-NEXT: .LBB8_5: # %entry -; X64-RETPOLINE-NEXT: cmovleq %r10, %r9 -; X64-RETPOLINE-NEXT: cmpl $2, %edi +; X64-RETPOLINE-NEXT: cmovlq %r10, %r9 ; X64-RETPOLINE-NEXT: je .LBB8_6 ; X64-RETPOLINE-NEXT: # %bb.7: # %entry ; X64-RETPOLINE-NEXT: cmoveq %r10, %r9 diff --git a/llvm/test/CodeGen/X86/statepoint-ra.ll b/llvm/test/CodeGen/X86/statepoint-ra.ll --- a/llvm/test/CodeGen/X86/statepoint-ra.ll +++ b/llvm/test/CodeGen/X86/statepoint-ra.ll @@ -95,7 +95,7 @@ ;CHECK: MOVSDmr %stack.2, 1, $noreg, 0, $noreg, %45 :: (store (s64) into %stack.2) ;CHECK: MOVSDmr %stack.5, 1, $noreg, 0, $noreg, %58 :: (store (s64) into %stack.5) ;CHECK: MOVSDmr %stack.6, 1, $noreg, 0, $noreg, %62 :: (store (s64) into %stack.6) -;CHECK: JCC_1 %bb.2, 4, implicit killed $eflags +;CHECK: JCC_1 %bb.2, 5, implicit killed $eflags ;CHECK: bb.1: ;CHECK: successors: %bb.3(0x80000000) ;CHECK: %54:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s64) from constant-pool) diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll --- a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll +++ b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll @@ -216,8 +216,8 @@ ; CHECK-VREG-NEXT: %5:gr8 = COPY $al ; CHECK-VREG-NEXT: %3:gr8 = COPY %5 ; CHECK-VREG-NEXT: TEST8ri killed %4, 1, implicit-def $eflags -; CHECK-VREG-NEXT: JCC_1 %bb.2, 4, implicit $eflags -; CHECK-VREG-NEXT: JMP_1 %bb.1 +; CHECK-VREG-NEXT: JCC_1 %bb.1, 5, implicit $eflags +; CHECK-VREG-NEXT: JMP_1 %bb.2 ; CHECK-VREG: bb.1.left: ; CHECK-VREG-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ; CHECK-VREG-NEXT: $rdi = COPY %2 diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll b/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll --- a/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll +++ b/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll @@ -49,8 +49,8 @@ ; CHECK: renamable $rbp = COPY $rdx ; CHECK: renamable $r14d = COPY $edi ; CHECK: TEST8ri renamable $r14b, 1, implicit-def $eflags -; CHECK: JCC_1 %bb.3, 4, implicit killed $eflags -; CHECK: JMP_1 %bb.1 +; CHECK: JCC_1 %bb.1, 5, implicit killed $eflags +; CHECK: JMP_1 %bb.3 ; CHECK: bb.1.left: ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, renamable $rsi :: (store (s64) into %stack.0) ; CHECK: $rdi = COPY killed renamable $rsi diff --git a/llvm/test/CodeGen/X86/switch-bt.ll b/llvm/test/CodeGen/X86/switch-bt.ll --- a/llvm/test/CodeGen/X86/switch-bt.ll +++ b/llvm/test/CodeGen/X86/switch-bt.ll @@ -140,15 +140,15 @@ ; The balanced binary switch here would start with a comparison against 39, but ; it is currently starting with 29 because of the density-sum heuristic. -; CHECK: cmpl $39 -; CHECK: jg +; CHECK: cmpl $40 +; CHECK: jge ; CHECK: cmpl $10 ; CHECK: je ; CHECK: cmpl $20 ; CHECK: je ; CHECK: cmpl $30 ; CHECK: jne -; CHECK: cmpl $40 +; CHECK: .LBB{{.*}} ; CHECK: je ; CHECK: cmpl $50 ; CHECK: je diff --git a/llvm/test/CodeGen/X86/switch-density.ll b/llvm/test/CodeGen/X86/switch-density.ll --- a/llvm/test/CodeGen/X86/switch-density.ll +++ b/llvm/test/CodeGen/X86/switch-density.ll @@ -19,10 +19,9 @@ ; Should pivot around 400 for two subtrees with two jump tables each. ; CHECK-LABEL: sparse ; CHECK-NOT: cmpl -; CHECK: cmpl $399 +; CHECK: cmpl $400 ; CHECK: cmpl $100 ; CHECK: cmpl $300 -; CHECK: cmpl $400 ; CHECK: cmpl $500 } @@ -48,7 +47,7 @@ ; SPARSE: ja ; SPARSE: jmpq *.LJTI ; DENSE-NOT: cmpl -; DENSE: cmpl $29 +; DENSE: cmpl $30 ; DENSE-DAG: cmpl $10 ; DENSE-DAG: cmpl $20 ; DENSE-DAG: cmpl $30 @@ -97,7 +96,7 @@ ; Lowered as branches. ; CHECK-LABEL: dense_optsize -; CHECK: cmpl $11 +; CHECK: cmpl $12 ; CHECK: cmpl $20 ; CHECK: cmpl $16 ; CHECK: cmpl $12 @@ -123,7 +122,7 @@ ; Lowered as branches. ; CHECK-LABEL: dense_pgso -; CHECK: cmpl $11 +; CHECK: cmpl $12 ; CHECK: cmpl $20 ; CHECK: cmpl $16 ; CHECK: cmpl $12 diff --git a/llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll b/llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll --- a/llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll +++ b/llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll @@ -17,9 +17,9 @@ ; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]] ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: successors: %[[BB1_LABEL:.*]](0x0206d3a0), %[[BB2_LABEL:.*]](0x7df92c60) -; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18311, implicit-def $eflags -; CHECK: JCC_1 %[[BB2_LABEL]], 15, implicit $eflags -; CHECK: JMP_1 %[[BB1_LABEL]] +; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18312, implicit-def $eflags +; CHECK: JCC_1 %[[BB1_LABEL]], 12, implicit $eflags +; CHECK: JMP_1 %[[BB2_LABEL]] ; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: successors: %[[CASE2_LABEL:.*]](0x35e50d5b), %[[BB3_LABEL:.*]](0x4a1af2a5) ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], -8826, implicit-def $eflags @@ -80,9 +80,9 @@ ; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]] ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: successors: %[[BB1_LABEL:.*]](0x0088888a), %[[BB2_LABEL:.*]](0x7f777776) -; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 4, implicit-def $eflags -; CHECK: JCC_1 %[[BB2_LABEL]], 15, implicit $eflags -; CHECK: JMP_1 %[[BB1_LABEL]] +; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 5, implicit-def $eflags +; CHECK: JCC_1 %[[BB1_LABEL]], 12, implicit $eflags +; CHECK: JMP_1 %[[BB2_LABEL]] ; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}: ; CHECK: successors: %[[CASE4_LABEL:.*]](0x7f775a4f), %[[BB3_LABEL:.*]](0x0088a5b1) ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 1, implicit-def $eflags diff --git a/llvm/test/CodeGen/X86/switch.ll b/llvm/test/CodeGen/X86/switch.ll --- a/llvm/test/CodeGen/X86/switch.ll +++ b/llvm/test/CodeGen/X86/switch.ll @@ -95,8 +95,8 @@ ; CHECK: leal -100 ; CHECK: cmpl $4 ; CHECK: jb -; CHECK: cmpl $3 -; CHECK: ja +; CHECK: cmpl $4 +; CHECK: jae ; We do this even at -O0, because it's cheap and makes codegen faster. ; NOOPT-LABEL: simple_ranges @@ -259,7 +259,7 @@ ; Should pivot around 400 for two subtrees of equal size. ; CHECK-LABEL: optimal_pivot1 ; CHECK-NOT: cmpl -; CHECK: cmpl $399 +; CHECK: cmpl $400 } @@ -281,7 +281,7 @@ ; Should pivot around 300 for two subtrees with two jump tables each. ; CHECK-LABEL: optimal_pivot2 ; CHECK-NOT: cmpl -; CHECK: cmpl $299 +; CHECK: cmpl $300 ; CHECK: jmpq *.LJTI ; CHECK: jmpq *.LJTI ; CHECK: jmpq *.LJTI @@ -599,7 +599,7 @@ ; Make sure to pick a pivot in the middle also with zero-weight cases. ; CHECK-LABEL: zero_weight_tree ; CHECK-NOT: cmpl -; CHECK: cmpl $29 +; CHECK: cmpl $30 } !3 = !{!"branch_weights", i32 1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 10} @@ -634,7 +634,7 @@ ; CHECK-LABEL: left_leaning_weight_balanced_tree ; CHECK-NOT: cmpl -; CHECK: cmpl $49 +; CHECK: cmpl $50 } !4 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1000} @@ -668,7 +668,7 @@ ; CHECK-LABEL: left_leaning_weight_balanced_tree2 ; CHECK-NOT: cmpl -; CHECK: cmpl $59 +; CHECK: cmpl $60 } !5 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 1, i32 90, i32 70, i32 1000} @@ -700,7 +700,7 @@ ; CHECK-LABEL: right_leaning_weight_balanced_tree ; CHECK-NOT: cmpl -; CHECK: cmpl $19 +; CHECK: cmpl $20 } !6 = !{!"branch_weights", i32 1, i32 1000, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 10} @@ -730,7 +730,7 @@ ; the left and {200,300} on the right. However, the jump table weights as much ; as its components, so 100 is selected as the pivot. ; CHECK-NOT: cmpl -; CHECK: cmpl $99 +; CHECK: cmpl $100 } diff --git a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll --- a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll +++ b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll @@ -14,8 +14,8 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.arg1) ; CHECK: [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[MOV64rm]], [[COPY]], implicit-def $eflags - ; CHECK: JCC_1 %bb.2, 4, implicit $eflags - ; CHECK: JMP_1 %bb.1 + ; CHECK: JCC_1 %bb.1, 5, implicit $eflags + ; CHECK: JMP_1 %bb.2 ; CHECK: bb.1.bb100: ; CHECK: successors: %bb.3(0x80000000) ; CHECK: MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg1) diff --git a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll --- a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll +++ b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll @@ -98,7 +98,7 @@ ; CHECK-NEXT: movl $1, %ebx ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_27 +; CHECK-NEXT: je .LBB1_27 ; CHECK-NEXT: # %bb.1: # %if.end19 ; CHECK-NEXT: movl %esi, %r13d ; CHECK-NEXT: movq %rdi, %r12 @@ -125,8 +125,8 @@ ; CHECK-NEXT: movq %rbx, %rdi ; CHECK-NEXT: movq %r15, %rdx ; CHECK-NEXT: callq memcpy@PLT -; CHECK-NEXT: cmpl $4, %r14d -; CHECK-NEXT: jb .LBB1_29 +; CHECK-NEXT: cmpl $3, %r14d +; CHECK-NEXT: jbe .LBB1_29 ; CHECK-NEXT: # %bb.6: # %shared_preheader ; CHECK-NEXT: movb $32, %dl ; CHECK-NEXT: xorl %eax, %eax @@ -160,15 +160,15 @@ ; CHECK-NEXT: jns .LBB1_10 ; CHECK-NEXT: # %bb.12: # %if.end96.i ; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1 -; CHECK-NEXT: cmpl $3, %ebp -; CHECK-NEXT: jae .LBB1_23 +; CHECK-NEXT: cmpl $2, %ebp +; CHECK-NEXT: ja .LBB1_23 ; CHECK-NEXT: # %bb.13: # %if.end287.i ; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1 ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: cmpl $1, %ebp ; CHECK-NEXT: setne %dl ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_17 +; CHECK-NEXT: je .LBB1_17 ; CHECK-NEXT: # %bb.14: # %if.end308.i ; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1 ; CHECK-NEXT: testb %al, %al diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll --- a/llvm/test/CodeGen/X86/tail-opts.ll +++ b/llvm/test/CodeGen/X86/tail-opts.ll @@ -247,7 +247,7 @@ ; CHECK-NEXT: movb 0, %bl ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB3_8 +; CHECK-NEXT: je .LBB3_8 ; CHECK-NEXT: # %bb.2: # %bb.i ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al diff --git a/llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll b/llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll --- a/llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll +++ b/llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll @@ -19,8 +19,8 @@ ; SSE-NEXT: # %bb.1: # %for.body.preheader ; SSE-NEXT: movl %ecx, %r9d ; SSE-NEXT: movl %edx, %eax -; SSE-NEXT: cmpl $31, %edx -; SSE-NEXT: ja .LBB0_3 +; SSE-NEXT: cmpl $32, %edx +; SSE-NEXT: jae .LBB0_3 ; SSE-NEXT: # %bb.2: ; SSE-NEXT: xorl %edx, %edx ; SSE-NEXT: jmp .LBB0_6 @@ -144,8 +144,8 @@ ; AVX1-NEXT: # %bb.1: # %for.body.preheader ; AVX1-NEXT: movl %ecx, %r9d ; AVX1-NEXT: movl %edx, %eax -; AVX1-NEXT: cmpl $31, %edx -; AVX1-NEXT: ja .LBB0_3 +; AVX1-NEXT: cmpl $32, %edx +; AVX1-NEXT: jae .LBB0_3 ; AVX1-NEXT: # %bb.2: ; AVX1-NEXT: xorl %edx, %edx ; AVX1-NEXT: jmp .LBB0_6 @@ -269,8 +269,8 @@ ; AVX2-NEXT: # %bb.1: # %for.body.preheader ; AVX2-NEXT: movl %ecx, %r9d ; AVX2-NEXT: movl %edx, %eax -; AVX2-NEXT: cmpl $31, %edx -; AVX2-NEXT: ja .LBB0_3 +; AVX2-NEXT: cmpl $32, %edx +; AVX2-NEXT: jae .LBB0_3 ; AVX2-NEXT: # %bb.2: ; AVX2-NEXT: xorl %edx, %edx ; AVX2-NEXT: jmp .LBB0_6 @@ -344,8 +344,8 @@ ; XOP-NEXT: # %bb.1: # %for.body.preheader ; XOP-NEXT: movl %ecx, %r9d ; XOP-NEXT: movl %edx, %eax -; XOP-NEXT: cmpl $31, %edx -; XOP-NEXT: ja .LBB0_3 +; XOP-NEXT: cmpl $32, %edx +; XOP-NEXT: jae .LBB0_3 ; XOP-NEXT: # %bb.2: ; XOP-NEXT: xorl %edx, %edx ; XOP-NEXT: jmp .LBB0_6 diff --git a/llvm/test/CodeGen/X86/widen_cast-1.ll b/llvm/test/CodeGen/X86/widen_cast-1.ll --- a/llvm/test/CodeGen/X86/widen_cast-1.ll +++ b/llvm/test/CodeGen/X86/widen_cast-1.ll @@ -12,8 +12,8 @@ ; CHECK-NEXT: pushl %eax ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 -; CHECK-NEXT: cmpl $3, (%esp) -; CHECK-NEXT: jg .LBB0_3 +; CHECK-NEXT: cmpl $4, (%esp) +; CHECK-NEXT: jge .LBB0_3 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_2: # %forbody ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 @@ -24,8 +24,8 @@ ; CHECK-NEXT: psubw %xmm0, %xmm1 ; CHECK-NEXT: movq %xmm1, (%ecx,%eax,8) ; CHECK-NEXT: incl (%esp) -; CHECK-NEXT: cmpl $3, (%esp) -; CHECK-NEXT: jle .LBB0_2 +; CHECK-NEXT: cmpl $4, (%esp) +; CHECK-NEXT: jl .LBB0_2 ; CHECK-NEXT: .LBB0_3: # %afterfor ; CHECK-NEXT: popl %eax ; CHECK-NEXT: retl @@ -35,8 +35,8 @@ ; ATOM-NEXT: pushl %eax ; ATOM-NEXT: pcmpeqd %xmm0, %xmm0 ; ATOM-NEXT: movl $0, (%esp) -; ATOM-NEXT: cmpl $3, (%esp) -; ATOM-NEXT: jg .LBB0_3 +; ATOM-NEXT: cmpl $4, (%esp) +; ATOM-NEXT: jge .LBB0_3 ; ATOM-NEXT: .p2align 4, 0x90 ; ATOM-NEXT: .LBB0_2: # %forbody ; ATOM-NEXT: # =>This Inner Loop Header: Depth=1 @@ -47,8 +47,8 @@ ; ATOM-NEXT: psubw %xmm0, %xmm1 ; ATOM-NEXT: movq %xmm1, (%ecx,%eax,8) ; ATOM-NEXT: incl (%esp) -; ATOM-NEXT: cmpl $3, (%esp) -; ATOM-NEXT: jle .LBB0_2 +; ATOM-NEXT: cmpl $4, (%esp) +; ATOM-NEXT: jl .LBB0_2 ; ATOM-NEXT: .LBB0_3: # %afterfor ; ATOM-NEXT: popl %eax ; ATOM-NEXT: retl diff --git a/llvm/test/CodeGen/X86/widen_cast-2.ll b/llvm/test/CodeGen/X86/widen_cast-2.ll --- a/llvm/test/CodeGen/X86/widen_cast-2.ll +++ b/llvm/test/CodeGen/X86/widen_cast-2.ll @@ -8,8 +8,8 @@ ; CHECK-NEXT: pushl %eax ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 -; CHECK-NEXT: cmpl $3, (%esp) -; CHECK-NEXT: jg .LBB0_3 +; CHECK-NEXT: cmpl $4, (%esp) +; CHECK-NEXT: jge .LBB0_3 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_2: # %forbody ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 @@ -26,8 +26,8 @@ ; CHECK-NEXT: pextrd $1, %xmm2, 20(%ecx,%eax) ; CHECK-NEXT: pextrd $2, %xmm2, 24(%ecx,%eax) ; CHECK-NEXT: incl (%esp) -; CHECK-NEXT: cmpl $3, (%esp) -; CHECK-NEXT: jle .LBB0_2 +; CHECK-NEXT: cmpl $4, (%esp) +; CHECK-NEXT: jl .LBB0_2 ; CHECK-NEXT: .LBB0_3: # %afterfor ; CHECK-NEXT: popl %eax ; CHECK-NEXT: retl diff --git a/llvm/test/CodeGen/X86/x32-va_start.ll b/llvm/test/CodeGen/X86/x32-va_start.ll --- a/llvm/test/CodeGen/X86/x32-va_start.ll +++ b/llvm/test/CodeGen/X86/x32-va_start.ll @@ -50,8 +50,8 @@ ; SSE-NEXT: movabsq $274877906952, %rax # imm = 0x4000000008 ; SSE-NEXT: movq %rax, -{{[0-9]+}}(%esp) ; SSE-NEXT: movl $8, %ecx -; SSE-NEXT: cmpl $40, %ecx -; SSE-NEXT: ja .LBB0_2 +; SSE-NEXT: cmpl $41, %ecx +; SSE-NEXT: jae .LBB0_2 ; SSE-NEXT: # %bb.1: # %vaarg.in_reg ; SSE-NEXT: movl -{{[0-9]+}}(%esp), %eax ; SSE-NEXT: addl %ecx, %eax @@ -81,8 +81,8 @@ ; NOSSE-NEXT: movabsq $206158430216, %rax # imm = 0x3000000008 ; NOSSE-NEXT: movq %rax, -{{[0-9]+}}(%esp) ; NOSSE-NEXT: movl $8, %ecx -; NOSSE-NEXT: cmpl $40, %ecx -; NOSSE-NEXT: ja .LBB0_2 +; NOSSE-NEXT: cmpl $41, %ecx +; NOSSE-NEXT: jae .LBB0_2 ; NOSSE-NEXT: # %bb.1: # %vaarg.in_reg ; NOSSE-NEXT: movl -{{[0-9]+}}(%esp), %eax ; NOSSE-NEXT: addl %ecx, %eax @@ -102,8 +102,8 @@ ; 32BITABI-NEXT: subl $28, %esp ; 32BITABI-NEXT: leal {{[0-9]+}}(%esp), %ecx ; 32BITABI-NEXT: movl %ecx, (%esp) -; 32BITABI-NEXT: cmpl $40, %ecx -; 32BITABI-NEXT: ja .LBB0_2 +; 32BITABI-NEXT: cmpl $41, %ecx +; 32BITABI-NEXT: jae .LBB0_2 ; 32BITABI-NEXT: # %bb.1: # %vaarg.in_reg ; 32BITABI-NEXT: movl {{[0-9]+}}(%esp), %eax ; 32BITABI-NEXT: addl %ecx, %eax diff --git a/llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll b/llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll --- a/llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll +++ b/llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs < %s | FileCheck %s target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i686-pc-windows-msvc18.0.0" @@ -6,6 +7,37 @@ ; Function Attrs: nounwind optsize define void @f(i8* %p, i8* %q, i32* inalloca(i32) nocapture %unused) #0 { +; CHECK-LABEL: f: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushl %ebp +; CHECK-NEXT: movl %esp, %ebp +; CHECK-NEXT: pushl %ebx +; CHECK-NEXT: pushl %edi +; CHECK-NEXT: pushl %esi +; CHECK-NEXT: andl $-8, %esp +; CHECK-NEXT: subl $40, %esp +; CHECK-NEXT: movl 8(%ebp), %edi +; CHECK-NEXT: movl 12(%ebp), %esi +; CHECK-NEXT: movl $0, (%esp) +; CHECK-NEXT: movl $6, %ecx +; CHECK-NEXT: rep;movsl (%esi), %es:(%edi) +; CHECK-NEXT: leal {{[0-9]+}}(%esp), %esi +; CHECK-NEXT: LBB0_1: # %while.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: decl (%esp) +; CHECK-NEXT: sete %bl +; CHECK-NEXT: pushl %esi +; CHECK-NEXT: calll _g +; CHECK-NEXT: addl $4, %esp +; CHECK-NEXT: testb %bl, %bl +; CHECK-NEXT: je LBB0_1 +; CHECK-NEXT: # %bb.2: # %while.end +; CHECK-NEXT: leal -12(%ebp), %esp +; CHECK-NEXT: popl %esi +; CHECK-NEXT: popl %edi +; CHECK-NEXT: popl %ebx +; CHECK-NEXT: popl %ebp +; CHECK-NEXT: retl entry: %g = alloca %struct.T, align 8 %r = alloca i32, align 8 @@ -26,6 +58,37 @@ } define void @f_pgso(i8* %p, i8* %q, i32* inalloca(i32) nocapture %unused) !prof !14 { +; CHECK-LABEL: f_pgso: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushl %ebp +; CHECK-NEXT: movl %esp, %ebp +; CHECK-NEXT: pushl %ebx +; CHECK-NEXT: pushl %edi +; CHECK-NEXT: pushl %esi +; CHECK-NEXT: andl $-8, %esp +; CHECK-NEXT: subl $40, %esp +; CHECK-NEXT: movl 8(%ebp), %edi +; CHECK-NEXT: movl 12(%ebp), %esi +; CHECK-NEXT: movl $0, (%esp) +; CHECK-NEXT: movl $6, %ecx +; CHECK-NEXT: rep;movsl (%esi), %es:(%edi) +; CHECK-NEXT: leal {{[0-9]+}}(%esp), %esi +; CHECK-NEXT: LBB1_1: # %while.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: decl (%esp) +; CHECK-NEXT: sete %bl +; CHECK-NEXT: pushl %esi +; CHECK-NEXT: calll _g +; CHECK-NEXT: addl $4, %esp +; CHECK-NEXT: testb %bl, %bl +; CHECK-NEXT: je LBB1_1 +; CHECK-NEXT: # %bb.2: # %while.end +; CHECK-NEXT: leal -12(%ebp), %esp +; CHECK-NEXT: popl %esi +; CHECK-NEXT: popl %edi +; CHECK-NEXT: popl %ebx +; CHECK-NEXT: popl %ebp +; CHECK-NEXT: retl entry: %g = alloca %struct.T, align 8 %r = alloca i32, align 8 @@ -50,38 +113,6 @@ declare void @g(%struct.T*) -; CHECK-LABEL: _f: -; CHECK: pushl %ebp -; CHECK: movl %esp, %ebp -; CHECK: andl $-8, %esp -; CHECK-NOT: movl %esp, %esi -; CHECK: rep;movsl -; CHECK: leal 8(%esp), %esi - -; CHECK: decl (%esp) -; CHECK: setne %[[NE_REG:.*]] -; CHECK: pushl %esi -; CHECK: calll _g -; CHECK: addl $4, %esp -; CHECK: testb %[[NE_REG]], %[[NE_REG]] -; CHECK: jne - -; CHECK-LABEL: _f_pgso: -; CHECK: pushl %ebp -; CHECK: movl %esp, %ebp -; CHECK: andl $-8, %esp -; CHECK-NOT: movl %esp, %esi -; CHECK: rep;movsl -; CHECK: leal 8(%esp), %esi - -; CHECK: decl (%esp) -; CHECK: setne %[[NE_REG:.*]] -; CHECK: pushl %esi -; CHECK: calll _g -; CHECK: addl $4, %esp -; CHECK: testb %[[NE_REG]], %[[NE_REG]] -; CHECK: jne - attributes #0 = { nounwind optsize } attributes #1 = { argmemonly nounwind } diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll --- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll @@ -819,7 +819,7 @@ ; ENABLE-NEXT: .cfi_offset %rbx, -24 ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: testb %al, %al -; ENABLE-NEXT: jne LBB10_3 +; ENABLE-NEXT: je LBB10_3 ; ENABLE-NEXT: ## %bb.1: ## %if.then ; ENABLE-NEXT: movq %rsp, %rcx ; ENABLE-NEXT: addq $-16, %rcx @@ -851,7 +851,7 @@ ; DISABLE-NEXT: .cfi_offset %rbx, -24 ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: testb %al, %al -; DISABLE-NEXT: jne LBB10_3 +; DISABLE-NEXT: je LBB10_3 ; DISABLE-NEXT: ## %bb.1: ## %if.then ; DISABLE-NEXT: movq %rsp, %rcx ; DISABLE-NEXT: addq $-16, %rcx @@ -902,7 +902,7 @@ ; ENABLE-NEXT: .cfi_offset %rbx, -24 ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: testb %al, %al -; ENABLE-NEXT: jne LBB11_5 +; ENABLE-NEXT: je LBB11_5 ; ENABLE-NEXT: ## %bb.1: ## %if.then ; ENABLE-NEXT: movq %rsp, %rcx ; ENABLE-NEXT: addq $-16, %rcx @@ -925,7 +925,7 @@ ; ENABLE-NEXT: addl %esi, %edx ; ENABLE-NEXT: movl %edx, (%rcx) ; ENABLE-NEXT: testb %al, %al -; ENABLE-NEXT: jne LBB11_4 +; ENABLE-NEXT: je LBB11_4 ; ENABLE-NEXT: ## %bb.3: ## %body1 ; ENABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 ; ENABLE-NEXT: ## InlineAsm Start @@ -950,7 +950,7 @@ ; DISABLE-NEXT: .cfi_offset %rbx, -24 ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: testb %al, %al -; DISABLE-NEXT: jne LBB11_5 +; DISABLE-NEXT: je LBB11_5 ; DISABLE-NEXT: ## %bb.1: ## %if.then ; DISABLE-NEXT: movq %rsp, %rcx ; DISABLE-NEXT: addq $-16, %rcx @@ -973,7 +973,7 @@ ; DISABLE-NEXT: addl %esi, %edx ; DISABLE-NEXT: movl %edx, (%rcx) ; DISABLE-NEXT: testb %al, %al -; DISABLE-NEXT: jne LBB11_4 +; DISABLE-NEXT: je LBB11_4 ; DISABLE-NEXT: ## %bb.3: ## %body1 ; DISABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 ; DISABLE-NEXT: ## InlineAsm Start @@ -1021,7 +1021,7 @@ ; ENABLE-NEXT: ## %bb.1: ## %body ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: testb %al, %al -; ENABLE-NEXT: jne LBB12_7 +; ENABLE-NEXT: je LBB12_7 ; ENABLE-NEXT: LBB12_2: ## %loop2a.preheader ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: xorl %ecx, %ecx @@ -1053,7 +1053,7 @@ ; DISABLE-NEXT: ## %bb.1: ## %body ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: testb %al, %al -; DISABLE-NEXT: jne LBB12_7 +; DISABLE-NEXT: je LBB12_7 ; DISABLE-NEXT: LBB12_2: ## %loop2a.preheader ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: xorl %ecx, %ecx diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll --- a/llvm/test/CodeGen/X86/xmulo.ll +++ b/llvm/test/CodeGen/X86/xmulo.ll @@ -1347,8 +1347,8 @@ ; WIN32-NEXT: setb %al ; WIN32-NEXT: orb %cl, %al ; WIN32-NEXT: orb %bl, %al -; WIN32-NEXT: subb $1, %al -; WIN32-NEXT: je LBB22_1 +; WIN32-NEXT: testb %al, %al +; WIN32-NEXT: jne LBB22_1 ; WIN32-NEXT: # %bb.3: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: LBB22_2: # %overflow diff --git a/llvm/test/CodeGen/X86/xor-combine-debugloc.ll b/llvm/test/CodeGen/X86/xor-combine-debugloc.ll --- a/llvm/test/CodeGen/X86/xor-combine-debugloc.ll +++ b/llvm/test/CodeGen/X86/xor-combine-debugloc.ll @@ -10,7 +10,7 @@ ; CHECK-DAG: [[VREG1:%[^ ]+]]:gr32 = COPY $esi ; CHECK-DAG: [[VREG2:%[^ ]+]]:gr32 = COPY $edi ; CHECK: SUB32rr [[VREG2]], [[VREG1]], implicit-def $eflags, debug-location [[DLOC1]] -; CHECK-NEXT: JCC_1{{.*}} 4, implicit $eflags, debug-location [[DLOC2]] +; CHECK-NEXT: JCC_1{{.*}} {{.*}}, implicit $eflags, debug-location [[DLOC2]] ; CHECK-NEXT: JMP_1{{.*}} debug-location [[DLOC2]] target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/xor-icmp.ll b/llvm/test/CodeGen/X86/xor-icmp.ll --- a/llvm/test/CodeGen/X86/xor-icmp.ll +++ b/llvm/test/CodeGen/X86/xor-icmp.ll @@ -53,7 +53,7 @@ ; X86-NEXT: sete %al ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: sete %cl -; X86-NEXT: cmpb %al, %cl +; X86-NEXT: xorb %al, %cl ; X86-NEXT: je .LBB1_1 ; X86-NEXT: # %bb.2: # %bb ; X86-NEXT: jmp foo # TAILCALL @@ -66,7 +66,7 @@ ; X64-NEXT: sete %al ; X64-NEXT: testl %esi, %esi ; X64-NEXT: sete %cl -; X64-NEXT: cmpb %al, %cl +; X64-NEXT: xorb %al, %cl ; X64-NEXT: je .LBB1_1 ; X64-NEXT: # %bb.2: # %bb ; X64-NEXT: xorl %eax, %eax diff --git a/llvm/test/CodeGen/XCore/threads.ll b/llvm/test/CodeGen/XCore/threads.ll --- a/llvm/test/CodeGen/XCore/threads.ll +++ b/llvm/test/CodeGen/XCore/threads.ll @@ -123,8 +123,8 @@ define void @phiNode2( i1 %bool) { ; N.B. check an extra 'Node_crit_edge' (LBB12_1) is inserted ; PHINODE-LABEL: phiNode2: -; PHINODE: bf {{r[0-9]}}, .LBB12_3 -; PHINODE: bu .LBB12_1 +; PHINODE: bt {{r[0-9]}}, .LBB12_1 +; PHINODE: bu .LBB12_3 ; PHINODE-LABEL: .LBB12_1: ; PHINODE: get r11, id ; PHINODE-LABEL: .LBB12_2: