diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -74,8 +74,8 @@ BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "") BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "") BUILTIN(__builtin_ppc_lwarx, "iiD*", "") -BUILTIN(__builtin_ppc_lharx, "isD*", "") -BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "") +BUILTIN(__builtin_ppc_lharx, "ssD*", "") +BUILTIN(__builtin_ppc_lbarx, "ccD*", "") BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "") BUILTIN(__builtin_ppc_stwcx, "iiD*i", "") BUILTIN(__builtin_ppc_sthcx, "isD*s", "") diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c --- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c +++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c @@ -24,7 +24,7 @@ return __lharx(a); } -char test_lbarx(volatile unsigned char *a) { +char test_lbarx(volatile char *a) { // CHECK-LABEL: @test_lbarx // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* %a) // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs @@ -46,3 +46,18 @@ // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs return __sthcx(a, val); } + +// Extra test cases that previously caused error during usage. +int test_lharx_intret(volatile short *a) { + // CHECK-LABEL: @test_lharx_intret + // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", "=r,*Z,~{memory}"(i16* %a) + // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs + return __lharx(a); +} + +int test_lbarx_intret(volatile char *a) { + // CHECK-LABEL: @test_lbarx_intret + // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* %a) + // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs + return __lbarx(a); +}