Index: clang/lib/Basic/Targets/AArch64.h =================================================================== --- clang/lib/Basic/Targets/AArch64.h +++ clang/lib/Basic/Targets/AArch64.h @@ -59,6 +59,7 @@ static const Builtin::Info BuiltinInfo[]; std::string ABI; + StringRef getArchProfile() const; public: AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); Index: clang/lib/Basic/Targets/AArch64.cpp =================================================================== --- clang/lib/Basic/Targets/AArch64.cpp +++ clang/lib/Basic/Targets/AArch64.cpp @@ -51,6 +51,15 @@ } } +StringRef AArch64TargetInfo::getArchProfile() const { + switch (ArchKind) { + case llvm::AArch64::ArchKind::ARMV8R: + return "R"; + default: + return "A"; + } +} + AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : TargetInfo(Triple), ABI("aapcs") { @@ -257,7 +266,7 @@ // ACLE predefines. Many can only have one possible value on v8 AArch64. Builder.defineMacro("__ARM_ACLE", "200"); Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind)); - Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); + Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + getArchProfile() + "'"); Builder.defineMacro("__ARM_64BIT_STATE", "1"); Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); @@ -512,7 +521,7 @@ HasMatmulFP32 = false; HasLSE = false; - ArchKind = llvm::AArch64::ArchKind::ARMV8A; + ArchKind = llvm::AArch64::ArchKind::INVALID; for (const auto &Feature : Features) { if (Feature == "+neon") @@ -574,6 +583,8 @@ HasSM4 = true; if (Feature == "+strict-align") HasUnaligned = false; + if (Feature == "+v8a") + ArchKind = llvm::AArch64::ArchKind::ARMV8A; if (Feature == "+v8.1a") ArchKind = llvm::AArch64::ArchKind::ARMV8_1A; if (Feature == "+v8.2a") Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp =================================================================== --- clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -213,6 +213,9 @@ else if (Args.hasArg(options::OPT_arch) || isCPUDeterminedByTriple(Triple)) success = getAArch64ArchFeaturesFromMcpu( D, getAArch64TargetCPU(Args, Triple, A), Args, Features); + else + // Default to 'A' profile if the architecture is not specified. + success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Features); if (success && (A = Args.getLastArg(clang::driver::options::OPT_mtune_EQ))) success = Index: clang/test/Driver/aarch64-cpus.c =================================================================== --- clang/test/Driver/aarch64-cpus.c +++ clang/test/Driver/aarch64-cpus.c @@ -490,6 +490,13 @@ // MCPU-MTUNE-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "thunderx2t99" // MCPU-MTUNE-THUNDERX3T110: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "thunderx3t110" +// RUN: %clang -target aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=GENERIC-V8A %s +// RUN: %clang -target aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERIC-V8A %s +// GENERIC-V8A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8a" + +// RUN: %clang -target aarch64 -march=armv8-r -### -c %s 2>&1 | FileCheck -check-prefix=GENERIC-V8R %s +// GENERIC-V8R: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8r" + // RUN: %clang -target aarch64 -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s // RUN: %clang -target aarch64 -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s // RUN: %clang -target aarch64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s Index: clang/test/Preprocessor/aarch64-target-features.c =================================================================== --- clang/test/Preprocessor/aarch64-target-features.c +++ clang/test/Preprocessor/aarch64-target-features.c @@ -57,6 +57,15 @@ // CHECK-NOT: __ARM_FEATURE_SVE_BITS 1024 // CHECK-NOT: __ARM_FEATURE_SVE_BITS 2048 +// RUN: %clang -target aarch64-arm-eabi -march=armv8-r -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-R-PROFILE +// RUN: %clang -target arm64-none-linux-gnu -march=armv8-r -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-R-PROFILE +// CHECK-R-PROFILE: __ARM_ARCH_PROFILE 'R' + +// RUN: %clang -target aarch64-arm-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-A-PROFILE +// RUN: %clang -target aarch64-arm-eabi -march=armv8-a -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-A-PROFILE +// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-A-PROFILE +// CHECK-A-PROFILE: __ARM_ARCH_PROFILE 'A' + // RUN: %clang -target aarch64_be-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-BIGENDIAN // CHECK-BIGENDIAN: __ARM_BIG_ENDIAN 1 @@ -239,7 +248,7 @@ // ================== Check whether -mtune accepts mixed-case features. // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MTUNE-CYCLONE %s -// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+zcm" "-target-feature" "+zcz" +// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+v8a" "-target-feature" "+zcm" "-target-feature" "+zcz" // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A7 %s // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A7 %s @@ -258,28 +267,28 @@ // RUN: %clang -target aarch64 -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A72 %s // RUN: %clang -target aarch64 -mcpu=cortex-a73 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CORTEX-A73 %s // RUN: %clang -target aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CORTEX-R82 %s -// RUN: %clang -target aarch64 -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M1 %s +// RUN: %clang -target aarch64 -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M3 %s // RUN: %clang -target aarch64 -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M4 %s // RUN: %clang -target aarch64 -mcpu=exynos-m5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M4 %s // RUN: %clang -target aarch64 -mcpu=kryo -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-KRYO %s // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-THUNDERX2T99 %s // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A64FX %s // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CARMEL %s -// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crypto" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes" +// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crypto" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes" // CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+rdm" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes" // CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes" // CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.3a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes" // CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" // CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.4a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+fp16fml" "-target-feature" "+sm4" "-target-feature" "+sha3" "-target-feature" "+sha2" "-target-feature" "+aes" -// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" -// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" -// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" -// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" -// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" +// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" +// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" +// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" +// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" +// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16" -// CHECK-MCPU-M1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" +// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fullfp16" -// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" +// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-A64FX: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+sve" "-target-feature" "+sha2" // CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+aes" @@ -360,7 +369,7 @@ // RUN: %clang -target aarch64 -march=armv8.3a+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO82 %s // RUN: %clang -target aarch64 -march=armv8.3a+nocrypto+crypto+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO82 %s -// CHECK-NOCRYPTO8A: "-target-feature" "+neon" "-target-feature" "-crypto" "-target-feature" "-sha2" "-target-feature" "-aes" "-target-abi" "aapcs" +// CHECK-NOCRYPTO8A: "-target-feature" "+neon" "-target-feature" "+v8a" "-target-feature" "-crypto" "-target-feature" "-sha2" "-target-feature" "-aes" "-target-abi" "aapcs" // CHECK-NOCRYPTO81: "-target-feature" "+neon" "-target-feature" "+v8.1a" "-target-feature" "-crypto" "-target-feature" "-sha2" "-target-feature" "-aes" "-target-abi" "aapcs" // CHECK-NOCRYPTO82: "-target-feature" "+neon" "-target-feature" "+v8.{{.}}a" "-target-feature" "-crypto" "-target-feature" "-sha2" "-target-feature" "-aes" "-target-feature" "-sm4" "-target-feature" "-sha3" "-target-abi" "aapcs" // @@ -411,7 +420,7 @@ // RUN: %clang -target aarch64 -mcpu=cyclone+nocrc+nocrypto -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MARCH %s // RUN: %clang -target aarch64 -march=armv8-a -mcpu=cyclone+nocrc+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MARCH %s -// CHECK-MCPU-MARCH: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+zcm" "-target-feature" "+zcz" +// CHECK-MCPU-MARCH: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+v8a" "-target-feature" "+zcm" "-target-feature" "+zcz" // RUN: %clang -target aarch64 -mcpu=cortex-a53 -mtune=cyclone -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MTUNE %s // RUN: %clang -target aarch64 -mtune=cyclone -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MTUNE %s Index: llvm/lib/Support/AArch64TargetParser.cpp =================================================================== --- llvm/lib/Support/AArch64TargetParser.cpp +++ llvm/lib/Support/AArch64TargetParser.cpp @@ -120,6 +120,8 @@ bool AArch64::getArchFeatures(AArch64::ArchKind AK, std::vector &Features) { + if (AK == ArchKind::ARMV8A) + Features.push_back("+v8a"); if (AK == ArchKind::ARMV8_1A) Features.push_back("+v8.1a"); if (AK == ArchKind::ARMV8_2A) Index: llvm/lib/Target/AArch64/AArch64.td =================================================================== --- llvm/lib/Target/AArch64/AArch64.td +++ llvm/lib/Target/AArch64/AArch64.td @@ -446,13 +446,21 @@ def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true", "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>; +def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", + "Enable Exception Level 2 Virtual Memory System Architecture">; + +def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", + "Enable Exception Level 3">; + //===----------------------------------------------------------------------===// // Architectures. // +def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", + "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", - "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM, - FeaturePAN, FeatureLOR, FeatureVH]>; + "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, + FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, @@ -599,6 +607,7 @@ def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", "Cortex-A35 ARM processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureFPARMv8, @@ -608,6 +617,7 @@ def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", [ + HasV8_0aOps, FeatureBalanceFPOps, FeatureCRC, FeatureCrypto, @@ -652,6 +662,7 @@ def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", [ + HasV8_0aOps, FeatureBalanceFPOps, FeatureCRC, FeatureCrypto, @@ -683,6 +694,7 @@ def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", "Cortex-A72 ARM processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureFPARMv8, @@ -694,6 +706,7 @@ def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", "Cortex-A73 ARM processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureFPARMv8, @@ -828,6 +841,7 @@ // perform the fusion and cyclone is used by default when targetting apple OSes. def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", "Apple A7 (the CPU formerly known as Cyclone)", [ + HasV8_0aOps, FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, @@ -954,7 +968,8 @@ def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", "Samsung Exynos-M3 processors", - [FeatureCRC, + [HasV8_0aOps, + FeatureCRC, FeatureCrypto, FeatureExynosCheapAsMoveHandling, FeatureForce32BitJumpTables, @@ -989,6 +1004,7 @@ def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", "Qualcomm Kryo processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureCustomCheapAsMoveHandling, @@ -1003,6 +1019,7 @@ def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", "Qualcomm Falkor processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureCustomCheapAsMoveHandling, @@ -1132,6 +1149,7 @@ def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", "Cavium ThunderX processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureFPARMv8, @@ -1143,6 +1161,7 @@ def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", "ThunderXT88", "Cavium ThunderX processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureFPARMv8, @@ -1154,6 +1173,7 @@ def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", "ThunderXT81", "Cavium ThunderX processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureFPARMv8, @@ -1165,6 +1185,7 @@ def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", "ThunderXT83", "Cavium ThunderX processors", [ + HasV8_0aOps, FeatureCRC, FeatureCrypto, FeatureFPARMv8, Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -33,6 +33,15 @@ AssemblerPredicate<(all_of HasV9_1aOps), "armv9.1a">; def HasV9_2a : Predicate<"Subtarget->hasV9_2aOps()">, AssemblerPredicate<(all_of HasV9_2aOps), "armv9.2a">; +def HasV8_0r : Predicate<"Subtarget->hasV8_0rOps()">, + AssemblerPredicate<(all_of HasV8_0rOps), "armv8-r">; + +def HasEL2VMSA : Predicate<"Subtarget->hasEL2VMSA()">, + AssemblerPredicate<(all_of FeatureEL2VMSA), "el2vmsa">; + +def HasEL3 : Predicate<"Subtarget->hasEL3()">, + AssemblerPredicate<(all_of FeatureEL3), "el3">; + def HasVH : Predicate<"Subtarget->hasVH()">, AssemblerPredicate<(all_of FeatureVH), "vh">; @@ -1306,6 +1315,7 @@ def : InstAlias<"isb", (ISB 0xf)>; def : InstAlias<"ssbb", (DSB 0)>; def : InstAlias<"pssbb", (DSB 4)>; +def : InstAlias<"dfb", (DSB 0b1100)>, Requires<[HasV8_0r]>; def MRS : MRSI; def MSR : MSRI; @@ -2368,16 +2378,16 @@ } def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">; def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">; -def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">; +def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">, Requires<[HasEL3]>; def HLT : ExceptionGeneration<0b010, 0b00, "hlt">; def HVC : ExceptionGeneration<0b000, 0b10, "hvc">; -def SMC : ExceptionGeneration<0b000, 0b11, "smc">; +def SMC : ExceptionGeneration<0b000, 0b11, "smc">, Requires<[HasEL3]>; def SVC : ExceptionGeneration<0b000, 0b01, "svc">; // DCPSn defaults to an immediate operand of zero if unspecified. def : InstAlias<"dcps1", (DCPS1 0)>; def : InstAlias<"dcps2", (DCPS2 0)>; -def : InstAlias<"dcps3", (DCPS3 0)>; +def : InstAlias<"dcps3", (DCPS3 0)>, Requires<[HasEL3]>; def UDF : UDFType<0, "udf">; Index: llvm/lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- llvm/lib/Target/AArch64/AArch64Subtarget.h +++ llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -83,6 +83,7 @@ /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others. ARMProcFamilyEnum ARMProcFamily = Others; + bool HasV8_0aOps = false; bool HasV8_1aOps = false; bool HasV8_2aOps = false; bool HasV8_3aOps = false; @@ -93,10 +94,11 @@ bool HasV9_0aOps = false; bool HasV9_1aOps = false; bool HasV9_2aOps = false; - bool HasV8_0rOps = false; - bool HasCONTEXTIDREL2 = false; + bool HasCONTEXTIDREL2 = false; + bool HasEL2VMSA = false; + bool HasEL3 = false; bool HasFPARMv8 = false; bool HasNEON = false; bool HasCrypto = false; @@ -344,6 +346,7 @@ return ARMProcFamily; } + bool hasV8_0aOps() const { return HasV8_0aOps; } bool hasV8_1aOps() const { return HasV8_1aOps; } bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; } @@ -557,6 +560,8 @@ bool hasTLB_RMI() const { return HasTLB_RMI; } bool hasFlagM() const { return HasFlagM; } bool hasRCPC_IMMO() const { return HasRCPC_IMMO; } + bool hasEL2VMSA() const { return HasEL2VMSA; } + bool hasEL3() const { return HasEL3; } bool addrSinkUsingGEPs() const override { // Keeping GEPs inbounds is important for exploiting AArch64 Index: llvm/lib/Target/AArch64/AArch64SystemOperands.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -586,6 +586,7 @@ let EnumValueField = "Encoding"; string Name = name; + string AltName = name; bits<16> Encoding; let Encoding{15-14} = op0; let Encoding{13-11} = op1; @@ -912,13 +913,19 @@ def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>; def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>; def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>; -def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>; def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>; + +let Requires = [{ {AArch64::FeatureEL2VMSA} }] in { +def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000> { + let AltName = "VSCTLR_EL2"; +} +def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>; +} + def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>; def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>; def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>; def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>; -def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>; def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>; def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>; def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>; @@ -1293,6 +1300,57 @@ def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>; def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>; +// v8r system registers +let Requires = [{ {AArch64::HasV8_0rOps} }] in { +//Virtualization System Control Register +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"VSCTLR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000> { + let AltName = "TTBR0_EL2"; +} + +//MPU Type Register +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"MPUIR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b100>; +def : RWSysReg<"MPUIR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b100>; + +//Protection Region Enable Register +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"PRENR_EL1", 0b11, 0b000, 0b0110, 0b0001, 0b001>; +def : RWSysReg<"PRENR_EL2", 0b11, 0b100, 0b0110, 0b0001, 0b001>; + +//Protection Region Selection Register +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"PRSELR_EL1", 0b11, 0b000, 0b0110, 0b0010, 0b001>; +def : RWSysReg<"PRSELR_EL2", 0b11, 0b100, 0b0110, 0b0010, 0b001>; + +//Protection Region Base Address Register +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"PRBAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b000>; +def : RWSysReg<"PRBAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b000>; + +//Protection Region Limit Address Register +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"PRLAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b001>; +def : RWSysReg<"PRLAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b001>; + +foreach n = 0-15 in { +foreach x = 1-2 in { +//Direct acces to Protection Region Base Address Register for n th MPU region + def : RWSysReg{ + let Encoding{5-2} = n; + let Encoding{13} = !add(x,-1); + } + + def : RWSysReg{ + let Encoding{5-2} = n; + let Encoding{13} = !add(x,-1); + } +} //foreach x = 1-2 in +} //foreach n = 0-15 in +} //let Requires = [{ {AArch64::HasV8_0rOps} }] in + // v8.1a "Privileged Access Never" extension-specific system registers let Requires = [{ {AArch64::FeaturePAN} }] in def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>; @@ -1396,7 +1454,9 @@ // v8.4a "Virtualization secure second stage translation" registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>; -def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000>; +def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000> { + let Requires = [{ {AArch64::HasV8_0aOps} }]; +} // v8.4a "Virtualization timer" registers // Op0 Op1 CRn CRm Op2 Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3296,6 +3296,8 @@ }; static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) { + if (FBS[AArch64::HasV8_0aOps]) + Str += "ARMv8a"; if (FBS[AArch64::HasV8_1aOps]) Str += "ARMv8.1a"; else if (FBS[AArch64::HasV8_2aOps]) @@ -3316,6 +3318,8 @@ Str += "ARMv9.1a"; else if (FBS[AArch64::HasV9_2aOps]) Str += "ARMv9.2a"; + else if (FBS[AArch64::HasV8_0rOps]) + Str += "ARMv8r"; else { SmallVector ExtMatches; for (const auto& Ext : ExtensionMap) { Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -1545,6 +1545,22 @@ O << "#" << Val; } +static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read, + const MCSubtargetInfo &STI) { + return (Reg && (Read ? Reg->Readable : Reg->Writeable) && + Reg->haveFeatures(STI.getFeatureBits())); +} + +static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read, + const MCSubtargetInfo &STI) { + const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); + + if (Reg && !isValidSysReg(Reg, Read, STI)) + Reg = AArch64SysReg::lookupSysRegByName(Reg->AltName); + + return Reg; +} + void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -1564,8 +1580,9 @@ return; } - const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); - if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) + const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI); + + if (isValidSysReg(Reg, true /*Read*/, STI)) O << Reg->Name; else O << AArch64SysReg::genericRegisterString(Val); @@ -1590,8 +1607,9 @@ return; } - const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); - if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) + const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI); + + if (isValidSysReg(Reg, false /*Read*/, STI)) O << Reg->Name; else O << AArch64SysReg::genericRegisterString(Val); Index: llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h =================================================================== --- llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -625,6 +625,7 @@ namespace AArch64SysReg { struct SysReg { const char *Name; + const char *AltName; unsigned Encoding; bool Readable; bool Writeable; Index: llvm/test/CodeGen/AArch64/arm64-crc32.ll =================================================================== --- llvm/test/CodeGen/AArch64/arm64-crc32.ll +++ llvm/test/CodeGen/AArch64/arm64-crc32.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=arm64-eabi -mattr=+crc -o - %s | FileCheck %s +; RUN: llc -mtriple=arm64-eabi -mattr=+v8r -o - %s | FileCheck %s ; RUN: llc -mtriple=arm64-eabi -mcpu=cortex-a53 -mattr=+crc -o - %s | FileCheck %s define i32 @test_crc32b(i32 %cur, i8 %next) { Index: llvm/test/MC/AArch64/arm64-branch-encoding.s =================================================================== --- llvm/test/MC/AArch64/arm64-branch-encoding.s +++ llvm/test/MC/AArch64/arm64-branch-encoding.s @@ -137,23 +137,17 @@ ; CHECK: encoding: [0x41,0x00,0xa0,0xd4] dcps2 #3 ; CHECK: encoding: [0x62,0x00,0xa0,0xd4] - dcps3 #4 -; CHECK: encoding: [0x83,0x00,0xa0,0xd4] hlt #5 ; CHECK: encoding: [0xa0,0x00,0x40,0xd4] hvc #6 ; CHECK: encoding: [0xc2,0x00,0x00,0xd4] - smc #7 -; CHECK: encoding: [0xe3,0x00,0x00,0xd4] svc #8 ; CHECK: encoding: [0x01,0x01,0x00,0xd4] ; The immediate defaults to zero for DCPSn dcps1 dcps2 - dcps3 ; CHECK: dcps1 ; encoding: [0x01,0x00,0xa0,0xd4] ; CHECK: dcps2 ; encoding: [0x02,0x00,0xa0,0xd4] -; CHECK: dcps3 ; encoding: [0x03,0x00,0xa0,0xd4] Index: llvm/test/MC/AArch64/arm64-system-encoding.s =================================================================== --- llvm/test/MC/AArch64/arm64-system-encoding.s +++ llvm/test/MC/AArch64/arm64-system-encoding.s @@ -123,7 +123,6 @@ msr TPIDR_EL2, x3 msr TPIDR_EL3, x3 msr TTBR0_EL1, x3 - msr TTBR0_EL2, x3 msr TTBR0_EL3, x3 msr TTBR1_EL1, x3 msr VBAR_EL1, x3 @@ -132,7 +131,6 @@ msr VMPIDR_EL2, x3 msr VPIDR_EL2, x3 msr VTCR_EL2, x3 - msr VTTBR_EL2, x3 msr SPSel, x3 msr S3_2_C11_C6_4, x1 msr S0_0_C0_C0_0, x0 @@ -202,7 +200,6 @@ ; CHECK: msr TPIDR_EL2, x3 ; encoding: [0x43,0xd0,0x1c,0xd5] ; CHECK: msr TPIDR_EL3, x3 ; encoding: [0x43,0xd0,0x1e,0xd5] ; CHECK: msr TTBR0_EL1, x3 ; encoding: [0x03,0x20,0x18,0xd5] -; CHECK: msr TTBR0_EL2, x3 ; encoding: [0x03,0x20,0x1c,0xd5] ; CHECK: msr TTBR0_EL3, x3 ; encoding: [0x03,0x20,0x1e,0xd5] ; CHECK: msr TTBR1_EL1, x3 ; encoding: [0x23,0x20,0x18,0xd5] ; CHECK: msr VBAR_EL1, x3 ; encoding: [0x03,0xc0,0x18,0xd5] @@ -211,7 +208,6 @@ ; CHECK: msr VMPIDR_EL2, x3 ; encoding: [0xa3,0x00,0x1c,0xd5] ; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5] ; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5] -; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5] ; CHECK: msr SPSel, x3 ; encoding: [0x03,0x42,0x18,0xd5] ; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5] ; CHECK: msr S0_0_C0_C0_0, x0 ; encoding: [0x00,0x00,0x00,0xd5] @@ -313,7 +309,6 @@ mrs x3, TPIDR_EL2 mrs x3, TPIDR_EL3 mrs x3, TTBR0_EL1 - mrs x3, TTBR0_EL2 mrs x3, TTBR0_EL3 mrs x3, TTBR1_EL1 mrs x3, VBAR_EL1 @@ -322,7 +317,6 @@ mrs x3, VMPIDR_EL2 mrs x3, VPIDR_EL2 mrs x3, VTCR_EL2 - mrs x3, VTTBR_EL2 mrs x3, MDCCSR_EL0 mrs x3, MDCCINT_EL1 @@ -500,7 +494,6 @@ ; CHECK: mrs x3, TPIDR_EL2 ; encoding: [0x43,0xd0,0x3c,0xd5] ; CHECK: mrs x3, TPIDR_EL3 ; encoding: [0x43,0xd0,0x3e,0xd5] ; CHECK: mrs x3, TTBR0_EL1 ; encoding: [0x03,0x20,0x38,0xd5] -; CHECK: mrs x3, TTBR0_EL2 ; encoding: [0x03,0x20,0x3c,0xd5] ; CHECK: mrs x3, TTBR0_EL3 ; encoding: [0x03,0x20,0x3e,0xd5] ; CHECK: mrs x3, TTBR1_EL1 ; encoding: [0x23,0x20,0x38,0xd5] ; CHECK: mrs x3, VBAR_EL1 ; encoding: [0x03,0xc0,0x38,0xd5] @@ -509,7 +502,6 @@ ; CHECK: mrs x3, VMPIDR_EL2 ; encoding: [0xa3,0x00,0x3c,0xd5] ; CHECK: mrs x3, VPIDR_EL2 ; encoding: [0x03,0x00,0x3c,0xd5] ; CHECK: mrs x3, VTCR_EL2 ; encoding: [0x43,0x21,0x3c,0xd5] -; CHECK: mrs x3, VTTBR_EL2 ; encoding: [0x03,0x21,0x3c,0xd5] ; CHECK: mrs x3, MDCCSR_EL0 ; encoding: [0x03,0x01,0x33,0xd5] ; CHECK: mrs x3, MDCCINT_EL1 ; encoding: [0x03,0x02,0x30,0xd5] ; CHECK: mrs x3, DBGDTR_EL0 ; encoding: [0x03,0x04,0x33,0xd5] Index: llvm/test/MC/AArch64/armv8.1a-lse.s =================================================================== --- llvm/test/MC/AArch64/armv8.1a-lse.s +++ llvm/test/MC/AArch64/armv8.1a-lse.s @@ -6,6 +6,8 @@ // RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mcpu=tsv110 -show-encoding < %s 2> %t | FileCheck %s // RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r -show-encoding < %s 2> %t | FileCheck %s +// RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s .text cas w0, w1, [x2] Index: llvm/test/MC/AArch64/armv8.1a-pan.s =================================================================== --- llvm/test/MC/AArch64/armv8.1a-pan.s +++ llvm/test/MC/AArch64/armv8.1a-pan.s @@ -1,5 +1,7 @@ // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r -show-encoding < %s 2> %t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t .text Index: llvm/test/MC/AArch64/armv8.1a-rdma.s =================================================================== --- llvm/test/MC/AArch64/armv8.1a-rdma.s +++ llvm/test/MC/AArch64/armv8.1a-rdma.s @@ -1,5 +1,7 @@ // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r -show-encoding < %s 2> %t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s .text //AdvSIMD RDMA vector Index: llvm/test/MC/AArch64/armv8.2a-at.s =================================================================== --- llvm/test/MC/AArch64/armv8.2a-at.s +++ llvm/test/MC/AArch64/armv8.2a-at.s @@ -1,7 +1,10 @@ // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a %s -o - | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a,+pan-rwv %s -o - | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r %s -o - | FileCheck %s // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8r %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-pan-rwv %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r,-pan-rwv %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR at s1e1rp, x1 at s1e1wp, x2 Index: llvm/test/MC/AArch64/armv8.2a-crypto.s =================================================================== --- llvm/test/MC/AArch64/armv8.2a-crypto.s +++ llvm/test/MC/AArch64/armv8.2a-crypto.s @@ -7,6 +7,8 @@ // RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-NO-SHA --check-prefix=CHECK-NO-SM < %t %s +// RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding -o - %s | FileCheck %s --check-prefixes=CHECK-SM,CHECK-SHA + sha512h q0, q1, v2.2d sha512h2 q0, q1, v2.2d sha512su0 v11.2d, v12.2d Index: llvm/test/MC/AArch64/armv8.2a-dotprod-errors.s =================================================================== --- llvm/test/MC/AArch64/armv8.2a-dotprod-errors.s +++ llvm/test/MC/AArch64/armv8.2a-dotprod-errors.s @@ -1,5 +1,7 @@ // RUN: not llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s +// RUN: not llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s udot v0.2s, v1.8b, v2.4b[4] sdot v0.2s, v1.8b, v2.4b[4] Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s =================================================================== --- llvm/test/MC/AArch64/armv8.2a-dotprod.s +++ llvm/test/MC/AArch64/armv8.2a-dotprod.s @@ -11,9 +11,15 @@ // RUN: llvm-mc -triple aarch64 -mcpu=neoverse-n1 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD // RUN: llvm-mc -triple aarch64 -mcpu=neoverse-n2 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD // RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD +// RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD +// RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD // RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s +// RUN: not llvm-mc -triple aarch64 -mattr=+v8r,-dotprod -show-encoding < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s +// RUN: not llvm-mc -triple aarch64 -mcpu=cortex-r82 -mattr=-dotprod -show-encoding < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s // RUN: not llvm-mc -triple aarch64 -mcpu=cortex-a65 -mattr=-dotprod -show-encoding < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s // RUN: not llvm-mc -triple aarch64 -mcpu=cortex-a65ae -mattr=-dotprod -show-encoding < %s 2> %t Index: llvm/test/MC/AArch64/armv8.2a-persistent-memory.s =================================================================== --- llvm/test/MC/AArch64/armv8.2a-persistent-memory.s +++ llvm/test/MC/AArch64/armv8.2a-persistent-memory.s @@ -1,5 +1,6 @@ // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -o - %s | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ccpp -o - %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r -o - %s | FileCheck %s // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR dc cvap, x7 Index: llvm/test/MC/AArch64/armv8.2a-uao.s =================================================================== --- llvm/test/MC/AArch64/armv8.2a-uao.s +++ llvm/test/MC/AArch64/armv8.2a-uao.s @@ -1,5 +1,7 @@ // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s 2> %t | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r -o - %s 2> %t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t msr uao, #0 msr uao, #1 Index: llvm/test/MC/AArch64/armv8r-inst.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/armv8r-inst.s @@ -0,0 +1,6 @@ +// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8r -o - %s | FileCheck %s +.text +dfb + +// CHECK: .text +// CHECK-NEXT: dfb // encoding: [0x9f,0x3c,0x03,0xd5] Index: llvm/test/MC/AArch64/armv8r-sysreg.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/armv8r-sysreg.s @@ -0,0 +1,606 @@ +// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8r -o - %s | FileCheck %s +.text +mrs x0, VSCTLR_EL2 +mrs x0, MPUIR_EL1 +mrs x0, MPUIR_EL2 +mrs x0, PRENR_EL1 +mrs x0, PRENR_EL2 +mrs x0, PRSELR_EL1 +mrs x0, PRSELR_EL2 +mrs x0, PRBAR_EL1 +mrs x0, PRBAR_EL2 +mrs x0, PRLAR_EL1 +mrs x0, PRLAR_EL2 +mrs x0, PRBAR0_EL1 +mrs x0, PRBAR1_EL1 +mrs x0, PRBAR2_EL1 +mrs x0, PRBAR3_EL1 +mrs x0, PRBAR4_EL1 +mrs x0, PRBAR5_EL1 +mrs x0, PRBAR6_EL1 +mrs x0, PRBAR7_EL1 +mrs x0, PRBAR8_EL1 +mrs x0, PRBAR9_EL1 +mrs x0, PRBAR10_EL1 +mrs x0, PRBAR11_EL1 +mrs x0, PRBAR12_EL1 +mrs x0, PRBAR13_EL1 +mrs x0, PRBAR14_EL1 +mrs x0, PRBAR15_EL1 +mrs x0, PRLAR0_EL1 +mrs x0, PRLAR1_EL1 +mrs x0, PRLAR2_EL1 +mrs x0, PRLAR3_EL1 +mrs x0, PRLAR4_EL1 +mrs x0, PRLAR5_EL1 +mrs x0, PRLAR6_EL1 +mrs x0, PRLAR7_EL1 +mrs x0, PRLAR8_EL1 +mrs x0, PRLAR9_EL1 +mrs x0, PRLAR10_EL1 +mrs x0, PRLAR11_EL1 +mrs x0, PRLAR12_EL1 +mrs x0, PRLAR13_EL1 +mrs x0, PRLAR14_EL1 +mrs x0, PRLAR15_EL1 +mrs x0, PRBAR0_EL2 +mrs x0, PRBAR1_EL2 +mrs x0, PRBAR2_EL2 +mrs x0, PRBAR3_EL2 +mrs x0, PRBAR4_EL2 +mrs x0, PRBAR5_EL2 +mrs x0, PRBAR6_EL2 +mrs x0, PRBAR7_EL2 +mrs x0, PRBAR8_EL2 +mrs x0, PRBAR9_EL2 +mrs x0, PRBAR10_EL2 +mrs x0, PRBAR11_EL2 +mrs x0, PRBAR12_EL2 +mrs x0, PRBAR13_EL2 +mrs x0, PRBAR14_EL2 +mrs x0, PRBAR15_EL2 +mrs x0, PRLAR0_EL2 +mrs x0, PRLAR1_EL2 +mrs x0, PRLAR2_EL2 +mrs x0, PRLAR3_EL2 +mrs x0, PRLAR4_EL2 +mrs x0, PRLAR5_EL2 +mrs x0, PRLAR6_EL2 +mrs x0, PRLAR7_EL2 +mrs x0, PRLAR8_EL2 +mrs x0, PRLAR9_EL2 +mrs x0, PRLAR10_EL2 +mrs x0, PRLAR11_EL2 +mrs x0, PRLAR12_EL2 +mrs x0, PRLAR13_EL2 +mrs x0, PRLAR14_EL2 +mrs x0, PRLAR15_EL2 +mrs x30, VSCTLR_EL2 +mrs x30, MPUIR_EL1 +mrs x30, MPUIR_EL2 +mrs x30, PRENR_EL1 +mrs x30, PRENR_EL2 +mrs x30, PRSELR_EL1 +mrs x30, PRSELR_EL2 +mrs x30, PRBAR_EL1 +mrs x30, PRBAR_EL2 +mrs x30, PRLAR_EL1 +mrs x30, PRLAR_EL2 +mrs x30, PRBAR0_EL1 +mrs x30, PRBAR1_EL1 +mrs x30, PRBAR2_EL1 +mrs x30, PRBAR3_EL1 +mrs x30, PRBAR4_EL1 +mrs x30, PRBAR5_EL1 +mrs x30, PRBAR6_EL1 +mrs x30, PRBAR7_EL1 +mrs x30, PRBAR8_EL1 +mrs x30, PRBAR9_EL1 +mrs x30, PRBAR10_EL1 +mrs x30, PRBAR11_EL1 +mrs x30, PRBAR12_EL1 +mrs x30, PRBAR13_EL1 +mrs x30, PRBAR14_EL1 +mrs x30, PRBAR15_EL1 +mrs x30, PRLAR0_EL1 +mrs x30, PRLAR1_EL1 +mrs x30, PRLAR2_EL1 +mrs x30, PRLAR3_EL1 +mrs x30, PRLAR4_EL1 +mrs x30, PRLAR5_EL1 +mrs x30, PRLAR6_EL1 +mrs x30, PRLAR7_EL1 +mrs x30, PRLAR8_EL1 +mrs x30, PRLAR9_EL1 +mrs x30, PRLAR10_EL1 +mrs x30, PRLAR11_EL1 +mrs x30, PRLAR12_EL1 +mrs x30, PRLAR13_EL1 +mrs x30, PRLAR14_EL1 +mrs x30, PRLAR15_EL1 +mrs x30, PRBAR0_EL2 +mrs x30, PRBAR1_EL2 +mrs x30, PRBAR2_EL2 +mrs x30, PRBAR3_EL2 +mrs x30, PRBAR4_EL2 +mrs x30, PRBAR5_EL2 +mrs x30, PRBAR6_EL2 +mrs x30, PRBAR7_EL2 +mrs x30, PRBAR8_EL2 +mrs x30, PRBAR9_EL2 +mrs x30, PRBAR10_EL2 +mrs x30, PRBAR11_EL2 +mrs x30, PRBAR12_EL2 +mrs x30, PRBAR13_EL2 +mrs x30, PRBAR14_EL2 +mrs x30, PRBAR15_EL2 +mrs x30, PRLAR0_EL2 +mrs x30, PRLAR1_EL2 +mrs x30, PRLAR2_EL2 +mrs x30, PRLAR3_EL2 +mrs x30, PRLAR4_EL2 +mrs x30, PRLAR5_EL2 +mrs x30, PRLAR6_EL2 +mrs x30, PRLAR7_EL2 +mrs x30, PRLAR8_EL2 +mrs x30, PRLAR9_EL2 +mrs x30, PRLAR10_EL2 +mrs x30, PRLAR11_EL2 +mrs x30, PRLAR12_EL2 +mrs x30, PRLAR13_EL2 +mrs x30, PRLAR14_EL2 +mrs x30, PRLAR15_EL2 +msr VSCTLR_EL2, x0 +msr MPUIR_EL1, x0 +msr MPUIR_EL2, x0 +msr PRENR_EL1, x0 +msr PRENR_EL2, x0 +msr PRSELR_EL1, x0 +msr PRSELR_EL2, x0 +msr PRBAR_EL1, x0 +msr PRBAR_EL2, x0 +msr PRLAR_EL1, x0 +msr PRLAR_EL2, x0 +msr PRBAR0_EL1, x0 +msr PRBAR1_EL1, x0 +msr PRBAR2_EL1, x0 +msr PRBAR3_EL1, x0 +msr PRBAR4_EL1, x0 +msr PRBAR5_EL1, x0 +msr PRBAR6_EL1, x0 +msr PRBAR7_EL1, x0 +msr PRBAR8_EL1, x0 +msr PRBAR9_EL1, x0 +msr PRBAR10_EL1, x0 +msr PRBAR11_EL1, x0 +msr PRBAR12_EL1, x0 +msr PRBAR13_EL1, x0 +msr PRBAR14_EL1, x0 +msr PRBAR15_EL1, x0 +msr PRLAR0_EL1, x0 +msr PRLAR1_EL1, x0 +msr PRLAR2_EL1, x0 +msr PRLAR3_EL1, x0 +msr PRLAR4_EL1, x0 +msr PRLAR5_EL1, x0 +msr PRLAR6_EL1, x0 +msr PRLAR7_EL1, x0 +msr PRLAR8_EL1, x0 +msr PRLAR9_EL1, x0 +msr PRLAR10_EL1, x0 +msr PRLAR11_EL1, x0 +msr PRLAR12_EL1, x0 +msr PRLAR13_EL1, x0 +msr PRLAR14_EL1, x0 +msr PRLAR15_EL1, x0 +msr PRBAR0_EL2, x0 +msr PRBAR1_EL2, x0 +msr PRBAR2_EL2, x0 +msr PRBAR3_EL2, x0 +msr PRBAR4_EL2, x0 +msr PRBAR5_EL2, x0 +msr PRBAR6_EL2, x0 +msr PRBAR7_EL2, x0 +msr PRBAR8_EL2, x0 +msr PRBAR9_EL2, x0 +msr PRBAR10_EL2, x0 +msr PRBAR11_EL2, x0 +msr PRBAR12_EL2, x0 +msr PRBAR13_EL2, x0 +msr PRBAR14_EL2, x0 +msr PRBAR15_EL2, x0 +msr PRLAR0_EL2, x0 +msr PRLAR1_EL2, x0 +msr PRLAR2_EL2, x0 +msr PRLAR3_EL2, x0 +msr PRLAR4_EL2, x0 +msr PRLAR5_EL2, x0 +msr PRLAR6_EL2, x0 +msr PRLAR7_EL2, x0 +msr PRLAR8_EL2, x0 +msr PRLAR9_EL2, x0 +msr PRLAR10_EL2, x0 +msr PRLAR11_EL2, x0 +msr PRLAR12_EL2, x0 +msr PRLAR13_EL2, x0 +msr PRLAR14_EL2, x0 +msr PRLAR15_EL2, x0 +msr VSCTLR_EL2, x30 +msr MPUIR_EL1, x30 +msr MPUIR_EL2, x30 +msr PRENR_EL1, x30 +msr PRENR_EL2, x30 +msr PRSELR_EL1, x30 +msr PRSELR_EL2, x30 +msr PRBAR_EL1, x30 +msr PRBAR_EL2, x30 +msr PRLAR_EL1, x30 +msr PRLAR_EL2, x30 +msr PRBAR0_EL1, x30 +msr PRBAR1_EL1, x30 +msr PRBAR2_EL1, x30 +msr PRBAR3_EL1, x30 +msr PRBAR4_EL1, x30 +msr PRBAR5_EL1, x30 +msr PRBAR6_EL1, x30 +msr PRBAR7_EL1, x30 +msr PRBAR8_EL1, x30 +msr PRBAR9_EL1, x30 +msr PRBAR10_EL1, x30 +msr PRBAR11_EL1, x30 +msr PRBAR12_EL1, x30 +msr PRBAR13_EL1, x30 +msr PRBAR14_EL1, x30 +msr PRBAR15_EL1, x30 +msr PRLAR0_EL1, x30 +msr PRLAR1_EL1, x30 +msr PRLAR2_EL1, x30 +msr PRLAR3_EL1, x30 +msr PRLAR4_EL1, x30 +msr PRLAR5_EL1, x30 +msr PRLAR6_EL1, x30 +msr PRLAR7_EL1, x30 +msr PRLAR8_EL1, x30 +msr PRLAR9_EL1, x30 +msr PRLAR10_EL1, x30 +msr PRLAR11_EL1, x30 +msr PRLAR12_EL1, x30 +msr PRLAR13_EL1, x30 +msr PRLAR14_EL1, x30 +msr PRLAR15_EL1, x30 +msr PRBAR0_EL2, x30 +msr PRBAR1_EL2, x30 +msr PRBAR2_EL2, x30 +msr PRBAR3_EL2, x30 +msr PRBAR4_EL2, x30 +msr PRBAR5_EL2, x30 +msr PRBAR6_EL2, x30 +msr PRBAR7_EL2, x30 +msr PRBAR8_EL2, x30 +msr PRBAR9_EL2, x30 +msr PRBAR10_EL2, x30 +msr PRBAR11_EL2, x30 +msr PRBAR12_EL2, x30 +msr PRBAR13_EL2, x30 +msr PRBAR14_EL2, x30 +msr PRBAR15_EL2, x30 +msr PRLAR0_EL2, x30 +msr PRLAR1_EL2, x30 +msr PRLAR2_EL2, x30 +msr PRLAR3_EL2, x30 +msr PRLAR4_EL2, x30 +msr PRLAR5_EL2, x30 +msr PRLAR6_EL2, x30 +msr PRLAR7_EL2, x30 +msr PRLAR8_EL2, x30 +msr PRLAR9_EL2, x30 +msr PRLAR10_EL2, x30 +msr PRLAR11_EL2, x30 +msr PRLAR12_EL2, x30 +msr PRLAR13_EL2, x30 +msr PRLAR14_EL2, x30 +msr PRLAR15_EL2, x30 +msr CONTEXTIDR_EL2, x0 + +# CHECK: .text +# CHECK-NEXT: mrs x0, VSCTLR_EL2 // encoding: [0x00,0x20,0x3c,0xd5] +# CHECK-NEXT: mrs x0, MPUIR_EL1 // encoding: [0x80,0x00,0x38,0xd5] +# CHECK-NEXT: mrs x0, MPUIR_EL2 // encoding: [0x80,0x00,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRENR_EL1 // encoding: [0x20,0x61,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRENR_EL2 // encoding: [0x20,0x61,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRSELR_EL1 // encoding: [0x20,0x62,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRSELR_EL2 // encoding: [0x20,0x62,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR_EL1 // encoding: [0x00,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR_EL2 // encoding: [0x00,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR_EL1 // encoding: [0x20,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x0, {{PRLAR[0]?_EL2}} // encoding: [0x20,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR_EL1 // encoding: [0x00,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR1_EL1 // encoding: [0x80,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR2_EL1 // encoding: [0x00,0x69,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR3_EL1 // encoding: [0x80,0x69,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR4_EL1 // encoding: [0x00,0x6a,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR5_EL1 // encoding: [0x80,0x6a,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR6_EL1 // encoding: [0x00,0x6b,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR7_EL1 // encoding: [0x80,0x6b,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR8_EL1 // encoding: [0x00,0x6c,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR9_EL1 // encoding: [0x80,0x6c,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR10_EL1 // encoding: [0x00,0x6d,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR11_EL1 // encoding: [0x80,0x6d,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR12_EL1 // encoding: [0x00,0x6e,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR13_EL1 // encoding: [0x80,0x6e,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR14_EL1 // encoding: [0x00,0x6f,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR15_EL1 // encoding: [0x80,0x6f,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR_EL1 // encoding: [0x20,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR1_EL1 // encoding: [0xa0,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR2_EL1 // encoding: [0x20,0x69,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR3_EL1 // encoding: [0xa0,0x69,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR4_EL1 // encoding: [0x20,0x6a,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR5_EL1 // encoding: [0xa0,0x6a,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR6_EL1 // encoding: [0x20,0x6b,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR7_EL1 // encoding: [0xa0,0x6b,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR8_EL1 // encoding: [0x20,0x6c,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR9_EL1 // encoding: [0xa0,0x6c,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR10_EL1 // encoding: [0x20,0x6d,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR11_EL1 // encoding: [0xa0,0x6d,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR12_EL1 // encoding: [0x20,0x6e,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR13_EL1 // encoding: [0xa0,0x6e,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR14_EL1 // encoding: [0x20,0x6f,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRLAR15_EL1 // encoding: [0xa0,0x6f,0x38,0xd5] +# CHECK-NEXT: mrs x0, PRBAR_EL2 // encoding: [0x00,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR1_EL2 // encoding: [0x80,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR2_EL2 // encoding: [0x00,0x69,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR3_EL2 // encoding: [0x80,0x69,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR4_EL2 // encoding: [0x00,0x6a,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR5_EL2 // encoding: [0x80,0x6a,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR6_EL2 // encoding: [0x00,0x6b,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR7_EL2 // encoding: [0x80,0x6b,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR8_EL2 // encoding: [0x00,0x6c,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR9_EL2 // encoding: [0x80,0x6c,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR10_EL2 // encoding: [0x00,0x6d,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR11_EL2 // encoding: [0x80,0x6d,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR12_EL2 // encoding: [0x00,0x6e,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR13_EL2 // encoding: [0x80,0x6e,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR14_EL2 // encoding: [0x00,0x6f,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRBAR15_EL2 // encoding: [0x80,0x6f,0x3c,0xd5] +# CHECK-NEXT: mrs x0, {{PRLAR[0]?_EL2}} // encoding: [0x20,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR1_EL2 // encoding: [0xa0,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR2_EL2 // encoding: [0x20,0x69,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR3_EL2 // encoding: [0xa0,0x69,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR4_EL2 // encoding: [0x20,0x6a,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR5_EL2 // encoding: [0xa0,0x6a,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR6_EL2 // encoding: [0x20,0x6b,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR7_EL2 // encoding: [0xa0,0x6b,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR8_EL2 // encoding: [0x20,0x6c,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR9_EL2 // encoding: [0xa0,0x6c,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR10_EL2 // encoding: [0x20,0x6d,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR11_EL2 // encoding: [0xa0,0x6d,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR12_EL2 // encoding: [0x20,0x6e,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR13_EL2 // encoding: [0xa0,0x6e,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR14_EL2 // encoding: [0x20,0x6f,0x3c,0xd5] +# CHECK-NEXT: mrs x0, PRLAR15_EL2 // encoding: [0xa0,0x6f,0x3c,0xd5] +# CHECK-NEXT: mrs x30, VSCTLR_EL2 // encoding: [0x1e,0x20,0x3c,0xd5] +# CHECK-NEXT: mrs x30, MPUIR_EL1 // encoding: [0x9e,0x00,0x38,0xd5] +# CHECK-NEXT: mrs x30, MPUIR_EL2 // encoding: [0x9e,0x00,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRENR_EL1 // encoding: [0x3e,0x61,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRENR_EL2 // encoding: [0x3e,0x61,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRSELR_EL1 // encoding: [0x3e,0x62,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRSELR_EL2 // encoding: [0x3e,0x62,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR_EL1 // encoding: [0x1e,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR_EL2 // encoding: [0x1e,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR_EL1 // encoding: [0x3e,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x30, {{PRLAR[0]?_EL2}} // encoding: [0x3e,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR_EL1 // encoding: [0x1e,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR1_EL1 // encoding: [0x9e,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR2_EL1 // encoding: [0x1e,0x69,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR3_EL1 // encoding: [0x9e,0x69,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR4_EL1 // encoding: [0x1e,0x6a,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR5_EL1 // encoding: [0x9e,0x6a,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR6_EL1 // encoding: [0x1e,0x6b,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR7_EL1 // encoding: [0x9e,0x6b,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR8_EL1 // encoding: [0x1e,0x6c,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR9_EL1 // encoding: [0x9e,0x6c,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR10_EL1 // encoding: [0x1e,0x6d,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR11_EL1 // encoding: [0x9e,0x6d,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR12_EL1 // encoding: [0x1e,0x6e,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR13_EL1 // encoding: [0x9e,0x6e,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR14_EL1 // encoding: [0x1e,0x6f,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR15_EL1 // encoding: [0x9e,0x6f,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR_EL1 // encoding: [0x3e,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR1_EL1 // encoding: [0xbe,0x68,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR2_EL1 // encoding: [0x3e,0x69,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR3_EL1 // encoding: [0xbe,0x69,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR4_EL1 // encoding: [0x3e,0x6a,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR5_EL1 // encoding: [0xbe,0x6a,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR6_EL1 // encoding: [0x3e,0x6b,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR7_EL1 // encoding: [0xbe,0x6b,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR8_EL1 // encoding: [0x3e,0x6c,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR9_EL1 // encoding: [0xbe,0x6c,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR10_EL1 // encoding: [0x3e,0x6d,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR11_EL1 // encoding: [0xbe,0x6d,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR12_EL1 // encoding: [0x3e,0x6e,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR13_EL1 // encoding: [0xbe,0x6e,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR14_EL1 // encoding: [0x3e,0x6f,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRLAR15_EL1 // encoding: [0xbe,0x6f,0x38,0xd5] +# CHECK-NEXT: mrs x30, PRBAR_EL2 // encoding: [0x1e,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR1_EL2 // encoding: [0x9e,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR2_EL2 // encoding: [0x1e,0x69,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR3_EL2 // encoding: [0x9e,0x69,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR4_EL2 // encoding: [0x1e,0x6a,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR5_EL2 // encoding: [0x9e,0x6a,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR6_EL2 // encoding: [0x1e,0x6b,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR7_EL2 // encoding: [0x9e,0x6b,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR8_EL2 // encoding: [0x1e,0x6c,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR9_EL2 // encoding: [0x9e,0x6c,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR10_EL2 // encoding: [0x1e,0x6d,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR11_EL2 // encoding: [0x9e,0x6d,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR12_EL2 // encoding: [0x1e,0x6e,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR13_EL2 // encoding: [0x9e,0x6e,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR14_EL2 // encoding: [0x1e,0x6f,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRBAR15_EL2 // encoding: [0x9e,0x6f,0x3c,0xd5] +# CHECK-NEXT: mrs x30, {{PRLAR[0]?_EL2}} // encoding: [0x3e,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR1_EL2 // encoding: [0xbe,0x68,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR2_EL2 // encoding: [0x3e,0x69,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR3_EL2 // encoding: [0xbe,0x69,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR4_EL2 // encoding: [0x3e,0x6a,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR5_EL2 // encoding: [0xbe,0x6a,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR6_EL2 // encoding: [0x3e,0x6b,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR7_EL2 // encoding: [0xbe,0x6b,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR8_EL2 // encoding: [0x3e,0x6c,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR9_EL2 // encoding: [0xbe,0x6c,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR10_EL2 // encoding: [0x3e,0x6d,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR11_EL2 // encoding: [0xbe,0x6d,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR12_EL2 // encoding: [0x3e,0x6e,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR13_EL2 // encoding: [0xbe,0x6e,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR14_EL2 // encoding: [0x3e,0x6f,0x3c,0xd5] +# CHECK-NEXT: mrs x30, PRLAR15_EL2 // encoding: [0xbe,0x6f,0x3c,0xd5] +# CHECK-NEXT: msr VSCTLR_EL2, x0 // encoding: [0x00,0x20,0x1c,0xd5] +# CHECK-NEXT: msr MPUIR_EL1, x0 // encoding: [0x80,0x00,0x18,0xd5] +# CHECK-NEXT: msr MPUIR_EL2, x0 // encoding: [0x80,0x00,0x1c,0xd5] +# CHECK-NEXT: msr PRENR_EL1, x0 // encoding: [0x20,0x61,0x18,0xd5] +# CHECK-NEXT: msr PRENR_EL2, x0 // encoding: [0x20,0x61,0x1c,0xd5] +# CHECK-NEXT: msr PRSELR_EL1, x0 // encoding: [0x20,0x62,0x18,0xd5] +# CHECK-NEXT: msr PRSELR_EL2, x0 // encoding: [0x20,0x62,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR_EL1, x0 // encoding: [0x00,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRBAR_EL2, x0 // encoding: [0x00,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR_EL1, x0 // encoding: [0x20,0x68,0x18,0xd5] +# CHECK-NEXT: msr {{PRLAR[0]?_EL2}}, x0 // encoding: [0x20,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR_EL1, x0 // encoding: [0x00,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRBAR1_EL1, x0 // encoding: [0x80,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRBAR2_EL1, x0 // encoding: [0x00,0x69,0x18,0xd5] +# CHECK-NEXT: msr PRBAR3_EL1, x0 // encoding: [0x80,0x69,0x18,0xd5] +# CHECK-NEXT: msr PRBAR4_EL1, x0 // encoding: [0x00,0x6a,0x18,0xd5] +# CHECK-NEXT: msr PRBAR5_EL1, x0 // encoding: [0x80,0x6a,0x18,0xd5] +# CHECK-NEXT: msr PRBAR6_EL1, x0 // encoding: [0x00,0x6b,0x18,0xd5] +# CHECK-NEXT: msr PRBAR7_EL1, x0 // encoding: [0x80,0x6b,0x18,0xd5] +# CHECK-NEXT: msr PRBAR8_EL1, x0 // encoding: [0x00,0x6c,0x18,0xd5] +# CHECK-NEXT: msr PRBAR9_EL1, x0 // encoding: [0x80,0x6c,0x18,0xd5] +# CHECK-NEXT: msr PRBAR10_EL1, x0 // encoding: [0x00,0x6d,0x18,0xd5] +# CHECK-NEXT: msr PRBAR11_EL1, x0 // encoding: [0x80,0x6d,0x18,0xd5] +# CHECK-NEXT: msr PRBAR12_EL1, x0 // encoding: [0x00,0x6e,0x18,0xd5] +# CHECK-NEXT: msr PRBAR13_EL1, x0 // encoding: [0x80,0x6e,0x18,0xd5] +# CHECK-NEXT: msr PRBAR14_EL1, x0 // encoding: [0x00,0x6f,0x18,0xd5] +# CHECK-NEXT: msr PRBAR15_EL1, x0 // encoding: [0x80,0x6f,0x18,0xd5] +# CHECK-NEXT: msr PRLAR_EL1, x0 // encoding: [0x20,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRLAR1_EL1, x0 // encoding: [0xa0,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRLAR2_EL1, x0 // encoding: [0x20,0x69,0x18,0xd5] +# CHECK-NEXT: msr PRLAR3_EL1, x0 // encoding: [0xa0,0x69,0x18,0xd5] +# CHECK-NEXT: msr PRLAR4_EL1, x0 // encoding: [0x20,0x6a,0x18,0xd5] +# CHECK-NEXT: msr PRLAR5_EL1, x0 // encoding: [0xa0,0x6a,0x18,0xd5] +# CHECK-NEXT: msr PRLAR6_EL1, x0 // encoding: [0x20,0x6b,0x18,0xd5] +# CHECK-NEXT: msr PRLAR7_EL1, x0 // encoding: [0xa0,0x6b,0x18,0xd5] +# CHECK-NEXT: msr PRLAR8_EL1, x0 // encoding: [0x20,0x6c,0x18,0xd5] +# CHECK-NEXT: msr PRLAR9_EL1, x0 // encoding: [0xa0,0x6c,0x18,0xd5] +# CHECK-NEXT: msr PRLAR10_EL1, x0 // encoding: [0x20,0x6d,0x18,0xd5] +# CHECK-NEXT: msr PRLAR11_EL1, x0 // encoding: [0xa0,0x6d,0x18,0xd5] +# CHECK-NEXT: msr PRLAR12_EL1, x0 // encoding: [0x20,0x6e,0x18,0xd5] +# CHECK-NEXT: msr PRLAR13_EL1, x0 // encoding: [0xa0,0x6e,0x18,0xd5] +# CHECK-NEXT: msr PRLAR14_EL1, x0 // encoding: [0x20,0x6f,0x18,0xd5] +# CHECK-NEXT: msr PRLAR15_EL1, x0 // encoding: [0xa0,0x6f,0x18,0xd5] +# CHECK-NEXT: msr PRBAR_EL2, x0 // encoding: [0x00,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR1_EL2, x0 // encoding: [0x80,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR2_EL2, x0 // encoding: [0x00,0x69,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR3_EL2, x0 // encoding: [0x80,0x69,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR4_EL2, x0 // encoding: [0x00,0x6a,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR5_EL2, x0 // encoding: [0x80,0x6a,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR6_EL2, x0 // encoding: [0x00,0x6b,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR7_EL2, x0 // encoding: [0x80,0x6b,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR8_EL2, x0 // encoding: [0x00,0x6c,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR9_EL2, x0 // encoding: [0x80,0x6c,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR10_EL2, x0 // encoding: [0x00,0x6d,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR11_EL2, x0 // encoding: [0x80,0x6d,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR12_EL2, x0 // encoding: [0x00,0x6e,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR13_EL2, x0 // encoding: [0x80,0x6e,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR14_EL2, x0 // encoding: [0x00,0x6f,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR15_EL2, x0 // encoding: [0x80,0x6f,0x1c,0xd5] +# CHECK-NEXT: msr {{PRLAR[0]?_EL2}}, x0 // encoding: [0x20,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR1_EL2, x0 // encoding: [0xa0,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR2_EL2, x0 // encoding: [0x20,0x69,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR3_EL2, x0 // encoding: [0xa0,0x69,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR4_EL2, x0 // encoding: [0x20,0x6a,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR5_EL2, x0 // encoding: [0xa0,0x6a,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR6_EL2, x0 // encoding: [0x20,0x6b,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR7_EL2, x0 // encoding: [0xa0,0x6b,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR8_EL2, x0 // encoding: [0x20,0x6c,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR9_EL2, x0 // encoding: [0xa0,0x6c,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR10_EL2, x0 // encoding: [0x20,0x6d,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR11_EL2, x0 // encoding: [0xa0,0x6d,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR12_EL2, x0 // encoding: [0x20,0x6e,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR13_EL2, x0 // encoding: [0xa0,0x6e,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR14_EL2, x0 // encoding: [0x20,0x6f,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR15_EL2, x0 // encoding: [0xa0,0x6f,0x1c,0xd5] +# CHECK-NEXT: msr VSCTLR_EL2, x30 // encoding: [0x1e,0x20,0x1c,0xd5] +# CHECK-NEXT: msr MPUIR_EL1, x30 // encoding: [0x9e,0x00,0x18,0xd5] +# CHECK-NEXT: msr MPUIR_EL2, x30 // encoding: [0x9e,0x00,0x1c,0xd5] +# CHECK-NEXT: msr PRENR_EL1, x30 // encoding: [0x3e,0x61,0x18,0xd5] +# CHECK-NEXT: msr PRENR_EL2, x30 // encoding: [0x3e,0x61,0x1c,0xd5] +# CHECK-NEXT: msr PRSELR_EL1, x30 // encoding: [0x3e,0x62,0x18,0xd5] +# CHECK-NEXT: msr PRSELR_EL2, x30 // encoding: [0x3e,0x62,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR_EL1, x30 // encoding: [0x1e,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRBAR_EL2, x30 // encoding: [0x1e,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR_EL1, x30 // encoding: [0x3e,0x68,0x18,0xd5] +# CHECK-NEXT: msr {{PRLAR[0]?_EL2}}, x30 // encoding: [0x3e,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR_EL1, x30 // encoding: [0x1e,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRBAR1_EL1, x30 // encoding: [0x9e,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRBAR2_EL1, x30 // encoding: [0x1e,0x69,0x18,0xd5] +# CHECK-NEXT: msr PRBAR3_EL1, x30 // encoding: [0x9e,0x69,0x18,0xd5] +# CHECK-NEXT: msr PRBAR4_EL1, x30 // encoding: [0x1e,0x6a,0x18,0xd5] +# CHECK-NEXT: msr PRBAR5_EL1, x30 // encoding: [0x9e,0x6a,0x18,0xd5] +# CHECK-NEXT: msr PRBAR6_EL1, x30 // encoding: [0x1e,0x6b,0x18,0xd5] +# CHECK-NEXT: msr PRBAR7_EL1, x30 // encoding: [0x9e,0x6b,0x18,0xd5] +# CHECK-NEXT: msr PRBAR8_EL1, x30 // encoding: [0x1e,0x6c,0x18,0xd5] +# CHECK-NEXT: msr PRBAR9_EL1, x30 // encoding: [0x9e,0x6c,0x18,0xd5] +# CHECK-NEXT: msr PRBAR10_EL1, x30 // encoding: [0x1e,0x6d,0x18,0xd5] +# CHECK-NEXT: msr PRBAR11_EL1, x30 // encoding: [0x9e,0x6d,0x18,0xd5] +# CHECK-NEXT: msr PRBAR12_EL1, x30 // encoding: [0x1e,0x6e,0x18,0xd5] +# CHECK-NEXT: msr PRBAR13_EL1, x30 // encoding: [0x9e,0x6e,0x18,0xd5] +# CHECK-NEXT: msr PRBAR14_EL1, x30 // encoding: [0x1e,0x6f,0x18,0xd5] +# CHECK-NEXT: msr PRBAR15_EL1, x30 // encoding: [0x9e,0x6f,0x18,0xd5] +# CHECK-NEXT: msr PRLAR_EL1, x30 // encoding: [0x3e,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRLAR1_EL1, x30 // encoding: [0xbe,0x68,0x18,0xd5] +# CHECK-NEXT: msr PRLAR2_EL1, x30 // encoding: [0x3e,0x69,0x18,0xd5] +# CHECK-NEXT: msr PRLAR3_EL1, x30 // encoding: [0xbe,0x69,0x18,0xd5] +# CHECK-NEXT: msr PRLAR4_EL1, x30 // encoding: [0x3e,0x6a,0x18,0xd5] +# CHECK-NEXT: msr PRLAR5_EL1, x30 // encoding: [0xbe,0x6a,0x18,0xd5] +# CHECK-NEXT: msr PRLAR6_EL1, x30 // encoding: [0x3e,0x6b,0x18,0xd5] +# CHECK-NEXT: msr PRLAR7_EL1, x30 // encoding: [0xbe,0x6b,0x18,0xd5] +# CHECK-NEXT: msr PRLAR8_EL1, x30 // encoding: [0x3e,0x6c,0x18,0xd5] +# CHECK-NEXT: msr PRLAR9_EL1, x30 // encoding: [0xbe,0x6c,0x18,0xd5] +# CHECK-NEXT: msr PRLAR10_EL1, x30 // encoding: [0x3e,0x6d,0x18,0xd5] +# CHECK-NEXT: msr PRLAR11_EL1, x30 // encoding: [0xbe,0x6d,0x18,0xd5] +# CHECK-NEXT: msr PRLAR12_EL1, x30 // encoding: [0x3e,0x6e,0x18,0xd5] +# CHECK-NEXT: msr PRLAR13_EL1, x30 // encoding: [0xbe,0x6e,0x18,0xd5] +# CHECK-NEXT: msr PRLAR14_EL1, x30 // encoding: [0x3e,0x6f,0x18,0xd5] +# CHECK-NEXT: msr PRLAR15_EL1, x30 // encoding: [0xbe,0x6f,0x18,0xd5] +# CHECK-NEXT: msr PRBAR_EL2, x30 // encoding: [0x1e,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR1_EL2, x30 // encoding: [0x9e,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR2_EL2, x30 // encoding: [0x1e,0x69,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR3_EL2, x30 // encoding: [0x9e,0x69,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR4_EL2, x30 // encoding: [0x1e,0x6a,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR5_EL2, x30 // encoding: [0x9e,0x6a,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR6_EL2, x30 // encoding: [0x1e,0x6b,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR7_EL2, x30 // encoding: [0x9e,0x6b,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR8_EL2, x30 // encoding: [0x1e,0x6c,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR9_EL2, x30 // encoding: [0x9e,0x6c,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR10_EL2, x30 // encoding: [0x1e,0x6d,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR11_EL2, x30 // encoding: [0x9e,0x6d,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR12_EL2, x30 // encoding: [0x1e,0x6e,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR13_EL2, x30 // encoding: [0x9e,0x6e,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR14_EL2, x30 // encoding: [0x1e,0x6f,0x1c,0xd5] +# CHECK-NEXT: msr PRBAR15_EL2, x30 // encoding: [0x9e,0x6f,0x1c,0xd5] +# CHECK-NEXT: msr {{PRLAR[0]?_EL2}}, x30 // encoding: [0x3e,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR1_EL2, x30 // encoding: [0xbe,0x68,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR2_EL2, x30 // encoding: [0x3e,0x69,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR3_EL2, x30 // encoding: [0xbe,0x69,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR4_EL2, x30 // encoding: [0x3e,0x6a,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR5_EL2, x30 // encoding: [0xbe,0x6a,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR6_EL2, x30 // encoding: [0x3e,0x6b,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR7_EL2, x30 // encoding: [0xbe,0x6b,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR8_EL2, x30 // encoding: [0x3e,0x6c,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR9_EL2, x30 // encoding: [0xbe,0x6c,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR10_EL2, x30 // encoding: [0x3e,0x6d,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR11_EL2, x30 // encoding: [0xbe,0x6d,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR12_EL2, x30 // encoding: [0x3e,0x6e,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR13_EL2, x30 // encoding: [0xbe,0x6e,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR14_EL2, x30 // encoding: [0x3e,0x6f,0x1c,0xd5] +# CHECK-NEXT: msr PRLAR15_EL2, x30 // encoding: [0xbe,0x6f,0x1c,0xd5] +# CHECK-NEXT: msr CONTEXTIDR_EL2, x0 // encoding: [0x20,0xd0,0x1c,0xd5] Index: llvm/test/MC/AArch64/armv8r-unsupported-inst.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/armv8r-unsupported-inst.s @@ -0,0 +1,23 @@ +// RUN: llvm-mc -triple aarch64 -mattr=+el3 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64 -mattr=+v8a -show-encoding < %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8r %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR + +// The immediate defaults to zero +// CHECK: dcps3 // encoding: [0x03,0x00,0xa0,0xd4] +dcps3 + +// CHECK: encoding: [0x83,0x00,0xa0,0xd4] +// CHECK: encoding: [0xe3,0x00,0x00,0xd4] + +dcps3 #4 +smc #7 + +// CHECK-ERROR: {{[0-9]+}}:{{[0-9]+}}: error: instruction requires: el3 +// CHECK-ERROR-NEXT: dcps3 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: {{[0-9]+}}:{{[0-9]+}}: error: instruction requires: el3 +// CHECK-ERROR-NEXT: dcps3 #4 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: {{[0-9]+}}:{{[0-9]+}}: error: instruction requires: el3 +// CHECK-ERROR-NEXT: smc #7 +// CHECK-ERROR-NEXT: ^ Index: llvm/test/MC/AArch64/armv8r-unsupported-sysreg.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/armv8r-unsupported-sysreg.s @@ -0,0 +1,36 @@ +// RUN: llvm-mc -triple aarch64 -mattr=+v8a -show-encoding < %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s 2>&1 |\ +// RUN: FileCheck --check-prefix=CHECK-ERROR %s + +// CHECK: msr TTBR0_EL2, x3 // encoding: [0x03,0x20,0x1c,0xd5] +// CHECK-NEXT: mrs x3, TTBR0_EL2 // encoding: [0x03,0x20,0x3c,0xd5] +// CHECK-NEXT: msr VTTBR_EL2, x3 // encoding: [0x03,0x21,0x1c,0xd5] +// CHECK-NEXT: mrs x3, VTTBR_EL2 // encoding: [0x03,0x21,0x3c,0xd5] +// CHECK-NEXT: msr VSTTBR_EL2, x3 // encoding: [0x03,0x26,0x1c,0xd5] +// CHECK-NEXT: mrs x3, VSTTBR_EL2 // encoding: [0x03,0x26,0x3c,0xd5] + +msr TTBR0_EL2, x3 +mrs x3, TTBR0_EL2 +msr VTTBR_EL2, x3 +mrs x3, VTTBR_EL2 +msr VSTTBR_EL2, x3 +mrs x3, VSTTBR_EL2 + +// CHECK-ERROR: {{.*}}: error: expected writable system register or pstate +// CHECK-ERROR-NEXT: msr TTBR0_EL2, x3 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: {{.*}}: error: expected readable system register +// CHECK-ERROR-NEXT: mrs x3, TTBR0_EL2 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: {{.*}}: error: expected writable system register or pstate +// CHECK-ERROR-NEXT: msr VTTBR_EL2, x3 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: {{.*}}: error: expected readable system register +// CHECK-ERROR-NEXT: mrs x3, VTTBR_EL2 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: {{.*}}: error: expected writable system register or pstate +// CHECK-ERROR-NEXT: msr VSTTBR_EL2, x3 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: {{.*}}: error: expected readable system register +// CHECK-ERROR-NEXT: mrs x3, VSTTBR_EL2 +// CHECK-ERROR-NEXT: ^ Index: llvm/test/MC/AArch64/basic-a64-instructions.s =================================================================== --- llvm/test/MC/AArch64/basic-a64-instructions.s +++ llvm/test/MC/AArch64/basic-a64-instructions.s @@ -1694,27 +1694,21 @@ // CHECK: svc #{{65535|0xffff}} // encoding: [0xe1,0xff,0x1f,0xd4] hvc #1 - smc #12000 brk #12 hlt #123 // CHECK: hvc #{{1|0x1}} // encoding: [0x22,0x00,0x00,0xd4] -// CHECK: smc #{{12000|0x2ee0}} // encoding: [0x03,0xdc,0x05,0xd4] // CHECK: brk #{{12|0xc}} // encoding: [0x80,0x01,0x20,0xd4] // CHECK: hlt #{{123|0x7b}} // encoding: [0x60,0x0f,0x40,0xd4] dcps1 #42 dcps2 #9 - dcps3 #1000 // CHECK: dcps1 #{{42|0x2a}} // encoding: [0x41,0x05,0xa0,0xd4] // CHECK: dcps2 #{{9|0x9}} // encoding: [0x22,0x01,0xa0,0xd4] -// CHECK: dcps3 #{{1000|0x3e8}} // encoding: [0x03,0x7d,0xa0,0xd4] dcps1 dcps2 - dcps3 // CHECK: dcps1 // encoding: [0x01,0x00,0xa0,0xd4] // CHECK: dcps2 // encoding: [0x02,0x00,0xa0,0xd4] -// CHECK: dcps3 // encoding: [0x03,0x00,0xa0,0xd4] //------------------------------------------------------------------------------ // Extract (immediate) @@ -3785,13 +3779,11 @@ msr HACR_EL2, x12 msr MDCR_EL3, x12 msr TTBR0_EL1, x12 - msr TTBR0_EL2, x12 msr TTBR0_EL3, x12 msr TTBR1_EL1, x12 msr TCR_EL1, x12 msr TCR_EL2, x12 msr TCR_EL3, x12 - msr VTTBR_EL2, x12 msr VTCR_EL2, x12 msr DACR32_EL2, x12 msr SPSR_EL1, x12 @@ -4039,13 +4031,11 @@ // CHECK: msr {{hacr_el2|HACR_EL2}}, x12 // encoding: [0xec,0x11,0x1c,0xd5] // CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 // encoding: [0x2c,0x13,0x1e,0xd5] // CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 // encoding: [0x0c,0x20,0x18,0xd5] -// CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 // encoding: [0x0c,0x20,0x1c,0xd5] // CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 // encoding: [0x0c,0x20,0x1e,0xd5] // CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 // encoding: [0x2c,0x20,0x18,0xd5] // CHECK: msr {{tcr_el1|TCR_EL1}}, x12 // encoding: [0x4c,0x20,0x18,0xd5] // CHECK: msr {{tcr_el2|TCR_EL2}}, x12 // encoding: [0x4c,0x20,0x1c,0xd5] // CHECK: msr {{tcr_el3|TCR_EL3}}, x12 // encoding: [0x4c,0x20,0x1e,0xd5] -// CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 // encoding: [0x0c,0x21,0x1c,0xd5] // CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 // encoding: [0x4c,0x21,0x1c,0xd5] // CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 // encoding: [0x0c,0x30,0x1c,0xd5] // CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 // encoding: [0x0c,0x40,0x18,0xd5] @@ -4334,13 +4324,11 @@ mrs x9, HACR_EL2 mrs x9, MDCR_EL3 mrs x9, TTBR0_EL1 - mrs x9, TTBR0_EL2 mrs x9, TTBR0_EL3 mrs x9, TTBR1_EL1 mrs x9, TCR_EL1 mrs x9, TCR_EL2 mrs x9, TCR_EL3 - mrs x9, VTTBR_EL2 mrs x9, VTCR_EL2 mrs x9, DACR32_EL2 mrs x9, SPSR_EL1 @@ -4637,13 +4625,11 @@ // CHECK: mrs x9, {{hacr_el2|HACR_EL2}} // encoding: [0xe9,0x11,0x3c,0xd5] // CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} // encoding: [0x29,0x13,0x3e,0xd5] // CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} // encoding: [0x09,0x20,0x38,0xd5] -// CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} // encoding: [0x09,0x20,0x3c,0xd5] // CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} // encoding: [0x09,0x20,0x3e,0xd5] // CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} // encoding: [0x29,0x20,0x38,0xd5] // CHECK: mrs x9, {{tcr_el1|TCR_EL1}} // encoding: [0x49,0x20,0x38,0xd5] // CHECK: mrs x9, {{tcr_el2|TCR_EL2}} // encoding: [0x49,0x20,0x3c,0xd5] // CHECK: mrs x9, {{tcr_el3|TCR_EL3}} // encoding: [0x49,0x20,0x3e,0xd5] -// CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} // encoding: [0x09,0x21,0x3c,0xd5] // CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} // encoding: [0x49,0x21,0x3c,0xd5] // CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} // encoding: [0x09,0x30,0x3c,0xd5] // CHECK: mrs x9, {{spsr_el1|SPSR_EL1}} // encoding: [0x09,0x40,0x38,0xd5] Index: llvm/test/MC/AArch64/ras-extension.s =================================================================== --- llvm/test/MC/AArch64/ras-extension.s +++ llvm/test/MC/AArch64/ras-extension.s @@ -2,6 +2,8 @@ // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a75 < %s | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=tsv110 < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-r82 < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r < %s | FileCheck %s esb // CHECK: esb // encoding: [0x1f,0x22,0x03,0xd5] Index: llvm/test/MC/Disassembler/AArch64/arm64-branch.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/arm64-branch.txt +++ llvm/test/MC/Disassembler/AArch64/arm64-branch.txt @@ -29,14 +29,10 @@ # CHECK: dcps1 #0x2 0x62 0x00 0xa0 0xd4 # CHECK: dcps2 #0x3 - 0x83 0x00 0xa0 0xd4 -# CHECK: dcps3 #0x4 0xa0 0x00 0x40 0xd4 # CHECK: hlt #0x5 0xc2 0x00 0x00 0xd4 # CHECK: hvc #0x6 - 0xe3 0x00 0x00 0xd4 -# CHECK: smc #0x7 0x01 0x01 0x00 0xd4 # CHECK: svc #0x8 Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-complex.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.3a-complex.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.3a-complex.txt @@ -1,6 +1,7 @@ # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK # RUN: FileCheck %s < %t --check-prefix=NO-FP16 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,+fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.3a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A ###### FCMLA vector Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-js.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.3a-js.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.3a-js.txt @@ -1,3 +1,4 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s # CHECK: fjcvtzs w0, d0 [0x00,0x00,0x7e,0x1e] Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt @@ -1,5 +1,7 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a -mattr=+rcpc --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-r82 --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a65 --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a65ae --disassemble < %s | FileCheck %s Index: llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84 [0x5f,0x41,0x03,0xd5] Index: llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s [0x1f,0x40,0x00,0xd5] [0x2d,0x08,0x00,0x3a] Index: llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s 0xa0,0x54,0x18,0xd5 0xa0,0x54,0x38,0xd5 Index: llvm/test/MC/Disassembler/AArch64/armv8.4a-tlb.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.4a-tlb.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.4a-tlb.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOV84 # Outer shareable TLB Maintenance instructions: Index: llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84 [0x20,0x12,0x18,0xd5] Index: llvm/test/MC/Disassembler/AArch64/armv8.4a-virt.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.4a-virt.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.4a-virt.txt @@ -1,4 +1,5 @@ -# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s --check-prefixes=CHECK,V8A +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s --check-prefixes=CHECK,V8R 0x40,0x26,0x1c,0xd5 0x40,0x26,0x3c,0xd5 @@ -21,8 +22,13 @@ #CHECK: msr VSTCR_EL2, x0 #CHECK: mrs x0, VSTCR_EL2 -#CHECK: msr VSTTBR_EL2, x0 -#CHECK: mrs x0, VSTTBR_EL2 + +#V8A: msr VSTTBR_EL2, x0 +#V8A: mrs x0, VSTTBR_EL2 + +#V8R: msr S3_4_C2_C6_0, x0 +#V8R: mrs x0, S3_4_C2_C6_0 + #CHECK: msr SDER32_EL2, x12 #CHECK: mrs x12, SDER32_EL2 #CHECK: msr CNTHVS_TVAL_EL2, x0 Index: llvm/test/MC/Disassembler/AArch64/armv8.5a-predres.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.5a-predres.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.5a-predres.txt @@ -1,5 +1,6 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+predres -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=-predres -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB [0x80 0x73 0x0b 0xd5] Index: llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt @@ -1,5 +1,6 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+specrestrict -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=-specrestrict -disassemble < %s | FileCheck %s --check-prefix=NOSPECID [0x81 0x03 0x38 0xd5] Index: llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt +++ llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt @@ -2,6 +2,7 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76 -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76ae -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=-ssbs -disassemble < %s | FileCheck %s --check-prefix=NOSPECID [0x3f 0x41 0x03 0xd5] Index: llvm/test/MC/Disassembler/AArch64/armv8a-el3.txt =================================================================== --- /dev/null +++ llvm/test/MC/Disassembler/AArch64/armv8a-el3.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc -triple=aarch64 -mattr=+v8a -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+el3 -disassemble < %s | FileCheck %s + +# CHECK: smc #{{12000|0x2ee0}} +# CHECK: dcps3 #{{1000|0x3e8}} +# CHECK: dcps3 + +0x3 0xdc 0x5 0xd4 +0x3 0x7d 0xa0 0xd4 +0x3 0x0 0xa0 0xd4 Index: llvm/test/MC/Disassembler/AArch64/armv8a-fpmul.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/armv8a-fpmul.txt +++ llvm/test/MC/Disassembler/AArch64/armv8a-fpmul.txt @@ -1,5 +1,6 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-fullfp16,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16 +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16 #A fullfp16 instruction, for testing the interaction of the features [0x41,0x08,0xe3,0x1e] Index: llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -1257,27 +1257,21 @@ 0xe1 0xff 0x1f 0xd4 # CHECK: hvc #{{1|0x1}} -# CHECK: smc #{{12000|0x2ee0}} # CHECK: brk #{{12|0xc}} # CHECK: hlt #{{123|0x7b}} 0x22 0x0 0x0 0xd4 -0x3 0xdc 0x5 0xd4 0x80 0x1 0x20 0xd4 0x60 0xf 0x40 0xd4 # CHECK: dcps1 #{{42|0x2a}} # CHECK: dcps2 #{{9|0x9}} -# CHECK: dcps3 #{{1000|0x3e8}} 0x41 0x5 0xa0 0xd4 0x22 0x1 0xa0 0xd4 -0x3 0x7d 0xa0 0xd4 # CHECK: dcps1 # CHECK: dcps2 -# CHECK: dcps3 0x1 0x0 0xa0 0xd4 0x2 0x0 0xa0 0xd4 -0x3 0x0 0xa0 0xd4 #------------------------------------------------------------------------------ # Extract (immediate) @@ -3258,13 +3252,11 @@ # CHECK: msr {{hacr_el2|HACR_EL2}}, x12 # CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 # CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 -# CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 # CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 # CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 # CHECK: msr {{tcr_el1|TCR_EL1}}, x12 # CHECK: msr {{tcr_el2|TCR_EL2}}, x12 # CHECK: msr {{tcr_el3|TCR_EL3}}, x12 -# CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 # CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 # CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 # CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 @@ -3554,13 +3546,11 @@ # CHECK: mrs x9, {{hacr_el2|HACR_EL2}} # CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} # CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} -# CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} # CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} # CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} # CHECK: mrs x9, {{tcr_el1|TCR_EL1}} # CHECK: mrs x9, {{tcr_el2|TCR_EL2}} # CHECK: mrs x9, {{tcr_el3|TCR_EL3}} -# CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} # CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} # CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} # CHECK: mrs x9, {{spsr_el1|SPSR_EL1}}