diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3623,7 +3623,7 @@
   SDLoc DL(N);
 
   EVT WidenVT = TLI.getTypeToTransformTo(Ctx, N->getValueType(0));
-  unsigned WidenNumElts = WidenVT.getVectorNumElements();
+  ElementCount WidenEC = WidenVT.getVectorElementCount();
 
   EVT InVT = InOp.getValueType();
 
@@ -3643,14 +3643,14 @@
   }
 
   EVT InEltVT = InVT.getVectorElementType();
-  EVT InWidenVT = EVT::getVectorVT(Ctx, InEltVT, WidenNumElts);
-  unsigned InVTNumElts = InVT.getVectorNumElements();
+  EVT InWidenVT = EVT::getVectorVT(Ctx, InEltVT, WidenEC);
+  ElementCount InVTEC = InVT.getVectorElementCount();
 
   if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
     InOp = GetWidenedVector(N->getOperand(0));
     InVT = InOp.getValueType();
-    InVTNumElts = InVT.getVectorNumElements();
-    if (InVTNumElts == WidenNumElts) {
+    InVTEC = InVT.getVectorElementCount();
+    if (InVTEC == WidenEC) {
       if (N->getNumOperands() == 1)
         return DAG.getNode(Opcode, DL, WidenVT, InOp);
       return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
@@ -3674,9 +3674,10 @@
     // it an illegal type that might lead to repeatedly splitting the input
     // and then widening it. To avoid this, we widen the input only if
     // it results in a legal type.
-    if (WidenNumElts % InVTNumElts == 0) {
+    if (WidenEC.isKnownMultipleOf(InVTEC.getKnownMinValue())) {
       // Widen the input and call convert on the widened input vector.
-      unsigned NumConcat = WidenNumElts/InVTNumElts;
+      unsigned NumConcat =
+          WidenEC.getKnownMinValue() / InVTEC.getKnownMinValue();
       SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
       Ops[0] = InOp;
       SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
@@ -3685,7 +3686,7 @@
       return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
     }
 
-    if (InVTNumElts % WidenNumElts == 0) {
+    if (InVTEC.isKnownMultipleOf(WidenEC.getKnownMinValue())) {
       SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
                                   DAG.getVectorIdxConstant(0, DL));
       // Extract the input and convert the shorten input vector.
@@ -3697,7 +3698,7 @@
 
   // Otherwise unroll into some nasty scalar code and rebuild the vector.
   EVT EltVT = WidenVT.getVectorElementType();
-  SmallVector<SDValue, 16> Ops(WidenNumElts, DAG.getUNDEF(EltVT));
+  SmallVector<SDValue, 16> Ops(WidenEC.getFixedValue(), DAG.getUNDEF(EltVT));
   // Use the original element count so we don't do more scalar opts than
   // necessary.
   unsigned MinElts = N->getValueType(0).getVectorNumElements();
diff --git a/llvm/test/CodeGen/AArch64/sve-fcvt.ll b/llvm/test/CodeGen/AArch64/sve-fcvt.ll
--- a/llvm/test/CodeGen/AArch64/sve-fcvt.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fcvt.ll
@@ -15,6 +15,16 @@
   ret <vscale x 2 x float> %res
 }
 
+define <vscale x 3 x float> @fcvts_nxv3f16(<vscale x 3 x half> %a) {
+; CHECK-LABEL: fcvts_nxv3f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = fpext <vscale x 3 x half> %a to <vscale x 3 x float>
+  ret <vscale x 3 x float> %res
+}
+
 define <vscale x 4 x float> @fcvts_nxv4f16(<vscale x 4 x half> %a) {
 ; CHECK-LABEL: fcvts_nxv4f16:
 ; CHECK:       // %bb.0:
@@ -59,6 +69,16 @@
   ret <vscale x 2 x half> %res
 }
 
+define <vscale x 3 x half> @fcvth_nxv3f32(<vscale x 3 x float> %a) {
+; CHECK-LABEL: fcvth_nxv3f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = fptrunc <vscale x 3 x float> %a to <vscale x 3 x half>
+  ret <vscale x 3 x half> %res
+}
+
 define <vscale x 4 x half> @fcvth_nxv4f32(<vscale x 4 x float> %a) {
 ; CHECK-LABEL: fcvth_nxv4f32:
 ; CHECK:       // %bb.0:
@@ -143,6 +163,16 @@
   ret <vscale x 4 x i16> %res
 }
 
+define <vscale x 7 x i16> @fcvtzs_h_nxv7f16(<vscale x 7 x half> %a) {
+; CHECK-LABEL: fcvtzs_h_nxv7f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    fcvtzs z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = fptosi <vscale x 7 x half> %a to <vscale x 7 x i16>
+  ret <vscale x 7 x i16> %res
+}
+
 define <vscale x 8 x i16> @fcvtzs_h_nxv8f16(<vscale x 8 x half> %a) {
 ; CHECK-LABEL: fcvtzs_h_nxv8f16:
 ; CHECK:       // %bb.0:
@@ -193,6 +223,16 @@
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 3 x i32> @fcvtzs_s_nxv3f16(<vscale x 3 x half> %a) {
+; CHECK-LABEL: fcvtzs_s_nxv3f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = fptosi <vscale x 3 x half> %a to <vscale x 3 x i32>
+  ret <vscale x 3 x i32> %res
+}
+
 define <vscale x 4 x i32> @fcvtzs_s_nxv4f32(<vscale x 4 x float> %a) {
 ; CHECK-LABEL: fcvtzs_s_nxv4f32:
 ; CHECK:       // %bb.0:
@@ -289,6 +329,16 @@
   ret <vscale x 4 x i16> %res
 }
 
+define <vscale x 7 x i16> @fcvtzu_h_nxv7f16(<vscale x 7 x half> %a) {
+; CHECK-LABEL: fcvtzu_h_nxv7f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    fcvtzu z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = fptoui <vscale x 7 x half> %a to <vscale x 7 x i16>
+  ret <vscale x 7 x i16> %res
+}
+
 define <vscale x 8 x i16> @fcvtzu_h_nxv8f16(<vscale x 8 x half> %a) {
 ; CHECK-LABEL: fcvtzu_h_nxv8f16:
 ; CHECK:       // %bb.0:
@@ -329,6 +379,26 @@
   ret <vscale x 2 x i32> %res
 }
 
+define <vscale x 3 x i32> @fcvtzu_s_nxv3f16(<vscale x 3 x half> %a) {
+; CHECK-LABEL: fcvtzu_s_nxv3f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = fptoui <vscale x 3 x half> %a to <vscale x 3 x i32>
+  ret <vscale x 3 x i32> %res
+}
+
+define <vscale x 3 x i32> @fcvtzu_s_nxv3f32(<vscale x 3 x float> %a) {
+; CHECK-LABEL: fcvtzu_s_nxv3f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = fptoui <vscale x 3 x float> %a to <vscale x 3 x i32>
+  ret <vscale x 3 x i32> %res
+}
+
 define <vscale x 4 x i32> @fcvtzu_s_nxv4f16(<vscale x 4 x half> %a) {
 ; CHECK-LABEL: fcvtzu_s_nxv4f16:
 ; CHECK:       // %bb.0:
@@ -422,6 +492,27 @@
   ret <vscale x 2 x half> %res
 }
 
+define <vscale x 3 x half> @scvtf_h_nxv3i1(<vscale x 3 x i1> %a) {
+; CHECK-LABEL: scvtf_h_nxv3i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    scvtf z0.h, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = sitofp <vscale x 3 x i1> %a to <vscale x 3 x half>
+  ret <vscale x 3 x half> %res
+}
+
+define <vscale x 3 x half> @scvtf_h_nxv3i16(<vscale x 3 x i16> %a) {
+; CHECK-LABEL: scvtf_h_nxv3i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = sitofp <vscale x 3 x i16> %a to <vscale x 3 x half>
+  ret <vscale x 3 x half> %res
+}
+
 define <vscale x 4 x half> @scvtf_h_nxv4i1(<vscale x 4 x i1> %a) {
 ; CHECK-LABEL: scvtf_h_nxv4i1:
 ; CHECK:       // %bb.0:
@@ -453,6 +544,27 @@
   ret <vscale x 4 x half> %res
 }
 
+define <vscale x 7 x half> @scvtf_h_nxv7i1(<vscale x 7 x i1> %a) {
+; CHECK-LABEL: scvtf_h_nxv7i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = sitofp <vscale x 7 x i1> %a to <vscale x 7 x half>
+  ret <vscale x 7 x half> %res
+}
+
+define <vscale x 7 x half> @scvtf_h_nxv7i16(<vscale x 7 x i16> %a) {
+; CHECK-LABEL: scvtf_h_nxv7i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = sitofp <vscale x 7 x i16> %a to <vscale x 7 x half>
+  ret <vscale x 7 x half> %res
+}
+
 define <vscale x 8 x half> @scvtf_h_nxv8i1(<vscale x 8 x i1> %a) {
 ; CHECK-LABEL: scvtf_h_nxv8i1:
 ; CHECK:       // %bb.0:
@@ -505,6 +617,27 @@
   ret <vscale x 2 x float> %res
 }
 
+define <vscale x 3 x float> @scvtf_s_nxv3i1(<vscale x 3 x i1> %a) {
+; CHECK-LABEL: scvtf_s_nxv3i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = sitofp <vscale x 3 x i1> %a to <vscale x 3 x float>
+  ret <vscale x 3 x float> %res
+}
+
+define <vscale x 3 x float> @scvtf_s_nxv3i32(<vscale x 3 x i32> %a) {
+; CHECK-LABEL: scvtf_s_nxv3i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = sitofp <vscale x 3 x i32> %a to <vscale x 3 x float>
+  ret <vscale x 3 x float> %res
+}
+
 define <vscale x 4 x float> @scvtf_s_nxv4i1(<vscale x 4 x i1> %a) {
 ; CHECK-LABEL: scvtf_s_nxv4i1:
 ; CHECK:       // %bb.0:
@@ -600,6 +733,37 @@
   ret <vscale x 2 x half> %res
 }
 
+define <vscale x 3 x half> @ucvtf_h_nxv3i1(<vscale x 3 x i1> %a) {
+; CHECK-LABEL: ucvtf_h_nxv3i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.s, p0/z, #1 // =0x1
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = uitofp <vscale x 3 x i1> %a to <vscale x 3 x half>
+  ret <vscale x 3 x half> %res
+}
+
+define <vscale x 3 x half> @ucvtf_h_nxv3i16(<vscale x 3 x i16> %a) {
+; CHECK-LABEL: ucvtf_h_nxv3i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = uitofp <vscale x 3 x i16> %a to <vscale x 3 x half>
+  ret <vscale x 3 x half> %res
+}
+
+define <vscale x 3 x half> @ucvtf_h_nxv3i32(<vscale x 3 x i32> %a) {
+; CHECK-LABEL: ucvtf_h_nxv3i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = uitofp <vscale x 3 x i32> %a to <vscale x 3 x half>
+  ret <vscale x 3 x half> %res
+}
+
 define <vscale x 4 x half> @ucvtf_h_nxv4i1(<vscale x 4 x i1> %a) {
 ; CHECK-LABEL: ucvtf_h_nxv4i1:
 ; CHECK:       // %bb.0: