diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -1272,7 +1272,7 @@ // Print a label for the basic block. emitBasicBlockStart(MBB); DenseMap MnemonicCounts; - for (auto &MI : MBB) { + for (auto &MI : MBB.instrs()) { // Print the assembly for the instruction. if (!MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() && !MI.isDebugInstr()) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -239,91 +239,86 @@ MI->print(errs()); } - if (MI->isBundle()) { - const MachineBasicBlock *MBB = MI->getParent(); - MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); - while (I != MBB->instr_end() && I->isInsideBundle()) { - emitInstruction(&*I); - ++I; - } - } else { - // We don't want these pseudo instructions encoded. They are - // placeholder terminator instructions and should only be printed as - // comments. - if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) { - if (isVerbose()) - OutStreamer->emitRawComment(" return to shader part epilog"); - return; - } + // Ignore the pseudo instruction + if (MI->isBundle()) + return; - if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) { - if (isVerbose()) - OutStreamer->emitRawComment(" wave barrier"); - return; - } + // We don't want these pseudo instructions encoded. They are + // placeholder terminator instructions and should only be printed as + // comments. + if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) { + if (isVerbose()) + OutStreamer->emitRawComment(" return to shader part epilog"); + return; + } - if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) { - if (isVerbose()) - OutStreamer->emitRawComment(" divergent unreachable"); - return; - } + if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) { + if (isVerbose()) + OutStreamer->emitRawComment(" wave barrier"); + return; + } - MCInst TmpInst; - MCInstLowering.lower(MI, TmpInst); - EmitToStreamer(*OutStreamer, TmpInst); + if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) { + if (isVerbose()) + OutStreamer->emitRawComment(" divergent unreachable"); + return; + } + + MCInst TmpInst; + MCInstLowering.lower(MI, TmpInst); + EmitToStreamer(*OutStreamer, TmpInst); #ifdef EXPENSIVE_CHECKS - // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot - // work correctly for the generic CPU). - // - // The isPseudo check really shouldn't be here, but unfortunately there are - // some negative lit tests that depend on being able to continue through - // here even when pseudo instructions haven't been lowered. - // - // We also overestimate branch sizes with the offset bug. - if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) && - (!STI.hasOffset3fBug() || !MI->isBranch())) { - SmallVector Fixups; - SmallVector CodeBytes; - raw_svector_ostream CodeStream(CodeBytes); - - std::unique_ptr InstEmitter(createSIMCCodeEmitter( - *STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext)); - InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI); - - assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI)); - } + // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot + // work correctly for the generic CPU). + // + // The isPseudo check really shouldn't be here, but unfortunately there are + // some negative lit tests that depend on being able to continue through + // here even when pseudo instructions haven't been lowered. + // + // We also overestimate branch sizes with the offset bug. + if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) && + (!STI.hasOffset3fBug() || !MI->isBranch())) { + SmallVector Fixups; + SmallVector CodeBytes; + raw_svector_ostream CodeStream(CodeBytes); + + std::unique_ptr InstEmitter(createSIMCCodeEmitter( + *STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext)); + InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI); + + assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI)); + } #endif - if (DumpCodeInstEmitter) { - // Disassemble instruction/operands to text - DisasmLines.resize(DisasmLines.size() + 1); - std::string &DisasmLine = DisasmLines.back(); - raw_string_ostream DisasmStream(DisasmLine); - - AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(), - *STI.getRegisterInfo()); - InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream); - - // Disassemble instruction/operands to hex representation. - SmallVector Fixups; - SmallVector CodeBytes; - raw_svector_ostream CodeStream(CodeBytes); - - DumpCodeInstEmitter->encodeInstruction( - TmpInst, CodeStream, Fixups, MF->getSubtarget()); - HexLines.resize(HexLines.size() + 1); - std::string &HexLine = HexLines.back(); - raw_string_ostream HexStream(HexLine); - - for (size_t i = 0; i < CodeBytes.size(); i += 4) { - unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; - HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); - } - - DisasmStream.flush(); - DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); + if (DumpCodeInstEmitter) { + // Disassemble instruction/operands to text + DisasmLines.resize(DisasmLines.size() + 1); + std::string &DisasmLine = DisasmLines.back(); + raw_string_ostream DisasmStream(DisasmLine); + + AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(), + *STI.getRegisterInfo()); + InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream); + + // Disassemble instruction/operands to hex representation. + SmallVector Fixups; + SmallVector CodeBytes; + raw_svector_ostream CodeStream(CodeBytes); + + DumpCodeInstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, + MF->getSubtarget()); + HexLines.resize(HexLines.size() + 1); + std::string &HexLine = HexLines.back(); + raw_string_ostream HexStream(HexLine); + + for (size_t i = 0; i < CodeBytes.size(); i += 4) { + unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; + HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); } + + DisasmStream.flush(); + DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); } } diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -755,6 +755,9 @@ for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII) if (!MII->isDebugInstr() && !MII->isImplicitDef()) HexagonLowerToMC(MCII, &*MII, MCB, *this); + } else if (MI->isInsideBundle()) { + // Already handled when the bundle was emitted + return; } else { HexagonLowerToMC(MCII, MI, MCB, *this); } diff --git a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp --- a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp +++ b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp @@ -195,17 +195,12 @@ } void LanaiAsmPrinter::emitInstruction(const MachineInstr *MI) { - MachineBasicBlock::const_instr_iterator I = MI->getIterator(); - MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); - - do { - if (I->isCall()) { - emitCallInstruction(&*I); - continue; - } + if (MI->isCall()) { + emitCallInstruction(MI); + return; + } - customEmitInstruction(&*I); - } while ((++I != E) && I->isInsideBundle()); + customEmitInstruction(MI); } // isBlockOnlyReachableByFallthough - Return true if the basic block has diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -249,43 +249,38 @@ emitDirectiveRelocJalr(*MI, OutContext, TM, *OutStreamer, *Subtarget); } - MachineBasicBlock::const_instr_iterator I = MI->getIterator(); - MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); - - do { - // Do any auto-generated pseudo lowerings. - if (emitPseudoExpansionLowering(*OutStreamer, &*I)) - continue; - - // Skip the BUNDLE pseudo instruction and lower the contents - if (I->isBundle()) - continue; - - if (I->getOpcode() == Mips::PseudoReturn || - I->getOpcode() == Mips::PseudoReturn64 || - I->getOpcode() == Mips::PseudoIndirectBranch || - I->getOpcode() == Mips::PseudoIndirectBranch64 || - I->getOpcode() == Mips::TAILCALLREG || - I->getOpcode() == Mips::TAILCALLREG64) { - emitPseudoIndirectBranch(*OutStreamer, &*I); - continue; - } + // Do any auto-generated pseudo lowerings. + if (emitPseudoExpansionLowering(*OutStreamer, MI)) + return; - // The inMips16Mode() test is not permanent. - // Some instructions are marked as pseudo right now which - // would make the test fail for the wrong reason but - // that will be fixed soon. We need this here because we are - // removing another test for this situation downstream in the - // callchain. - // - if (I->isPseudo() && !Subtarget->inMips16Mode() - && !isLongBranchPseudo(I->getOpcode())) - llvm_unreachable("Pseudo opcode found in emitInstruction()"); - - MCInst TmpInst0; - MCInstLowering.Lower(&*I, TmpInst0); - EmitToStreamer(*OutStreamer, TmpInst0); - } while ((++I != E) && I->isInsideBundle()); // Delay slot check + // Skip the BUNDLE pseudo instruction and lower the contents + if (MI->isBundle()) + return; + + if (MI->getOpcode() == Mips::PseudoReturn || + MI->getOpcode() == Mips::PseudoReturn64 || + MI->getOpcode() == Mips::PseudoIndirectBranch || + MI->getOpcode() == Mips::PseudoIndirectBranch64 || + MI->getOpcode() == Mips::TAILCALLREG || + MI->getOpcode() == Mips::TAILCALLREG64) { + emitPseudoIndirectBranch(*OutStreamer, MI); + return; + } + + // The inMips16Mode() test is not permanent. + // Some instructions are marked as pseudo right now which + // would make the test fail for the wrong reason but + // that will be fixed soon. We need this here because we are + // removing another test for this situation downstream in the + // callchain. + // + if (MI->isPseudo() && !Subtarget->inMips16Mode() && + !isLongBranchPseudo(MI->getOpcode())) + llvm_unreachable("Pseudo opcode found in emitInstruction()"); + + MCInst TmpInst0; + MCInstLowering.Lower(MI, TmpInst0); + EmitToStreamer(*OutStreamer, TmpInst0); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp --- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -260,13 +260,9 @@ LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo()); return; } - MachineBasicBlock::const_instr_iterator I = MI->getIterator(); - MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); - do { - MCInst TmpInst; - LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this); - EmitToStreamer(*OutStreamer, TmpInst); - } while ((++I != E) && I->isInsideBundle()); // Delay slot check. + MCInst TmpInst; + LowerSparcMachineInstrToMCInst(MI, TmpInst, *this); + EmitToStreamer(*OutStreamer, TmpInst); } void SparcAsmPrinter::emitFunctionBodyStart() { diff --git a/llvm/lib/Target/VE/VEAsmPrinter.cpp b/llvm/lib/Target/VE/VEAsmPrinter.cpp --- a/llvm/lib/Target/VE/VEAsmPrinter.cpp +++ b/llvm/lib/Target/VE/VEAsmPrinter.cpp @@ -343,13 +343,9 @@ return; } - MachineBasicBlock::const_instr_iterator I = MI->getIterator(); - MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); - do { - MCInst TmpInst; - LowerVEMachineInstrToMCInst(&*I, TmpInst, *this); - EmitToStreamer(*OutStreamer, TmpInst); - } while ((++I != E) && I->isInsideBundle()); // Delay slot check. + MCInst TmpInst; + LowerVEMachineInstrToMCInst(MI, TmpInst, *this); + EmitToStreamer(*OutStreamer, TmpInst); } void VEAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll --- a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll +++ b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll @@ -145,7 +145,7 @@ ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: image_gather4_c_b_cl v[0:3], [v45, v44, v43, v42, v41], s[36:43], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D -; GFX10: buffer_load_dword v45, off, s[0:3], s33{{$}} +; GFX10: buffer_load_dword v45, off, s[0:3], s33 ; 4-byte Folded Reload{{$}} ; GFX10-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:4 ; GFX10-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:8 ; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:12 diff --git a/llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll b/llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll --- a/llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll @@ -45,16 +45,19 @@ ; CHECK-NEXT: r2 = add(r29,#2048) ; CHECK-NEXT: memd(r30+#-16) = r19:18 ; CHECK-NEXT: } // 8-byte Folded Spill +; CHECK-NEXT: // 8-byte Folded Spill ; CHECK-NEXT: { ; CHECK-NEXT: q0 = vand(v0,r0) ; CHECK-NEXT: r18 = ##-2147483648 ; CHECK-NEXT: vmem(r2+#-7) = v0 -; CHECK-NEXT: } // 128-byte Folded Spill +; CHECK-NEXT: } // 8-byte Folded Spill +; CHECK-NEXT: // 128-byte Folded Spill ; CHECK-NEXT: { ; CHECK-NEXT: v0 = vand(q0,r17) ; CHECK-NEXT: r0 = ##g1 ; CHECK-NEXT: memd(r30+#-24) = r21:20 -; CHECK-NEXT: } // 8-byte Folded Spill +; CHECK-NEXT: } // 128-byte Folded Spill +; CHECK-NEXT: // 8-byte Folded Spill ; CHECK-NEXT: { ; CHECK-NEXT: r19 = ##g0+128 ; CHECK-NEXT: vmem(r2+#-6) = v0 @@ -66,7 +69,8 @@ ; CHECK-NEXT: } // 128-byte Folded Spill ; CHECK-NEXT: { ; CHECK-NEXT: vmem(r29+#6) = v2 -; CHECK-NEXT: } // 256-byte Folded Spill +; CHECK-NEXT: } // 128-byte Folded Spill +; CHECK-NEXT: // 256-byte Folded Spill ; CHECK-NEXT: { ; CHECK-NEXT: v31:30.uw = vrmpy(v3:2.ub,r18.ub,#0) ; CHECK-NEXT: vmem(r29+#7) = v3 @@ -92,6 +96,7 @@ ; CHECK-NEXT: { ; CHECK-NEXT: vmem(r29+#3) = v1 ; CHECK-NEXT: } // 256-byte Folded Spill +; CHECK-NEXT: // 256-byte Folded Spill ; CHECK-NEXT: { ; CHECK-NEXT: v1:0.uw = vrmpy(v1:0.ub,r17.ub,#0) ; CHECK-NEXT: vmem(r19+#0) = v1.new @@ -107,6 +112,7 @@ ; CHECK-NEXT: { ; CHECK-NEXT: v1 = vmem(r29+#3) ; CHECK-NEXT: } // 256-byte Folded Reload +; CHECK-NEXT: // 256-byte Folded Reload ; CHECK-NEXT: { ; CHECK-NEXT: v1:0.uw = vrmpy(v1:0.ub,r0.ub,#1) ; CHECK-NEXT: r0 = ##g3 @@ -137,6 +143,7 @@ ; CHECK-NEXT: { ; CHECK-NEXT: v1 = vmem(r29+#7) ; CHECK-NEXT: } // 256-byte Folded Reload +; CHECK-NEXT: // 256-byte Folded Reload ; CHECK-NEXT: { ; CHECK-NEXT: v1:0.uw = vrmpy(v1:0.ub,r0.ub,#1) ; CHECK-NEXT: vmem(r19+#0) = v1.new @@ -152,6 +159,7 @@ ; CHECK-NEXT: { ; CHECK-NEXT: v0 = vmem(r0+#-7) ; CHECK-NEXT: } // 128-byte Folded Reload +; CHECK-NEXT: // 128-byte Folded Reload ; CHECK-NEXT: { ; CHECK-NEXT: v1:0.h = vadd(v0.ub,v1.ub) ; CHECK-NEXT: } @@ -164,6 +172,7 @@ ; CHECK-NEXT: r19:18 = memd(r30+#-16) ; CHECK-NEXT: vmem(r20+#0) = v0 ; CHECK-NEXT: } // 8-byte Folded Reload +; CHECK-NEXT: // 8-byte Folded Reload ; CHECK-NEXT: { ; CHECK-NEXT: r21:20 = memd(r30+#-24) ; CHECK-NEXT: r31:30 = dealloc_return(r30):raw diff --git a/llvm/test/DebugInfo/Mips/dbg-call-site-low-pc.ll b/llvm/test/DebugInfo/Mips/dbg-call-site-low-pc.ll --- a/llvm/test/DebugInfo/Mips/dbg-call-site-low-pc.ll +++ b/llvm/test/DebugInfo/Mips/dbg-call-site-low-pc.ll @@ -22,7 +22,7 @@ ;; Test mips, mipsel, mips64, mips64el: ; CHECK: DW_TAG_GNU_call_site ; CHECK-NEXT: DW_AT_abstract_origin {{.*}} "f1" -; CHECK-NEXT: DW_AT_low_pc (0x{{(00000000)?}}00000010) +; CHECK-NEXT: DW_AT_low_pc (0x{{(00000000)?}}0000000c) ; ModuleID = 'm.c' source_filename = "m.c"