Index: include/clang/Basic/DiagnosticParseKinds.td =================================================================== --- include/clang/Basic/DiagnosticParseKinds.td +++ include/clang/Basic/DiagnosticParseKinds.td @@ -358,6 +358,10 @@ "'%0' declaration specifier not allowed here">; def err_invalid_vector_bool_decl_spec : Error< "cannot use '%0' with '__vector bool'">; +def err_invalid_vector_long_decl_spec : Error< + "cannot use 'long' with '__vector'">; +def err_invalid_vector_float_decl_spec : Error< + "cannot use 'float' with '__vector'">; def err_invalid_vector_double_decl_spec : Error < "use of 'double' with '__vector' requires VSX support to be enabled " "(available on POWER7 or later)">; Index: include/clang/Basic/LangOptions.def =================================================================== --- include/clang/Basic/LangOptions.def +++ include/clang/Basic/LangOptions.def @@ -104,6 +104,7 @@ LANGOPT(ConstStrings , 1, 0, "const-qualified string support") LANGOPT(LaxVectorConversions , 1, 1, "lax vector conversions") LANGOPT(AltiVec , 1, 0, "AltiVec-style vector initializers") +LANGOPT(ZVector , 1, 0, "System z vector extensions") LANGOPT(Exceptions , 1, 0, "exception handling") LANGOPT(ObjCExceptions , 1, 0, "Objective-C exceptions") LANGOPT(CXXExceptions , 1, 0, "C++ exceptions") Index: include/clang/Basic/TokenKinds.def =================================================================== --- include/clang/Basic/TokenKinds.def +++ include/clang/Basic/TokenKinds.def @@ -239,6 +239,8 @@ // KEYOPENCL - This is a keyword in OpenCL // KEYNOOPENCL - This is a keyword that is not supported in OpenCL // KEYALTIVEC - This is a keyword in AltiVec +// KEYZVECTOR - This is a keyword for the System z vector extensions, +// which are heavily based on AltiVec // KEYBORLAND - This is a keyword if Borland extensions are enabled // BOOLSUPPORT - This is a keyword if 'bool' is a built-in type // HALFSUPPORT - This is a keyword if 'half' is a built-in type @@ -501,7 +503,7 @@ ALIAS("read_write", __read_write , KEYOPENCL) // OpenCL builtins KEYWORD(__builtin_astype , KEYOPENCL) -KEYWORD(vec_step , KEYOPENCL|KEYALTIVEC) +KEYWORD(vec_step , KEYOPENCL|KEYALTIVEC|KEYZVECTOR) // OpenMP Type Traits KEYWORD(__builtin_omp_required_simd_align, KEYALL) @@ -510,9 +512,9 @@ KEYWORD(__pascal , KEYALL) // Altivec Extension. -KEYWORD(__vector , KEYALTIVEC) +KEYWORD(__vector , KEYALTIVEC|KEYZVECTOR) KEYWORD(__pixel , KEYALTIVEC) -KEYWORD(__bool , KEYALTIVEC) +KEYWORD(__bool , KEYALTIVEC|KEYZVECTOR) // ARM NEON extensions. ALIAS("__fp16", half , KEYALL) Index: include/clang/Driver/Options.td =================================================================== --- include/clang/Driver/Options.td +++ include/clang/Driver/Options.td @@ -1327,6 +1327,13 @@ def mvx : Flag<["-"], "mvx">, Group; def mno_vx : Flag<["-"], "mno-vx">, Group; +def fzvector : Flag<["-"], "fzvector">, Group, Flags<[CC1Option]>, + HelpText<"Enable System z vector language extension">; +def fno_zvector : Flag<["-"], "fno-zvector">, Group, + Flags<[CC1Option]>; +def mzvector : Flag<["-"], "mzvector">, Alias; +def mno_zvector : Flag<["-"], "mno-zvector">, Alias; + def mno_warn_nonportable_cfstrings : Flag<["-"], "mno-warn-nonportable-cfstrings">, Group; def mno_omit_leaf_frame_pointer : Flag<["-"], "mno-omit-leaf-frame-pointer">, Group; def momit_leaf_frame_pointer : Flag<["-"], "momit-leaf-frame-pointer">, Group, Index: include/clang/Parse/Parser.h =================================================================== --- include/clang/Parse/Parser.h +++ include/clang/Parse/Parser.h @@ -108,12 +108,13 @@ /// Ident_super - IdentifierInfo for "super", to support fast /// comparison. IdentifierInfo *Ident_super; - /// Ident_vector, Ident_pixel, Ident_bool - cached IdentifierInfo's - /// for "vector", "pixel", and "bool" fast comparison. Only present - /// if AltiVec enabled. + /// Ident_vector, Ident_bool - cached IdentifierInfos for "vector" and + /// "bool" fast comparison. Only present if AltiVec or ZVector are enabled. IdentifierInfo *Ident_vector; - IdentifierInfo *Ident_pixel; IdentifierInfo *Ident_bool; + /// Ident_pixel - cached cached IdentifierInfos for "pixel" fast comparison. + /// Only present if AltiVec enabled. + IdentifierInfo *Ident_pixel; /// Objective-C contextual keywords. mutable IdentifierInfo *Ident_instancetype; @@ -605,10 +606,12 @@ bool TryAltiVecToken(DeclSpec &DS, SourceLocation Loc, const char *&PrevSpec, unsigned &DiagID, bool &isInvalid) { - if (!getLangOpts().AltiVec || - (Tok.getIdentifierInfo() != Ident_vector && - Tok.getIdentifierInfo() != Ident_pixel && - Tok.getIdentifierInfo() != Ident_bool)) + if (!getLangOpts().AltiVec && !getLangOpts().ZVector) + return false; + + if (Tok.getIdentifierInfo() != Ident_vector && + Tok.getIdentifierInfo() != Ident_bool && + (!getLangOpts().AltiVec || Tok.getIdentifierInfo() != Ident_pixel)) return false; return TryAltiVecTokenOutOfLine(DS, Loc, PrevSpec, DiagID, isInvalid); @@ -618,7 +621,7 @@ /// identifier token, replacing it with the non-context-sensitive __vector. /// This returns true if the token was replaced. bool TryAltiVecVectorToken() { - if (!getLangOpts().AltiVec || + if ((!getLangOpts().AltiVec && !getLangOpts().ZVector) || Tok.getIdentifierInfo() != Ident_vector) return false; return TryAltiVecVectorTokenOutOfLine(); } Index: include/clang/Sema/Sema.h =================================================================== --- include/clang/Sema/Sema.h +++ include/clang/Sema/Sema.h @@ -8362,7 +8362,8 @@ /// type checking for vector binary operators. QualType CheckVectorOperands(ExprResult &LHS, ExprResult &RHS, - SourceLocation Loc, bool IsCompAssign); + SourceLocation Loc, bool IsCompAssign, + bool AllowBothBool, bool AllowBoolConversion); QualType GetSignedVectorType(QualType V); QualType CheckVectorCompareOperands(ExprResult &LHS, ExprResult &RHS, SourceLocation Loc, bool isRelational); Index: lib/Basic/IdentifierTable.cpp =================================================================== --- lib/Basic/IdentifierTable.cpp +++ lib/Basic/IdentifierTable.cpp @@ -110,7 +110,8 @@ HALFSUPPORT = 0x08000, KEYCONCEPTS = 0x10000, KEYOBJC2 = 0x20000, - KEYALL = (0x3ffff & ~KEYNOMS18 & + KEYZVECTOR = 0x40000, + KEYALL = (0x7ffff & ~KEYNOMS18 & ~KEYNOOPENCL) // KEYNOMS18 and KEYNOOPENCL are used to exclude. }; Index: lib/Basic/Module.cpp =================================================================== --- lib/Basic/Module.cpp +++ lib/Basic/Module.cpp @@ -67,6 +67,7 @@ .Case("objc_arc", LangOpts.ObjCAutoRefCount) .Case("opencl", LangOpts.OpenCL) .Case("tls", Target.isTLSSupported()) + .Case("zvector", LangOpts.ZVector) .Default(Target.hasFeature(Feature)); if (!HasFeature) HasFeature = std::find(LangOpts.ModuleFeatures.begin(), Index: lib/Basic/Targets.cpp =================================================================== --- lib/Basic/Targets.cpp +++ lib/Basic/Targets.cpp @@ -5677,6 +5677,8 @@ Builder.defineMacro("__LONG_DOUBLE_128__"); if (HasTransactionalExecution) Builder.defineMacro("__HTM__"); + if (Opts.ZVector) + Builder.defineMacro("__VEC__", "10301"); } void getTargetBuiltins(const Builtin::Info *&Records, unsigned &NumRecords) const override { Index: lib/Driver/Tools.cpp =================================================================== --- lib/Driver/Tools.cpp +++ lib/Driver/Tools.cpp @@ -3913,9 +3913,11 @@ Args.AddLastArg(CmdArgs, options::OPT_fstandalone_debug); Args.AddLastArg(CmdArgs, options::OPT_fno_standalone_debug); Args.AddLastArg(CmdArgs, options::OPT_fno_operator_names); - // AltiVec language extensions aren't relevant for assembling. - if (!isa(JA) || Output.getType() != types::TY_PP_Asm) + // AltiVec-like language extensions aren't relevant for assembling. + if (!isa(JA) || Output.getType() != types::TY_PP_Asm) { Args.AddLastArg(CmdArgs, options::OPT_faltivec); + Args.AddLastArg(CmdArgs, options::OPT_fzvector); + } Args.AddLastArg(CmdArgs, options::OPT_fdiagnostics_show_template_tree); Args.AddLastArg(CmdArgs, options::OPT_fno_elide_type); @@ -3950,6 +3952,12 @@ << "ppc/ppc64/ppc64le"; } + // -fzvector is incompatible with -faltivec. + if (Arg *A = Args.getLastArg(options::OPT_fzvector)) + if (Args.hasArg(options::OPT_faltivec)) + D.Diag(diag::err_drv_argument_not_allowed_with) << A->getAsString(Args) + << "-faltivec"; + if (getToolChain().SupportsProfiling()) Args.AddLastArg(CmdArgs, options::OPT_pg); Index: lib/Frontend/CompilerInvocation.cpp =================================================================== --- lib/Frontend/CompilerInvocation.cpp +++ lib/Frontend/CompilerInvocation.cpp @@ -1256,6 +1256,7 @@ // OpenCL has some additional defaults. if (Opts.OpenCL) { Opts.AltiVec = 0; + Opts.ZVector = 0; Opts.CXXOperatorNames = 1; Opts.LaxVectorConversions = 0; Opts.DefaultFPContract = 1; @@ -1444,6 +1445,9 @@ if (Args.hasArg(OPT_faltivec)) Opts.AltiVec = 1; + if (Args.hasArg(OPT_fzvector)) + Opts.ZVector = 1; + if (Args.hasArg(OPT_pthread)) Opts.POSIXThreads = 1; Index: lib/Parse/Parser.cpp =================================================================== --- lib/Parse/Parser.cpp +++ lib/Parse/Parser.cpp @@ -476,11 +476,12 @@ Ident_super = &PP.getIdentifierTable().get("super"); - if (getLangOpts().AltiVec) { + if (getLangOpts().AltiVec || getLangOpts().ZVector) { Ident_vector = &PP.getIdentifierTable().get("vector"); - Ident_pixel = &PP.getIdentifierTable().get("pixel"); Ident_bool = &PP.getIdentifierTable().get("bool"); } + if (getLangOpts().AltiVec) + Ident_pixel = &PP.getIdentifierTable().get("pixel"); Ident_introduced = nullptr; Ident_deprecated = nullptr; Index: lib/Sema/DeclSpec.cpp =================================================================== --- lib/Sema/DeclSpec.cpp +++ lib/Sema/DeclSpec.cpp @@ -987,10 +987,11 @@ Diag(D, TSWLoc, diag::err_invalid_vector_bool_decl_spec) << getSpecifierName((TSW)TypeSpecWidth); - // vector bool long long requires VSX support. + // vector bool long long requires VSX support or ZVector. if ((TypeSpecWidth == TSW_longlong) && (!PP.getTargetInfo().hasFeature("vsx")) && - (!PP.getTargetInfo().hasFeature("power8-vector"))) + (!PP.getTargetInfo().hasFeature("power8-vector")) && + !PP.getLangOpts().ZVector) Diag(D, TSTLoc, diag::err_invalid_vector_long_long_decl_spec); // Elements of vector bool are interpreted as unsigned. (PIM 2.1) @@ -999,14 +1000,23 @@ TypeSpecSign = TSS_unsigned; } else if (TypeSpecType == TST_double) { // vector long double and vector long long double are never allowed. - // vector double is OK for Power7 and later. + // vector double is OK for Power7 and later, and ZVector. if (TypeSpecWidth == TSW_long || TypeSpecWidth == TSW_longlong) Diag(D, TSWLoc, diag::err_invalid_vector_long_double_decl_spec); - else if (!PP.getTargetInfo().hasFeature("vsx")) + else if (!PP.getTargetInfo().hasFeature("vsx") && + !PP.getLangOpts().ZVector) Diag(D, TSTLoc, diag::err_invalid_vector_double_decl_spec); + } else if (TypeSpecType == TST_float) { + // vector float is unsupported for ZVector. + if (PP.getLangOpts().ZVector) + Diag(D, TSTLoc, diag::err_invalid_vector_float_decl_spec); } else if (TypeSpecWidth == TSW_long) { - Diag(D, TSWLoc, diag::warn_vector_long_decl_spec_combination) - << getSpecifierName((TST)TypeSpecType, Policy); + // vector long is unsupported for ZVector and deprecated for AltiVec. + if (PP.getLangOpts().ZVector) + Diag(D, TSWLoc, diag::err_invalid_vector_long_decl_spec); + else + Diag(D, TSWLoc, diag::warn_vector_long_decl_spec_combination) + << getSpecifierName((TST)TypeSpecType, Policy); } if (TypeAltiVecPixel) { Index: lib/Sema/SemaExpr.cpp =================================================================== --- lib/Sema/SemaExpr.cpp +++ lib/Sema/SemaExpr.cpp @@ -5518,7 +5518,7 @@ // i.e. all the elements are integer constants. ParenExpr *PE = dyn_cast(CastExpr); ParenListExpr *PLE = dyn_cast(CastExpr); - if ((getLangOpts().AltiVec || getLangOpts().OpenCL) + if ((getLangOpts().AltiVec || getLangOpts().ZVector || getLangOpts().OpenCL) && castType->isVectorType() && (PE || PLE)) { if (PLE && PLE->getNumExprs() == 0) { Diag(PLE->getExprLoc(), diag::err_altivec_empty_initializer); @@ -6075,7 +6075,9 @@ if (LHS.get()->getType()->isVectorType() || RHS.get()->getType()->isVectorType()) { QualType VecResTy = S.CheckVectorOperands(LHS, RHS, QuestionLoc, - /*isCompAssign*/false); + /*isCompAssign*/false, + /*AllowBothBool*/true, + /*AllowBoolConversions*/false); if (VecResTy.isNull()) return QualType(); // The result type must match the condition type as specified in // OpenCL v1.1 s6.11.6. @@ -6126,7 +6128,9 @@ // Now check the two expressions. if (LHS.get()->getType()->isVectorType() || RHS.get()->getType()->isVectorType()) - return CheckVectorOperands(LHS, RHS, QuestionLoc, /*isCompAssign*/false); + return CheckVectorOperands(LHS, RHS, QuestionLoc, /*isCompAssign*/false, + /*AllowBothBool*/true, + /*AllowBoolConversions*/false); QualType ResTy = UsualArithmeticConversions(LHS, RHS); if (LHS.isInvalid() || RHS.isInvalid()) @@ -7267,7 +7271,9 @@ } QualType Sema::CheckVectorOperands(ExprResult &LHS, ExprResult &RHS, - SourceLocation Loc, bool IsCompAssign) { + SourceLocation Loc, bool IsCompAssign, + bool AllowBothBool, + bool AllowBoolConversions) { if (!IsCompAssign) { LHS = DefaultFunctionArrayLvalueConversion(LHS.get()); if (LHS.isInvalid()) @@ -7282,14 +7288,21 @@ QualType LHSType = LHS.get()->getType().getUnqualifiedType(); QualType RHSType = RHS.get()->getType().getUnqualifiedType(); - // If the vector types are identical, return. - if (Context.hasSameType(LHSType, RHSType)) - return LHSType; - const VectorType *LHSVecType = LHSType->getAs(); const VectorType *RHSVecType = RHSType->getAs(); assert(LHSVecType || RHSVecType); + // AltiVec-style "vector bool op vector bool" combinations are allowed + // for some operators but not others. + if (!AllowBothBool && + LHSVecType && LHSVecType->getVectorKind() == VectorType::AltiVecBool && + RHSVecType && RHSVecType->getVectorKind() == VectorType::AltiVecBool) + return InvalidOperands(Loc, LHS, RHS); + + // If the vector types are identical, return. + if (Context.hasSameType(LHSType, RHSType)) + return LHSType; + // If we have compatible AltiVec and GCC vector types, use the AltiVec type. if (LHSVecType && RHSVecType && Context.areCompatibleVectorTypes(LHSType, RHSType)) { @@ -7303,6 +7316,28 @@ return RHSType; } + // AllowBoolConversions says that bool and non-bool AltiVec vectors + // can be mixed, with the result being the non-bool type. The non-bool + // operand must have integer element type. + if (AllowBoolConversions && LHSVecType && RHSVecType && + LHSVecType->getNumElements() == RHSVecType->getNumElements() && + (Context.getTypeSize(LHSVecType->getElementType()) == + Context.getTypeSize(RHSVecType->getElementType()))) { + if (LHSVecType->getVectorKind() == VectorType::AltiVecVector && + LHSVecType->getElementType()->isIntegerType() && + RHSVecType->getVectorKind() == VectorType::AltiVecBool) { + RHS = ImpCastExprToType(RHS.get(), LHSType, CK_BitCast); + return LHSType; + } + if (!IsCompAssign && + LHSVecType->getVectorKind() == VectorType::AltiVecBool && + RHSVecType->getVectorKind() == VectorType::AltiVecVector && + RHSVecType->getElementType()->isIntegerType()) { + LHS = ImpCastExprToType(LHS.get(), RHSType, CK_BitCast); + return RHSType; + } + } + // If there's an ext-vector type and a scalar, try to convert the scalar to // the vector element type and splat. if (!RHSVecType && isa(LHSVecType)) { @@ -7391,7 +7426,9 @@ if (LHS.get()->getType()->isVectorType() || RHS.get()->getType()->isVectorType()) - return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign); + return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign, + /*AllowBothBool*/getLangOpts().AltiVec, + /*AllowBoolConversions*/false); QualType compType = UsualArithmeticConversions(LHS, RHS, IsCompAssign); if (LHS.isInvalid() || RHS.isInvalid()) @@ -7420,7 +7457,9 @@ RHS.get()->getType()->isVectorType()) { if (LHS.get()->getType()->hasIntegerRepresentation() && RHS.get()->getType()->hasIntegerRepresentation()) - return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign); + return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign, + /*AllowBothBool*/getLangOpts().AltiVec, + /*AllowBoolConversions*/false); return InvalidOperands(Loc, LHS, RHS); } @@ -7706,7 +7745,10 @@ if (LHS.get()->getType()->isVectorType() || RHS.get()->getType()->isVectorType()) { - QualType compType = CheckVectorOperands(LHS, RHS, Loc, CompLHSTy); + QualType compType = CheckVectorOperands( + LHS, RHS, Loc, CompLHSTy, + /*AllowBothBool*/getLangOpts().AltiVec, + /*AllowBoolConversions*/getLangOpts().ZVector); if (CompLHSTy) *CompLHSTy = compType; return compType; } @@ -7781,7 +7823,10 @@ if (LHS.get()->getType()->isVectorType() || RHS.get()->getType()->isVectorType()) { - QualType compType = CheckVectorOperands(LHS, RHS, Loc, CompLHSTy); + QualType compType = CheckVectorOperands( + LHS, RHS, Loc, CompLHSTy, + /*AllowBothBool*/getLangOpts().AltiVec, + /*AllowBoolConversions*/getLangOpts().ZVector); if (CompLHSTy) *CompLHSTy = compType; return compType; } @@ -8023,7 +8068,21 @@ RHS.get()->getType()->isVectorType()) { if (LangOpts.OpenCL) return checkOpenCLVectorShift(*this, LHS, RHS, Loc, IsCompAssign); - return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign); + if (LangOpts.ZVector) { + // The shift operators for the z vector extensions work basically + // like OpenCL shifts, except that neither the LHS nor the RHS is + // allowed to be a "vector bool". + if (auto LHSVecType = LHS.get()->getType()->getAs()) + if (LHSVecType->getVectorKind() == VectorType::AltiVecBool) + return InvalidOperands(Loc, LHS, RHS); + if (auto RHSVecType = RHS.get()->getType()->getAs()) + if (RHSVecType->getVectorKind() == VectorType::AltiVecBool) + return InvalidOperands(Loc, LHS, RHS); + return checkOpenCLVectorShift(*this, LHS, RHS, Loc, IsCompAssign); + } + return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign, + /*AllowBothBool*/true, + /*AllowBoolConversions*/false); } // Shifts don't perform usual arithmetic conversions, they just do integer @@ -8797,7 +8856,9 @@ bool IsRelational) { // Check to make sure we're operating on vectors of the same type and width, // Allowing one side to be a scalar of element type. - QualType vType = CheckVectorOperands(LHS, RHS, Loc, /*isCompAssign*/false); + QualType vType = CheckVectorOperands(LHS, RHS, Loc, /*isCompAssign*/false, + /*AllowBothBool*/true, + /*AllowBoolConversions*/getLangOpts().ZVector); if (vType.isNull()) return vType; @@ -8805,7 +8866,8 @@ // If AltiVec, the comparison results in a numeric type, i.e. // bool for C++, int for C - if (vType->getAs()->getVectorKind() == VectorType::AltiVecVector) + if (getLangOpts().AltiVec && + vType->getAs()->getVectorKind() == VectorType::AltiVecVector) return Context.getLogicalOperationType(); // For non-floating point types, check for self-comparisons of the form @@ -8839,7 +8901,9 @@ SourceLocation Loc) { // Ensure that either both operands are of the same vector type, or // one operand is of a vector type and the other is of its element type. - QualType vType = CheckVectorOperands(LHS, RHS, Loc, false); + QualType vType = CheckVectorOperands(LHS, RHS, Loc, false, + /*AllowBothBool*/true, + /*AllowBoolConversions*/false); if (vType.isNull()) return InvalidOperands(Loc, LHS, RHS); if (getLangOpts().OpenCL && getLangOpts().OpenCLVersion < 120 && @@ -8857,8 +8921,9 @@ RHS.get()->getType()->isVectorType()) { if (LHS.get()->getType()->hasIntegerRepresentation() && RHS.get()->getType()->hasIntegerRepresentation()) - return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign); - + return CheckVectorOperands(LHS, RHS, Loc, IsCompAssign, + /*AllowBothBool*/true, + /*AllowBoolConversions*/getLangOpts().ZVector); return InvalidOperands(Loc, LHS, RHS); } @@ -9472,6 +9537,10 @@ IsInc, IsPrefix); } else if (S.getLangOpts().AltiVec && ResType->isVectorType()) { // OK! ( C/C++ Language Extensions for CBEA(Version 2.6) 10.3 ) + } else if (S.getLangOpts().ZVector && ResType->isVectorType() && + (ResType->getAs()->getVectorKind() != + VectorType::AltiVecBool)) { + // The z vector extensions allow ++ and -- for non-bool vectors. } else if(S.getLangOpts().OpenCL && ResType->isVectorType() && ResType->getAs()->getElementType()->isIntegerType()) { // OpenCL V1.2 6.3 says dec/inc ops operate on integer vector types. @@ -10552,8 +10621,13 @@ resultType = Input.get()->getType(); if (resultType->isDependentType()) break; - if (resultType->isArithmeticType() || // C99 6.5.3.3p1 - resultType->isVectorType()) + if (resultType->isArithmeticType()) // C99 6.5.3.3p1 + break; + else if (resultType->isVectorType() && + // The z vector extensions don't allow + or - with bool vectors. + (!Context.getLangOpts().ZVector || + resultType->getAs()->getVectorKind() != + VectorType::AltiVecBool)) break; else if (getLangOpts().CPlusPlus && // C++ [expr.unary.op]p6 Opc == UO_Plus && Index: lib/Sema/SemaExprCXX.cpp =================================================================== --- lib/Sema/SemaExprCXX.cpp +++ lib/Sema/SemaExprCXX.cpp @@ -4950,7 +4950,9 @@ // Extension: conditional operator involving vector types. if (LTy->isVectorType() || RTy->isVectorType()) - return CheckVectorOperands(LHS, RHS, QuestionLoc, /*isCompAssign*/false); + return CheckVectorOperands(LHS, RHS, QuestionLoc, /*isCompAssign*/false, + /*AllowBothBool*/true, + /*AllowBoolConversions*/false); // -- The second and third operands have arithmetic or enumeration type; // the usual arithmetic conversions are performed to bring them to a Index: lib/Sema/SemaLookup.cpp =================================================================== --- lib/Sema/SemaLookup.cpp +++ lib/Sema/SemaLookup.cpp @@ -4245,7 +4245,7 @@ // Don't try to correct the identifier "vector" when in AltiVec mode. // TODO: Figure out why typo correction misbehaves in this case, fix it, and // remove this workaround. - if (getLangOpts().AltiVec && Typo->isStr("vector")) + if ((getLangOpts().AltiVec || getLangOpts().ZVector) && Typo->isStr("vector")) return nullptr; // Provide a stop gap for files that are just seriously broken. Trying Index: test/CodeGen/zvector.c =================================================================== --- test/CodeGen/zvector.c +++ test/CodeGen/zvector.c @@ -0,0 +1,2798 @@ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 -fzvector \ +// RUN: -O -emit-llvm -o - -W -Wall -Werror %s | FileCheck %s + +volatile vector signed char sc, sc2; +volatile vector unsigned char uc, uc2; +volatile vector bool char bc, bc2; + +volatile vector signed short ss, ss2; +volatile vector unsigned short us, us2; +volatile vector bool short bs, bs2; + +volatile vector signed int si, si2; +volatile vector unsigned int ui, ui2; +volatile vector bool int bi, bi2; + +volatile vector signed long long sl, sl2; +volatile vector unsigned long long ul, ul2; +volatile vector bool long long bl, bl2; + +volatile vector double fd, fd2; + +volatile int cnt; + +void test_assign (void) +{ +// CHECK-LABEL: test_assign + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: store volatile <16 x i8> [[VAL]], <16 x i8>* @sc + sc = sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: store volatile <16 x i8> [[VAL]], <16 x i8>* @uc + uc = uc2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: store volatile <8 x i16> [[VAL]], <8 x i16>* @ss + ss = ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: store volatile <8 x i16> [[VAL]], <8 x i16>* @us + us = us2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: store volatile <4 x i32> [[VAL]], <4 x i32>* @si + si = si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: store volatile <4 x i32> [[VAL]], <4 x i32>* @ui + ui = ui2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: store volatile <2 x i64> [[VAL]], <2 x i64>* @sl + sl = sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: store volatile <2 x i64> [[VAL]], <2 x i64>* @ul + ul = ul2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: store volatile <2 x double> [[VAL]], <2 x double>* @fd + fd = fd2; +} + +void test_pos (void) +{ +// CHECK-LABEL: test_pos + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: store volatile <16 x i8> [[VAL]], <16 x i8>* @sc + sc = +sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: store volatile <16 x i8> [[VAL]], <16 x i8>* @uc + uc = +uc2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: store volatile <8 x i16> [[VAL]], <8 x i16>* @ss + ss = +ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: store volatile <8 x i16> [[VAL]], <8 x i16>* @us + us = +us2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: store volatile <4 x i32> [[VAL]], <4 x i32>* @si + si = +si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: store volatile <4 x i32> [[VAL]], <4 x i32>* @ui + ui = +ui2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: store volatile <2 x i64> [[VAL]], <2 x i64>* @sl + sl = +sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: store volatile <2 x i64> [[VAL]], <2 x i64>* @ul + ul = +ul2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: store volatile <2 x double> [[VAL]], <2 x double>* @fd + fd = +fd2; +} + +void test_neg (void) +{ +// CHECK-LABEL: test_neg + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = sub <16 x i8> zeroinitializer, [[VAL]] + sc = -sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = sub <8 x i16> zeroinitializer, [[VAL]] + ss = -ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = sub <4 x i32> zeroinitializer, [[VAL]] + si = -si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = sub <2 x i64> zeroinitializer, [[VAL]] + sl = -sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fsub <2 x double> , [[VAL]] + fd = -fd2; +} + +void test_preinc (void) +{ +// CHECK-LABEL: test_preinc + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL]], + ++sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL]], + ++uc2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL]], + ++ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL]], + ++us2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL]], + ++si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL]], + ++ui2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL]], + ++sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL]], + ++ul2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fadd <2 x double> [[VAL]], + ++fd2; +} + +void test_postinc (void) +{ +// CHECK-LABEL: test_postinc + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL]], + sc2++; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL]], + uc2++; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL]], + ss2++; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL]], + us2++; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL]], + si2++; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL]], + ui2++; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL]], + sl2++; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL]], + ul2++; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fadd <2 x double> [[VAL]], + fd2++; +} + +void test_predec (void) +{ +// CHECK-LABEL: test_predec + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL]], + --sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL]], + --uc2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL]], + --ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL]], + --us2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL]], + --si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL]], + --ui2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL]], + --sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL]], + --ul2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fadd <2 x double> [[VAL]], + --fd2; +} + +void test_postdec (void) +{ +// CHECK-LABEL: test_postdec + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL]], + sc2--; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL]], + uc2--; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL]], + ss2--; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL]], + us2--; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL]], + si2--; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL]], + ui2--; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL]], + sl2--; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL]], + ul2--; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fadd <2 x double> [[VAL]], + fd2--; +} + +void test_add (void) +{ +// CHECK-LABEL: test_add + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL2]], [[VAL1]] + sc = sc + sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL2]], [[VAL1]] + sc = sc + bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL2]], [[VAL1]] + sc = bc + sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL2]], [[VAL1]] + uc = uc + uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL2]], [[VAL1]] + uc = uc + bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = add <16 x i8> [[VAL2]], [[VAL1]] + uc = bc + uc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL2]], [[VAL1]] + ss = ss + ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL2]], [[VAL1]] + ss = ss + bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL2]], [[VAL1]] + ss = bs + ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL2]], [[VAL1]] + us = us + us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL2]], [[VAL1]] + us = us + bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = add <8 x i16> [[VAL2]], [[VAL1]] + us = bs + us2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL2]], [[VAL1]] + si = si + si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL2]], [[VAL1]] + si = si + bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL2]], [[VAL1]] + si = bi + si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL2]], [[VAL1]] + ui = ui + ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL2]], [[VAL1]] + ui = ui + bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = add <4 x i32> [[VAL2]], [[VAL1]] + ui = bi + ui2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL2]], [[VAL1]] + sl = sl + sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL2]], [[VAL1]] + sl = sl + bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL2]], [[VAL1]] + sl = bl + sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL2]], [[VAL1]] + ul = ul + ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL2]], [[VAL1]] + ul = ul + bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = add <2 x i64> [[VAL2]], [[VAL1]] + ul = bl + ul2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fadd <2 x double> [[VAL1]], [[VAL2]] + fd = fd + fd2; +} + +void test_add_assign (void) +{ +// CHECK-LABEL: test_add_assign + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = add <16 x i8> [[VAL1]], [[VAL2]] + sc += sc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = add <16 x i8> [[VAL1]], [[VAL2]] + sc += bc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = add <16 x i8> [[VAL1]], [[VAL2]] + uc += uc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = add <16 x i8> [[VAL1]], [[VAL2]] + uc += bc2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = add <8 x i16> [[VAL1]], [[VAL2]] + ss += ss2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = add <8 x i16> [[VAL1]], [[VAL2]] + ss += bs2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = add <8 x i16> [[VAL1]], [[VAL2]] + us += us2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = add <8 x i16> [[VAL1]], [[VAL2]] + us += bs2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = add <4 x i32> [[VAL1]], [[VAL2]] + si += si2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = add <4 x i32> [[VAL1]], [[VAL2]] + si += bi2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = add <4 x i32> [[VAL1]], [[VAL2]] + ui += ui2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = add <4 x i32> [[VAL1]], [[VAL2]] + ui += bi2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = add <2 x i64> [[VAL1]], [[VAL2]] + sl += sl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = add <2 x i64> [[VAL1]], [[VAL2]] + sl += bl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = add <2 x i64> [[VAL1]], [[VAL2]] + ul += ul2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = add <2 x i64> [[VAL1]], [[VAL2]] + ul += bl2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: %{{.*}} = fadd <2 x double> [[VAL2]], [[VAL1]] + fd += fd2; +} + +void test_sub (void) +{ +// CHECK-LABEL: test_sub + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + sc = sc - sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + sc = sc - bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + sc = bc - sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + uc = uc - uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + uc = uc - bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + uc = bc - uc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + ss = ss - ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + ss = ss - bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + ss = bs - ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + us = us - us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + us = us - bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + us = bs - us2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + si = si - si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + si = si - bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + si = bi - si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + ui = ui - ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + ui = ui - bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + ui = bi - ui2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + sl = sl - sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + sl = sl - bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + sl = bl - sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + ul = ul - ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + ul = ul - bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + ul = bl - ul2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fsub <2 x double> [[VAL1]], [[VAL2]] + fd = fd - fd2; +} + +void test_sub_assign (void) +{ +// CHECK-LABEL: test_sub_assign + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + sc -= sc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + sc -= bc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + uc -= uc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = sub <16 x i8> [[VAL1]], [[VAL2]] + uc -= bc2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + ss -= ss2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + ss -= bs2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + us -= us2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = sub <8 x i16> [[VAL1]], [[VAL2]] + us -= bs2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + si -= si2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + si -= bi2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + ui -= ui2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = sub <4 x i32> [[VAL1]], [[VAL2]] + ui -= bi2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + sl -= sl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + sl -= bl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + ul -= ul2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = sub <2 x i64> [[VAL1]], [[VAL2]] + ul -= bl2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: %{{.*}} = fsub <2 x double> [[VAL1]], [[VAL2]] + fd -= fd2; +} + +void test_mul (void) +{ +// CHECK-LABEL: test_mul + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = mul <16 x i8> [[VAL2]], [[VAL1]] + sc = sc * sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = mul <16 x i8> [[VAL2]], [[VAL1]] + uc = uc * uc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = mul <8 x i16> [[VAL2]], [[VAL1]] + ss = ss * ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = mul <8 x i16> [[VAL2]], [[VAL1]] + us = us * us2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = mul <4 x i32> [[VAL2]], [[VAL1]] + si = si * si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = mul <4 x i32> [[VAL2]], [[VAL1]] + ui = ui * ui2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = mul <2 x i64> [[VAL2]], [[VAL1]] + sl = sl * sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = mul <2 x i64> [[VAL2]], [[VAL1]] + ul = ul * ul2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fmul <2 x double> [[VAL1]], [[VAL2]] + fd = fd * fd2; +} + +void test_mul_assign (void) +{ +// CHECK-LABEL: test_mul_assign + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = mul <16 x i8> [[VAL1]], [[VAL2]] + sc *= sc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = mul <16 x i8> [[VAL1]], [[VAL2]] + uc *= uc2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = mul <8 x i16> [[VAL1]], [[VAL2]] + ss *= ss2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = mul <8 x i16> [[VAL1]], [[VAL2]] + us *= us2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = mul <4 x i32> [[VAL1]], [[VAL2]] + si *= si2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = mul <4 x i32> [[VAL1]], [[VAL2]] + ui *= ui2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = mul <2 x i64> [[VAL1]], [[VAL2]] + sl *= sl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = mul <2 x i64> [[VAL1]], [[VAL2]] + ul *= ul2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: %{{.*}} = fmul <2 x double> [[VAL2]], [[VAL1]] + fd *= fd2; +} + +void test_div (void) +{ +// CHECK-LABEL: test_div + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = sdiv <16 x i8> [[VAL1]], [[VAL2]] + sc = sc / sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = udiv <16 x i8> [[VAL1]], [[VAL2]] + uc = uc / uc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = sdiv <8 x i16> [[VAL1]], [[VAL2]] + ss = ss / ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = udiv <8 x i16> [[VAL1]], [[VAL2]] + us = us / us2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = sdiv <4 x i32> [[VAL1]], [[VAL2]] + si = si / si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = udiv <4 x i32> [[VAL1]], [[VAL2]] + ui = ui / ui2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = sdiv <2 x i64> [[VAL1]], [[VAL2]] + sl = sl / sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = udiv <2 x i64> [[VAL1]], [[VAL2]] + ul = ul / ul2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: %{{.*}} = fdiv <2 x double> [[VAL1]], [[VAL2]] + fd = fd / fd2; +} + +void test_div_assign (void) +{ +// CHECK-LABEL: test_div_assign + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = sdiv <16 x i8> [[VAL1]], [[VAL2]] + sc /= sc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = udiv <16 x i8> [[VAL1]], [[VAL2]] + uc /= uc2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = sdiv <8 x i16> [[VAL1]], [[VAL2]] + ss /= ss2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = udiv <8 x i16> [[VAL1]], [[VAL2]] + us /= us2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = sdiv <4 x i32> [[VAL1]], [[VAL2]] + si /= si2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = udiv <4 x i32> [[VAL1]], [[VAL2]] + ui /= ui2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = sdiv <2 x i64> [[VAL1]], [[VAL2]] + sl /= sl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = udiv <2 x i64> [[VAL1]], [[VAL2]] + ul /= ul2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: %{{.*}} = fdiv <2 x double> [[VAL1]], [[VAL2]] + fd /= fd2; +} + +void test_rem (void) +{ +// CHECK-LABEL: test_rem + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = srem <16 x i8> [[VAL1]], [[VAL2]] + sc = sc % sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = urem <16 x i8> [[VAL1]], [[VAL2]] + uc = uc % uc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = srem <8 x i16> [[VAL1]], [[VAL2]] + ss = ss % ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = urem <8 x i16> [[VAL1]], [[VAL2]] + us = us % us2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = srem <4 x i32> [[VAL1]], [[VAL2]] + si = si % si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = urem <4 x i32> [[VAL1]], [[VAL2]] + ui = ui % ui2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = srem <2 x i64> [[VAL1]], [[VAL2]] + sl = sl % sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = urem <2 x i64> [[VAL1]], [[VAL2]] + ul = ul % ul2; +} + +void test_rem_assign (void) +{ +// CHECK-LABEL: test_rem_assign + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = srem <16 x i8> [[VAL1]], [[VAL2]] + sc %= sc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = urem <16 x i8> [[VAL1]], [[VAL2]] + uc %= uc2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = srem <8 x i16> [[VAL1]], [[VAL2]] + ss %= ss2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = urem <8 x i16> [[VAL1]], [[VAL2]] + us %= us2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = srem <4 x i32> [[VAL1]], [[VAL2]] + si %= si2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = urem <4 x i32> [[VAL1]], [[VAL2]] + ui %= ui2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = srem <2 x i64> [[VAL1]], [[VAL2]] + sl %= sl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = urem <2 x i64> [[VAL1]], [[VAL2]] + ul %= ul2; +} + +void test_not (void) +{ +// CHECK-LABEL: test_not + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL]], + sc = ~sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL]], + uc = ~uc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL]], + bc = ~bc2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL]], + ss = ~ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL]], + us = ~us2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL]], + bs = ~bs2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL]], + si = ~si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL]], + ui = ~ui2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL]], + bi = ~bi2; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL]], + sl = ~sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL]], + ul = ~ul2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL]], + bl = ~bl2; +} + +void test_and (void) +{ +// CHECK-LABEL: test_and + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = and <16 x i8> [[VAL2]], [[VAL1]] + sc = sc & sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = and <16 x i8> [[VAL2]], [[VAL1]] + sc = sc & bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = and <16 x i8> [[VAL2]], [[VAL1]] + sc = bc & sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = and <16 x i8> [[VAL2]], [[VAL1]] + uc = uc & uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = and <16 x i8> [[VAL2]], [[VAL1]] + uc = uc & bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = and <16 x i8> [[VAL2]], [[VAL1]] + uc = bc & uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = and <16 x i8> [[VAL2]], [[VAL1]] + bc = bc & bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = and <8 x i16> [[VAL2]], [[VAL1]] + ss = ss & ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = and <8 x i16> [[VAL2]], [[VAL1]] + ss = ss & bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = and <8 x i16> [[VAL2]], [[VAL1]] + ss = bs & ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = and <8 x i16> [[VAL2]], [[VAL1]] + us = us & us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = and <8 x i16> [[VAL2]], [[VAL1]] + us = us & bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = and <8 x i16> [[VAL2]], [[VAL1]] + us = bs & us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = and <8 x i16> [[VAL2]], [[VAL1]] + bs = bs & bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = and <4 x i32> [[VAL2]], [[VAL1]] + si = si & si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = and <4 x i32> [[VAL2]], [[VAL1]] + si = si & bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = and <4 x i32> [[VAL2]], [[VAL1]] + si = bi & si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = and <4 x i32> [[VAL2]], [[VAL1]] + ui = ui & ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = and <4 x i32> [[VAL2]], [[VAL1]] + ui = ui & bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = and <4 x i32> [[VAL2]], [[VAL1]] + ui = bi & ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = and <4 x i32> [[VAL2]], [[VAL1]] + bi = bi & bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = and <2 x i64> [[VAL2]], [[VAL1]] + sl = sl & sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = and <2 x i64> [[VAL2]], [[VAL1]] + sl = sl & bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = and <2 x i64> [[VAL2]], [[VAL1]] + sl = bl & sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = and <2 x i64> [[VAL2]], [[VAL1]] + ul = ul & ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = and <2 x i64> [[VAL2]], [[VAL1]] + ul = ul & bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = and <2 x i64> [[VAL2]], [[VAL1]] + ul = bl & ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = and <2 x i64> [[VAL2]], [[VAL1]] + bl = bl & bl2; +} + +void test_and_assign (void) +{ +// CHECK-LABEL: test_and_assign + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = and <16 x i8> [[VAL1]], [[VAL2]] + sc &= sc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = and <16 x i8> [[VAL1]], [[VAL2]] + sc &= bc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = and <16 x i8> [[VAL1]], [[VAL2]] + uc &= uc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = and <16 x i8> [[VAL1]], [[VAL2]] + uc &= bc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: %{{.*}} = and <16 x i8> [[VAL1]], [[VAL2]] + bc &= bc2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = and <8 x i16> [[VAL1]], [[VAL2]] + ss &= ss2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = and <8 x i16> [[VAL1]], [[VAL2]] + ss &= bs2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = and <8 x i16> [[VAL1]], [[VAL2]] + us &= us2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = and <8 x i16> [[VAL1]], [[VAL2]] + us &= bs2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: %{{.*}} = and <8 x i16> [[VAL1]], [[VAL2]] + bs &= bs2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = and <4 x i32> [[VAL1]], [[VAL2]] + si &= si2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = and <4 x i32> [[VAL1]], [[VAL2]] + si &= bi2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = and <4 x i32> [[VAL1]], [[VAL2]] + ui &= ui2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = and <4 x i32> [[VAL1]], [[VAL2]] + ui &= bi2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: %{{.*}} = and <4 x i32> [[VAL1]], [[VAL2]] + bi &= bi2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = and <2 x i64> [[VAL1]], [[VAL2]] + sl &= sl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = and <2 x i64> [[VAL1]], [[VAL2]] + sl &= bl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = and <2 x i64> [[VAL1]], [[VAL2]] + ul &= ul2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = and <2 x i64> [[VAL1]], [[VAL2]] + ul &= bl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: %{{.*}} = and <2 x i64> [[VAL1]], [[VAL2]] + bl &= bl2; +} + +void test_or (void) +{ +// CHECK-LABEL: test_or + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = or <16 x i8> [[VAL2]], [[VAL1]] + sc = sc | sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = or <16 x i8> [[VAL2]], [[VAL1]] + sc = sc | bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = or <16 x i8> [[VAL2]], [[VAL1]] + sc = bc | sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = or <16 x i8> [[VAL2]], [[VAL1]] + uc = uc | uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = or <16 x i8> [[VAL2]], [[VAL1]] + uc = uc | bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = or <16 x i8> [[VAL2]], [[VAL1]] + uc = bc | uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = or <16 x i8> [[VAL2]], [[VAL1]] + bc = bc | bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = or <8 x i16> [[VAL2]], [[VAL1]] + ss = ss | ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = or <8 x i16> [[VAL2]], [[VAL1]] + ss = ss | bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = or <8 x i16> [[VAL2]], [[VAL1]] + ss = bs | ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = or <8 x i16> [[VAL2]], [[VAL1]] + us = us | us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = or <8 x i16> [[VAL2]], [[VAL1]] + us = us | bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = or <8 x i16> [[VAL2]], [[VAL1]] + us = bs | us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = or <8 x i16> [[VAL2]], [[VAL1]] + bs = bs | bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = or <4 x i32> [[VAL2]], [[VAL1]] + si = si | si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = or <4 x i32> [[VAL2]], [[VAL1]] + si = si | bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = or <4 x i32> [[VAL2]], [[VAL1]] + si = bi | si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = or <4 x i32> [[VAL2]], [[VAL1]] + ui = ui | ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = or <4 x i32> [[VAL2]], [[VAL1]] + ui = ui | bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = or <4 x i32> [[VAL2]], [[VAL1]] + ui = bi | ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = or <4 x i32> [[VAL2]], [[VAL1]] + bi = bi | bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = or <2 x i64> [[VAL2]], [[VAL1]] + sl = sl | sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = or <2 x i64> [[VAL2]], [[VAL1]] + sl = sl | bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = or <2 x i64> [[VAL2]], [[VAL1]] + sl = bl | sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = or <2 x i64> [[VAL2]], [[VAL1]] + ul = ul | ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = or <2 x i64> [[VAL2]], [[VAL1]] + ul = ul | bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = or <2 x i64> [[VAL2]], [[VAL1]] + ul = bl | ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = or <2 x i64> [[VAL2]], [[VAL1]] + bl = bl | bl2; +} + +void test_or_assign (void) +{ +// CHECK-LABEL: test_or_assign + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = or <16 x i8> [[VAL1]], [[VAL2]] + sc |= sc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = or <16 x i8> [[VAL1]], [[VAL2]] + sc |= bc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = or <16 x i8> [[VAL1]], [[VAL2]] + uc |= uc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = or <16 x i8> [[VAL1]], [[VAL2]] + uc |= bc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: %{{.*}} = or <16 x i8> [[VAL1]], [[VAL2]] + bc |= bc2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = or <8 x i16> [[VAL1]], [[VAL2]] + ss |= ss2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = or <8 x i16> [[VAL1]], [[VAL2]] + ss |= bs2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = or <8 x i16> [[VAL1]], [[VAL2]] + us |= us2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = or <8 x i16> [[VAL1]], [[VAL2]] + us |= bs2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: %{{.*}} = or <8 x i16> [[VAL1]], [[VAL2]] + bs |= bs2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = or <4 x i32> [[VAL1]], [[VAL2]] + si |= si2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = or <4 x i32> [[VAL1]], [[VAL2]] + si |= bi2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = or <4 x i32> [[VAL1]], [[VAL2]] + ui |= ui2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = or <4 x i32> [[VAL1]], [[VAL2]] + ui |= bi2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: %{{.*}} = or <4 x i32> [[VAL1]], [[VAL2]] + bi |= bi2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = or <2 x i64> [[VAL1]], [[VAL2]] + sl |= sl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = or <2 x i64> [[VAL1]], [[VAL2]] + sl |= bl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = or <2 x i64> [[VAL1]], [[VAL2]] + ul |= ul2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = or <2 x i64> [[VAL1]], [[VAL2]] + ul |= bl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: %{{.*}} = or <2 x i64> [[VAL1]], [[VAL2]] + bl |= bl2; +} + +void test_xor (void) +{ +// CHECK-LABEL: test_xor + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL1]], [[VAL2]] + sc = sc ^ sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL1]], [[VAL2]] + sc = sc ^ bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL1]], [[VAL2]] + sc = bc ^ sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL1]], [[VAL2]] + uc = uc ^ uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL1]], [[VAL2]] + uc = uc ^ bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL1]], [[VAL2]] + uc = bc ^ uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: %{{.*}} = xor <16 x i8> [[VAL1]], [[VAL2]] + bc = bc ^ bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL1]], [[VAL2]] + ss = ss ^ ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL1]], [[VAL2]] + ss = ss ^ bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL1]], [[VAL2]] + ss = bs ^ ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL1]], [[VAL2]] + us = us ^ us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL1]], [[VAL2]] + us = us ^ bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL1]], [[VAL2]] + us = bs ^ us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: %{{.*}} = xor <8 x i16> [[VAL1]], [[VAL2]] + bs = bs ^ bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL1]], [[VAL2]] + si = si ^ si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL1]], [[VAL2]] + si = si ^ bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL1]], [[VAL2]] + si = bi ^ si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL1]], [[VAL2]] + ui = ui ^ ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL1]], [[VAL2]] + ui = ui ^ bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL1]], [[VAL2]] + ui = bi ^ ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: %{{.*}} = xor <4 x i32> [[VAL1]], [[VAL2]] + bi = bi ^ bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL1]], [[VAL2]] + sl = sl ^ sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL1]], [[VAL2]] + sl = sl ^ bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL1]], [[VAL2]] + sl = bl ^ sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL1]], [[VAL2]] + ul = ul ^ ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL1]], [[VAL2]] + ul = ul ^ bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL1]], [[VAL2]] + ul = bl ^ ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: %{{.*}} = xor <2 x i64> [[VAL1]], [[VAL2]] + bl = bl ^ bl2; +} + +void test_xor_assign (void) +{ +// CHECK-LABEL: test_xor_assign + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = xor <16 x i8> [[VAL2]], [[VAL1]] + sc ^= sc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = xor <16 x i8> [[VAL2]], [[VAL1]] + sc ^= bc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = xor <16 x i8> [[VAL2]], [[VAL1]] + uc ^= uc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = xor <16 x i8> [[VAL2]], [[VAL1]] + uc ^= bc2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: %{{.*}} = xor <16 x i8> [[VAL2]], [[VAL1]] + bc ^= bc2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = xor <8 x i16> [[VAL2]], [[VAL1]] + ss ^= ss2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = xor <8 x i16> [[VAL2]], [[VAL1]] + ss ^= bs2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = xor <8 x i16> [[VAL2]], [[VAL1]] + us ^= us2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = xor <8 x i16> [[VAL2]], [[VAL1]] + us ^= bs2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: %{{.*}} = xor <8 x i16> [[VAL2]], [[VAL1]] + bs ^= bs2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = xor <4 x i32> [[VAL2]], [[VAL1]] + si ^= si2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = xor <4 x i32> [[VAL2]], [[VAL1]] + si ^= bi2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = xor <4 x i32> [[VAL2]], [[VAL1]] + ui ^= ui2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = xor <4 x i32> [[VAL2]], [[VAL1]] + ui ^= bi2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: %{{.*}} = xor <4 x i32> [[VAL2]], [[VAL1]] + bi ^= bi2; + +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = xor <2 x i64> [[VAL2]], [[VAL1]] + sl ^= sl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = xor <2 x i64> [[VAL2]], [[VAL1]] + sl ^= bl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = xor <2 x i64> [[VAL2]], [[VAL1]] + ul ^= ul2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = xor <2 x i64> [[VAL2]], [[VAL1]] + ul ^= bl2; +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: %{{.*}} = xor <2 x i64> [[VAL2]], [[VAL1]] + bl ^= bl2; +} + +void test_sl (void) +{ +// CHECK-LABEL: test_sl + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + sc = sc << sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + sc = sc << uc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <16 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <16 x i32> [[T2]], <16 x i32> undef, <16 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = trunc <16 x i32> [[T3]] to <16 x i8> +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + sc = sc << cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], + sc = sc << 5; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + uc = uc << sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + uc = uc << uc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <16 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <16 x i32> [[T2]], <16 x i32> undef, <16 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = trunc <16 x i32> [[T3]] to <16 x i8> +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + uc = uc << cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], + uc = uc << 5; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + ss = ss << ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + ss = ss << us2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <8 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <8 x i32> [[T2]], <8 x i32> undef, <8 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = trunc <8 x i32> [[T3]] to <8 x i16> +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + ss = ss << cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], + ss = ss << 5; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + us = us << ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + us = us << us2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <8 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <8 x i32> [[T2]], <8 x i32> undef, <8 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = trunc <8 x i32> [[T3]] to <8 x i16> +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + us = us << cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], + us = us << 5; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + si = si << si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + si = si << ui2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T3:%[^ ]+]] = insertelement <4 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[CNT:%[^ ]+]] = shufflevector <4 x i32> [[T3]], <4 x i32> undef, <4 x i32> zeroinitializer +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + si = si << cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], + si = si << 5; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + ui = ui << si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + ui = ui << ui2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T3:%[^ ]+]] = insertelement <4 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[CNT:%[^ ]+]] = shufflevector <4 x i32> [[T3]], <4 x i32> undef, <4 x i32> zeroinitializer +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + ui = ui << cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], + ui = ui << 5; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + sl = sl << sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + sl = sl << ul2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <2 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = zext <2 x i32> [[T3]] to <2 x i64> +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + sl = sl << cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], + sl = sl << 5; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + ul = ul << sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + ul = ul << ul2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <2 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = zext <2 x i32> [[T3]] to <2 x i64> +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + ul = ul << cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], + ul = ul << 5; +} + +void test_sl_assign (void) +{ +// CHECK-LABEL: test_sl_assign + +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + sc <<= sc2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + sc <<= uc2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <16 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <16 x i32> [[T2]], <16 x i32> undef, <16 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[CNT:%[^ ]+]] = trunc <16 x i32> [[T3]] to <16 x i8> +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + sc <<= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], + sc <<= 5; +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + uc <<= sc2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + uc <<= uc2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <16 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <16 x i32> [[T2]], <16 x i32> undef, <16 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[CNT:%[^ ]+]] = trunc <16 x i32> [[T3]] to <16 x i8> +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], [[CNT]] + uc <<= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = shl <16 x i8> [[VAL]], + uc <<= 5; + +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + ss <<= ss2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + ss <<= us2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <8 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <8 x i32> [[T2]], <8 x i32> undef, <8 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[CNT:%[^ ]+]] = trunc <8 x i32> [[T3]] to <8 x i16> +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + ss <<= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], + ss <<= 5; +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + us <<= ss2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + us <<= us2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <8 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <8 x i32> [[T2]], <8 x i32> undef, <8 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[CNT:%[^ ]+]] = trunc <8 x i32> [[T3]] to <8 x i16> +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], [[CNT]] + us <<= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = shl <8 x i16> [[VAL]], + us <<= 5; + +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + si <<= si2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + si <<= ui2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T3:%[^ ]+]] = insertelement <4 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[CNT:%[^ ]+]] = shufflevector <4 x i32> [[T3]], <4 x i32> undef, <4 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + si <<= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], + si <<= 5; +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + ui <<= si2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + ui <<= ui2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T3:%[^ ]+]] = insertelement <4 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[CNT:%[^ ]+]] = shufflevector <4 x i32> [[T3]], <4 x i32> undef, <4 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], [[CNT]] + ui <<= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = shl <4 x i32> [[VAL]], + ui <<= 5; + +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + sl <<= sl2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + sl <<= ul2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <2 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[CNT:%[^ ]+]] = zext <2 x i32> [[T3]] to <2 x i64> +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + sl <<= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], + sl <<= 5; +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + ul <<= sl2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + ul <<= ul2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <2 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[CNT:%[^ ]+]] = zext <2 x i32> [[T3]] to <2 x i64> +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], [[CNT]] + ul <<= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = shl <2 x i64> [[VAL]], + ul <<= 5; +} + +void test_sr (void) +{ +// CHECK-LABEL: test_sr + +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = ashr <16 x i8> [[VAL]], [[CNT]] + sc = sc >> sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = ashr <16 x i8> [[VAL]], [[CNT]] + sc = sc >> uc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <16 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <16 x i32> [[T2]], <16 x i32> undef, <16 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = trunc <16 x i32> [[T3]] to <16 x i8> +// CHECK: %{{.*}} = ashr <16 x i8> [[VAL]], [[CNT]] + sc = sc >> cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = ashr <16 x i8> [[VAL]], + sc = sc >> 5; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: %{{.*}} = lshr <16 x i8> [[VAL]], [[CNT]] + uc = uc >> sc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: %{{.*}} = lshr <16 x i8> [[VAL]], [[CNT]] + uc = uc >> uc2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <16 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <16 x i32> [[T2]], <16 x i32> undef, <16 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = trunc <16 x i32> [[T3]] to <16 x i8> +// CHECK: %{{.*}} = lshr <16 x i8> [[VAL]], [[CNT]] + uc = uc >> cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = lshr <16 x i8> [[VAL]], + uc = uc >> 5; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = ashr <8 x i16> [[VAL]], [[CNT]] + ss = ss >> ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = ashr <8 x i16> [[VAL]], [[CNT]] + ss = ss >> us2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <8 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <8 x i32> [[T2]], <8 x i32> undef, <8 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = trunc <8 x i32> [[T3]] to <8 x i16> +// CHECK: %{{.*}} = ashr <8 x i16> [[VAL]], [[CNT]] + ss = ss >> cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = ashr <8 x i16> [[VAL]], + ss = ss >> 5; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: %{{.*}} = lshr <8 x i16> [[VAL]], [[CNT]] + us = us >> ss2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: %{{.*}} = lshr <8 x i16> [[VAL]], [[CNT]] + us = us >> us2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <8 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <8 x i32> [[T2]], <8 x i32> undef, <8 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = trunc <8 x i32> [[T3]] to <8 x i16> +// CHECK: %{{.*}} = lshr <8 x i16> [[VAL]], [[CNT]] + us = us >> cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = lshr <8 x i16> [[VAL]], + us = us >> 5; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = ashr <4 x i32> [[VAL]], [[CNT]] + si = si >> si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = ashr <4 x i32> [[VAL]], [[CNT]] + si = si >> ui2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T3:%[^ ]+]] = insertelement <4 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[CNT:%[^ ]+]] = shufflevector <4 x i32> [[T3]], <4 x i32> undef, <4 x i32> zeroinitializer +// CHECK: %{{.*}} = ashr <4 x i32> [[VAL]], [[CNT]] + si = si >> cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = ashr <4 x i32> [[VAL]], + si = si >> 5; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: %{{.*}} = lshr <4 x i32> [[VAL]], [[CNT]] + ui = ui >> si2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: %{{.*}} = lshr <4 x i32> [[VAL]], [[CNT]] + ui = ui >> ui2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T3:%[^ ]+]] = insertelement <4 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[CNT:%[^ ]+]] = shufflevector <4 x i32> [[T3]], <4 x i32> undef, <4 x i32> zeroinitializer +// CHECK: %{{.*}} = lshr <4 x i32> [[VAL]], [[CNT]] + ui = ui >> cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = lshr <4 x i32> [[VAL]], + ui = ui >> 5; + +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = ashr <2 x i64> [[VAL]], [[CNT]] + sl = sl >> sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = ashr <2 x i64> [[VAL]], [[CNT]] + sl = sl >> ul2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <2 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = zext <2 x i32> [[T3]] to <2 x i64> +// CHECK: %{{.*}} = ashr <2 x i64> [[VAL]], [[CNT]] + sl = sl >> cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = ashr <2 x i64> [[VAL]], + sl = sl >> 5; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: %{{.*}} = lshr <2 x i64> [[VAL]], [[CNT]] + ul = ul >> sl2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: %{{.*}} = lshr <2 x i64> [[VAL]], [[CNT]] + ul = ul >> ul2; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <2 x i32> zeroinitializer +// CHECK: [[CNT:%[^ ]+]] = zext <2 x i32> [[T3]] to <2 x i64> +// CHECK: %{{.*}} = lshr <2 x i64> [[VAL]], [[CNT]] + ul = ul >> cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = lshr <2 x i64> [[VAL]], + ul = ul >> 5; +} + +void test_sr_assign (void) +{ +// CHECK-LABEL: test_sr_assign + +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = ashr <16 x i8> [[VAL]], [[CNT]] + sc >>= sc2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = ashr <16 x i8> [[VAL]], [[CNT]] + sc >>= uc2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <16 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <16 x i32> [[T2]], <16 x i32> undef, <16 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[CNT:%[^ ]+]] = trunc <16 x i32> [[T3]] to <16 x i8> +// CHECK: %{{.*}} = ashr <16 x i8> [[VAL]], [[CNT]] + sc >>= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: %{{.*}} = ashr <16 x i8> [[VAL]], + sc >>= 5; +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = lshr <16 x i8> [[VAL]], [[CNT]] + uc >>= sc2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = lshr <16 x i8> [[VAL]], [[CNT]] + uc >>= uc2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <16 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <16 x i32> [[T2]], <16 x i32> undef, <16 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[CNT:%[^ ]+]] = trunc <16 x i32> [[T3]] to <16 x i8> +// CHECK: %{{.*}} = lshr <16 x i8> [[VAL]], [[CNT]] + uc >>= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: %{{.*}} = lshr <16 x i8> [[VAL]], + uc >>= 5; + +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = ashr <8 x i16> [[VAL]], [[CNT]] + ss >>= ss2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = ashr <8 x i16> [[VAL]], [[CNT]] + ss >>= us2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <8 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <8 x i32> [[T2]], <8 x i32> undef, <8 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[CNT:%[^ ]+]] = trunc <8 x i32> [[T3]] to <8 x i16> +// CHECK: %{{.*}} = ashr <8 x i16> [[VAL]], [[CNT]] + ss >>= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: %{{.*}} = ashr <8 x i16> [[VAL]], + ss >>= 5; +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = lshr <8 x i16> [[VAL]], [[CNT]] + us >>= ss2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = lshr <8 x i16> [[VAL]], [[CNT]] + us >>= us2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <8 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <8 x i32> [[T2]], <8 x i32> undef, <8 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[CNT:%[^ ]+]] = trunc <8 x i32> [[T3]] to <8 x i16> +// CHECK: %{{.*}} = lshr <8 x i16> [[VAL]], [[CNT]] + us >>= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: %{{.*}} = lshr <8 x i16> [[VAL]], + us >>= 5; + +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = ashr <4 x i32> [[VAL]], [[CNT]] + si >>= si2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = ashr <4 x i32> [[VAL]], [[CNT]] + si >>= ui2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T3:%[^ ]+]] = insertelement <4 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[CNT:%[^ ]+]] = shufflevector <4 x i32> [[T3]], <4 x i32> undef, <4 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = ashr <4 x i32> [[VAL]], [[CNT]] + si >>= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: %{{.*}} = ashr <4 x i32> [[VAL]], + si >>= 5; +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = lshr <4 x i32> [[VAL]], [[CNT]] + ui >>= si2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = lshr <4 x i32> [[VAL]], [[CNT]] + ui >>= ui2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T3:%[^ ]+]] = insertelement <4 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[CNT:%[^ ]+]] = shufflevector <4 x i32> [[T3]], <4 x i32> undef, <4 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = lshr <4 x i32> [[VAL]], [[CNT]] + ui >>= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: %{{.*}} = lshr <4 x i32> [[VAL]], + ui >>= 5; + +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = ashr <2 x i64> [[VAL]], [[CNT]] + sl >>= sl2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = ashr <2 x i64> [[VAL]], [[CNT]] + sl >>= ul2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <2 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[CNT:%[^ ]+]] = zext <2 x i32> [[T3]] to <2 x i64> +// CHECK: %{{.*}} = ashr <2 x i64> [[VAL]], [[CNT]] + sl >>= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: %{{.*}} = ashr <2 x i64> [[VAL]], + sl >>= 5; +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = lshr <2 x i64> [[VAL]], [[CNT]] + ul >>= sl2; +// CHECK: [[CNT:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = lshr <2 x i64> [[VAL]], [[CNT]] + ul >>= ul2; +// CHECK: [[T1:%[^ ]+]] = load volatile i32, i32* @cnt +// CHECK: [[T2:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[T1]], i32 0 +// CHECK: [[T3:%[^ ]+]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <2 x i32> zeroinitializer +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[CNT:%[^ ]+]] = zext <2 x i32> [[T3]] to <2 x i64> +// CHECK: %{{.*}} = lshr <2 x i64> [[VAL]], [[CNT]] + ul >>= cnt; +// CHECK: [[VAL:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: %{{.*}} = lshr <2 x i64> [[VAL]], + ul >>= 5; +} + + +void test_cmpeq (void) +{ +// CHECK-LABEL: test_cmpeq + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = sc == sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = sc == bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc == sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = uc == uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = uc == bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc == uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc == bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = ss == ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = ss == bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs == ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = us == us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = us == bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs == us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs == bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = si == si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = si == bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi == si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = ui == ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = ui == bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi == ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi == bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = sl == sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = sl == bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl == sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = ul == ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = ul == bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl == ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp eq <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl == bl2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[CMP:%[^ ]+]] = fcmp oeq <2 x double> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = fd == fd2; +} + +void test_cmpne (void) +{ +// CHECK-LABEL: test_cmpne + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = sc != sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = sc != bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc != sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = uc != uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = uc != bc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc != uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc != bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = ss != ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = ss != bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs != ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = us != us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = us != bs2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs != us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs != bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = si != si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = si != bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi != si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = ui != ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = ui != bi2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi != ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi != bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = sl != sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = sl != bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl != sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = ul != ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = ul != bl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl != ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp ne <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl != bl2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[CMP:%[^ ]+]] = fcmp une <2 x double> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = fd != fd2; +} + +void test_cmpge (void) +{ +// CHECK-LABEL: test_cmpge + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[CMP:%[^ ]+]] = icmp sge <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = sc >= sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[CMP:%[^ ]+]] = icmp uge <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = uc >= uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp uge <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc >= bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[CMP:%[^ ]+]] = icmp sge <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = ss >= ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[CMP:%[^ ]+]] = icmp uge <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = us >= us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp uge <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs >= bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[CMP:%[^ ]+]] = icmp sge <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = si >= si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[CMP:%[^ ]+]] = icmp uge <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = ui >= ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp uge <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi >= bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[CMP:%[^ ]+]] = icmp sge <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = sl >= sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[CMP:%[^ ]+]] = icmp uge <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = ul >= ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp uge <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl >= bl2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[CMP:%[^ ]+]] = fcmp oge <2 x double> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = fd >= fd2; +} + +void test_cmpgt (void) +{ +// CHECK-LABEL: test_cmpgt + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[CMP:%[^ ]+]] = icmp sgt <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = sc > sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ugt <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = uc > uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ugt <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc > bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[CMP:%[^ ]+]] = icmp sgt <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = ss > ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[CMP:%[^ ]+]] = icmp ugt <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = us > us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp ugt <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs > bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[CMP:%[^ ]+]] = icmp sgt <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = si > si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[CMP:%[^ ]+]] = icmp ugt <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = ui > ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp ugt <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi > bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[CMP:%[^ ]+]] = icmp sgt <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = sl > sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[CMP:%[^ ]+]] = icmp ugt <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = ul > ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp ugt <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl > bl2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[CMP:%[^ ]+]] = fcmp ogt <2 x double> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = fd > fd2; +} + +void test_cmple (void) +{ +// CHECK-LABEL: test_cmple + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[CMP:%[^ ]+]] = icmp sle <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = sc <= sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ule <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = uc <= uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ule <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc <= bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[CMP:%[^ ]+]] = icmp sle <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = ss <= ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[CMP:%[^ ]+]] = icmp ule <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = us <= us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp ule <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs <= bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[CMP:%[^ ]+]] = icmp sle <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = si <= si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[CMP:%[^ ]+]] = icmp ule <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = ui <= ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp ule <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi <= bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[CMP:%[^ ]+]] = icmp sle <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = sl <= sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[CMP:%[^ ]+]] = icmp ule <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = ul <= ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp ule <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl <= bl2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[CMP:%[^ ]+]] = fcmp ole <2 x double> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = fd <= fd2; +} + +void test_cmplt (void) +{ +// CHECK-LABEL: test_cmplt + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @sc2 +// CHECK: [[CMP:%[^ ]+]] = icmp slt <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = sc < sc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @uc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ult <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = uc < uc2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc +// CHECK: [[VAL2:%[^ ]+]] = load volatile <16 x i8>, <16 x i8>* @bc2 +// CHECK: [[CMP:%[^ ]+]] = icmp ult <16 x i8> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <16 x i1> [[CMP]] to <16 x i8> + bc = bc < bc2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @ss2 +// CHECK: [[CMP:%[^ ]+]] = icmp slt <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = ss < ss2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @us2 +// CHECK: [[CMP:%[^ ]+]] = icmp ult <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = us < us2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs +// CHECK: [[VAL2:%[^ ]+]] = load volatile <8 x i16>, <8 x i16>* @bs2 +// CHECK: [[CMP:%[^ ]+]] = icmp ult <8 x i16> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <8 x i1> [[CMP]] to <8 x i16> + bs = bs < bs2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @si2 +// CHECK: [[CMP:%[^ ]+]] = icmp slt <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = si < si2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @ui2 +// CHECK: [[CMP:%[^ ]+]] = icmp ult <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = ui < ui2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi +// CHECK: [[VAL2:%[^ ]+]] = load volatile <4 x i32>, <4 x i32>* @bi2 +// CHECK: [[CMP:%[^ ]+]] = icmp ult <4 x i32> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <4 x i1> [[CMP]] to <4 x i32> + bi = bi < bi2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @sl2 +// CHECK: [[CMP:%[^ ]+]] = icmp slt <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = sl < sl2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @ul2 +// CHECK: [[CMP:%[^ ]+]] = icmp ult <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = ul < ul2; +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x i64>, <2 x i64>* @bl2 +// CHECK: [[CMP:%[^ ]+]] = icmp ult <2 x i64> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = bl < bl2; + +// CHECK: [[VAL1:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd +// CHECK: [[VAL2:%[^ ]+]] = load volatile <2 x double>, <2 x double>* @fd2 +// CHECK: [[CMP:%[^ ]+]] = fcmp olt <2 x double> [[VAL1]], [[VAL2]] +// CHECK: %{{.*}} = sext <2 x i1> [[CMP]] to <2 x i64> + bl = fd < fd2; +} + Index: test/Preprocessor/predefined-arch-macros.c =================================================================== --- test/Preprocessor/predefined-arch-macros.c +++ test/Preprocessor/predefined-arch-macros.c @@ -1748,3 +1748,12 @@ // RUN: | FileCheck %s -check-prefix=CHECK_SYSTEMZ_HTM // // CHECK_SYSTEMZ_HTM: #define __HTM__ 1 +// +// RUN: %clang -fzvector -E -dM %s -o - 2>&1 \ +// RUN: -target s390x-unknown-linux \ +// RUN: | FileCheck %s -check-prefix=CHECK_SYSTEMZ_ZVECTOR +// RUN: %clang -mzvector -E -dM %s -o - 2>&1 \ +// RUN: -target s390x-unknown-linux \ +// RUN: | FileCheck %s -check-prefix=CHECK_SYSTEMZ_ZVECTOR +// +// CHECK_SYSTEMZ_ZVECTOR: #define __VEC__ 10301 Index: test/Sema/zvector.c =================================================================== --- test/Sema/zvector.c +++ test/Sema/zvector.c @@ -0,0 +1,1009 @@ +// RUN: %clang_cc1 -triple s390x-linux-gnu -fzvector \ +// RUN: -fno-lax-vector-conversions -W -Wall -Wconversion \ +// RUN: -Werror -fsyntax-only -verify %s + +vector signed char sc, sc2; +vector unsigned char uc, uc2; +vector bool char bc, bc2; + +vector signed short ss, ss2; +vector unsigned short us, us2; +vector bool short bs, bs2; + +vector signed int si, si2; +vector unsigned int ui, ui2; +vector bool int bi, bi2; + +vector signed long long sl, sl2; +vector unsigned long long ul, ul2; +vector bool long long bl, bl2; + +vector double fd, fd2; + +vector long ll; // expected-error {{cannot use 'long' with '__vector'}} +vector float ff; // expected-error {{cannot use 'float' with '__vector'}} + +signed char sc_scalar; +unsigned char uc_scalar; + +signed short ss_scalar; +unsigned short us_scalar; + +signed int si_scalar; +unsigned int ui_scalar; + +signed long sl_scalar; +unsigned long ul_scalar; + +double fd_scalar; + +void foo(void) +{ + // ------------------------------------------------------------------------- + // Test assignment. + // ------------------------------------------------------------------------- + + sc = sc2; + uc = uc2; + bc = bc2; + + ss = ss2; + us = us2; + bs = bs2; + + si = si2; + ui = ui2; + bi = bi2; + + sl = sl2; + ul = ul2; + bl = bl2; + fd = fd2; + + sc = uc2; // expected-error {{incompatible type}} + sc = bc2; // expected-error {{incompatible type}} + uc = sc2; // expected-error {{incompatible type}} + uc = bc2; // expected-error {{incompatible type}} + bc = sc2; // expected-error {{incompatible type}} + bc = uc2; // expected-error {{incompatible type}} + + sc = sc_scalar; // expected-error {{incompatible type}} + sc = uc_scalar; // expected-error {{incompatible type}} + uc = sc_scalar; // expected-error {{incompatible type}} + uc = uc_scalar; // expected-error {{incompatible type}} + bc = sc_scalar; // expected-error {{incompatible type}} + bc = uc_scalar; // expected-error {{incompatible type}} + + sc = ss2; // expected-error {{incompatible type}} + sc = si2; // expected-error {{incompatible type}} + sc = sl2; // expected-error {{incompatible type}} + sc = fd2; // expected-error {{incompatible type}} + + ss = sc2; // expected-error {{incompatible type}} + si = sc2; // expected-error {{incompatible type}} + sl = sc2; // expected-error {{incompatible type}} + fd = sc2; // expected-error {{incompatible type}} + + uc = us2; // expected-error {{incompatible type}} + uc = ui2; // expected-error {{incompatible type}} + uc = ul2; // expected-error {{incompatible type}} + uc = fd2; // expected-error {{incompatible type}} + + us = uc2; // expected-error {{incompatible type}} + ui = uc2; // expected-error {{incompatible type}} + ul = uc2; // expected-error {{incompatible type}} + fd = uc2; // expected-error {{incompatible type}} + + bc = us2; // expected-error {{incompatible type}} + bc = ui2; // expected-error {{incompatible type}} + bc = ul2; // expected-error {{incompatible type}} + bc = fd2; // expected-error {{incompatible type}} + + bs = bc2; // expected-error {{incompatible type}} + bi = bc2; // expected-error {{incompatible type}} + bl = bc2; // expected-error {{incompatible type}} + fd = bc2; // expected-error {{incompatible type}} + + // ------------------------------------------------------------------------- + // Test casts to same element width. + // ------------------------------------------------------------------------- + + sc = (vector signed char)bc2; + bc = (vector bool char)uc2; + uc = (vector unsigned char)sc2; + + ss = (vector signed short)bs2; + bs = (vector bool short)us2; + us = (vector unsigned short)ss2; + + si = (vector signed int)bi2; + bi = (vector bool int)ui2; + ui = (vector unsigned int)si2; + + sl = (vector signed long long)bl2; + bl = (vector bool long long)ul2; + ul = (vector unsigned long long)fd2; + fd = (vector double)sl2; + + // ------------------------------------------------------------------------- + // Test casts to different element width. + // ------------------------------------------------------------------------- + + sc = (vector signed char)bs2; + bc = (vector bool char)us2; + uc = (vector unsigned char)fd2; + + ss = (vector signed short)bi2; + bs = (vector bool short)ui2; + us = (vector unsigned short)fd2; + + si = (vector signed int)bl2; + bi = (vector bool int)ul2; + ui = (vector unsigned int)fd2; + + sl = (vector signed long long)bc2; + bl = (vector bool long long)uc2; + ul = (vector unsigned long long)sc2; + fd = (vector double)sc2; + + // ------------------------------------------------------------------------- + // Test ++. + // ------------------------------------------------------------------------- + + ++sc2; + ++uc2; + ++bc2; // expected-error {{cannot increment}} + + ++ss2; + ++us2; + ++bs2; // expected-error {{cannot increment}} + + ++si2; + ++ui2; + ++bi2; // expected-error {{cannot increment}} + + ++sl2; + ++ul2; + ++bl2; // expected-error {{cannot increment}} + + ++fd2; + + sc++; + uc++; + bc++; // expected-error {{cannot increment}} + + ss++; + us++; + bs++; // expected-error {{cannot increment}} + + si++; + ui++; + bi++; // expected-error {{cannot increment}} + + sl++; + ul++; + bl++; // expected-error {{cannot increment}} + + fd++; + + // ------------------------------------------------------------------------- + // Test --. + // ------------------------------------------------------------------------- + + --sc2; + --uc2; + --bc2; // expected-error {{cannot decrement}} + + --ss2; + --us2; + --bs2; // expected-error {{cannot decrement}} + + --si2; + --ui2; + --bi2; // expected-error {{cannot decrement}} + + --sl2; + --ul2; + --bl2; // expected-error {{cannot decrement}} + + --fd2; + + sc--; + uc--; + bc--; // expected-error {{cannot decrement}} + + ss--; + us--; + bs--; // expected-error {{cannot decrement}} + + si--; + ui--; + bi--; // expected-error {{cannot decrement}} + + sl--; + ul--; + bl--; // expected-error {{cannot decrement}} + + fd--; + + // ------------------------------------------------------------------------- + // Test unary +. + // ------------------------------------------------------------------------- + + sc = +sc2; + uc = +uc2; + bc = +bc2; // expected-error {{invalid argument type}} + + ss = +ss2; + us = +us2; + bs = +bs2; // expected-error {{invalid argument type}} + + si = +si2; + ui = +ui2; + bi = +bi2; // expected-error {{invalid argument type}} + + sl = +sl2; + ul = +ul2; + bl = +bl2; // expected-error {{invalid argument type}} + + fd = +fd2; + + sc = +si2; // expected-error {{assigning to}} + ui = +si2; // expected-error {{assigning to}} + ui = +bi2; // expected-error {{invalid argument type}} + + // ------------------------------------------------------------------------- + // Test unary -. + // ------------------------------------------------------------------------- + + sc = -sc2; + uc = -uc2; + bc = -bc2; // expected-error {{invalid argument type}} + + ss = -ss2; + us = -us2; + bs = -bs2; // expected-error {{invalid argument type}} + + si = -si2; + ui = -ui2; + bi = -bi2; // expected-error {{invalid argument type}} + + sl = -sl2; + ul = -ul2; + bl = -bl2; // expected-error {{invalid argument type}} + + fd = -fd2; + + sc = -si2; // expected-error {{assigning to}} + ui = -si2; // expected-error {{assigning to}} + ui = -bi2; // expected-error {{invalid argument type}} + + // ------------------------------------------------------------------------- + // Test ~. + // ------------------------------------------------------------------------- + + sc = ~sc2; + uc = ~uc2; + bc = ~bc2; + + ss = ~ss2; + us = ~us2; + bs = ~bs2; + + si = ~si2; + ui = ~ui2; + bi = ~bi2; + + sl = ~sl2; + ul = ~ul2; + bl = ~bl2; + + fd = ~fd2; // expected-error {{invalid argument}} + + sc = ~si2; // expected-error {{assigning to}} + ui = ~si2; // expected-error {{assigning to}} + ui = ~bi2; // expected-error {{assigning to}} + + // ------------------------------------------------------------------------- + // Test binary +. + // ------------------------------------------------------------------------- + + sc = sc + sc2; + sc = sc + uc2; // expected-error {{can't convert}} + sc = uc + sc2; // expected-error {{can't convert}} + sc = sc + bc2; + sc = bc + sc2; + + uc = uc + uc2; + uc = sc + uc2; // expected-error {{can't convert}} + uc = uc + sc2; // expected-error {{can't convert}} + uc = bc + uc2; + uc = uc + bc2; + + bc = bc + bc2; // expected-error {{invalid operands}} + bc = bc + uc2; // expected-error {{incompatible type}} + bc = uc + bc2; // expected-error {{incompatible type}} + bc = bc + sc2; // expected-error {{incompatible type}} + bc = sc + bc2; // expected-error {{incompatible type}} + + sc = sc + sc_scalar; // expected-error {{can't convert}} + sc = sc + uc_scalar; // expected-error {{can't convert}} + sc = sc_scalar + sc; // expected-error {{can't convert}} + sc = uc_scalar + sc; // expected-error {{can't convert}} + uc = uc + sc_scalar; // expected-error {{can't convert}} + uc = uc + uc_scalar; // expected-error {{can't convert}} + uc = sc_scalar + uc; // expected-error {{can't convert}} + uc = uc_scalar + uc; // expected-error {{can't convert}} + + ss = ss + ss2; + us = us + us2; + bs = bs + bs2; // expected-error {{invalid operands}} + + si = si + si2; + ui = ui + ui2; + bi = bi + bi2; // expected-error {{invalid operands}} + + sl = sl + sl2; + ul = ul + ul2; + bl = bl + bl2; // expected-error {{invalid operands}} + + fd = fd + fd2; + fd = fd + ul2; // expected-error {{can't convert}} + fd = sl + fd2; // expected-error {{can't convert}} + + sc += sc2; + sc += uc2; // expected-error {{can't convert}} + sc += bc2; + + uc += uc2; + uc += sc2; // expected-error {{can't convert}} + uc += bc2; + + bc += bc2; // expected-error {{invalid operands}} + bc += sc2; // expected-error {{can't convert}} + bc += uc2; // expected-error {{can't convert}} + + sc += ss2; // expected-error {{can't convert}} + sc += si2; // expected-error {{can't convert}} + sc += sl2; // expected-error {{can't convert}} + sc += fd2; // expected-error {{can't convert}} + + sc += sc_scalar; // expected-error {{can't convert}} + sc += uc_scalar; // expected-error {{can't convert}} + uc += sc_scalar; // expected-error {{can't convert}} + uc += uc_scalar; // expected-error {{can't convert}} + + ss += ss2; + us += us2; + bs += bs2; // expected-error {{invalid operands}} + + si += si2; + ui += ui2; + bi += bi2; // expected-error {{invalid operands}} + + sl += sl2; + ul += ul2; + bl += bl2; // expected-error {{invalid operands}} + + fd += fd2; + + // ------------------------------------------------------------------------- + // Test that binary + rules apply to binary - too. + // ------------------------------------------------------------------------- + + sc = sc - sc2; + uc = uc - uc2; + bc = bc - bc2; // expected-error {{invalid operands}} + + sc = uc - sc2; // expected-error {{can't convert}} + sc = sc - bc2; + uc = bc - uc2; + + sc -= sc2; + uc -= uc2; + bc -= bc2; // expected-error {{invalid operands}} + + sc -= uc2; // expected-error {{can't convert}} + uc -= bc2; + bc -= sc2; // expected-error {{can't convert}} + + ss -= ss2; + us -= us2; + bs -= bs2; // expected-error {{invalid operands}} + + si -= si2; + ui -= ui2; + bi -= bi2; // expected-error {{invalid operands}} + + sl -= sl2; + ul -= ul2; + bl -= bl2; // expected-error {{invalid operands}} + + fd -= fd2; + + // ------------------------------------------------------------------------- + // Test that binary + rules apply to * too. 64-bit integer multiplication + // is not required by the spec and so isn't tested here. + // ------------------------------------------------------------------------- + + sc = sc * sc2; + uc = uc * uc2; + bc = bc * bc2; // expected-error {{invalid operands}} + + sc = uc * sc2; // expected-error {{can't convert}} + sc = sc * bc2; // expected-error {{can't convert}} + uc = bc * uc2; // expected-error {{can't convert}} + + sc *= sc2; + uc *= uc2; + bc *= bc2; // expected-error {{invalid operands}} + + sc *= uc2; // expected-error {{can't convert}} + uc *= bc2; // expected-error {{can't convert}} + bc *= sc2; // expected-error {{can't convert}} + + ss *= ss2; + us *= us2; + bs *= bs2; // expected-error {{invalid operands}} + + si *= si2; + ui *= ui2; + bi *= bi2; // expected-error {{invalid operands}} + + sl *= sl2; + ul *= ul2; + bl *= bl2; // expected-error {{invalid operands}} + + fd *= fd2; + + // ------------------------------------------------------------------------- + // Test that * rules apply to / too. + // ------------------------------------------------------------------------- + + sc = sc / sc2; + uc = uc / uc2; + bc = bc / bc2; // expected-error {{invalid operands}} + + sc = uc / sc2; // expected-error {{can't convert}} + sc = sc / bc2; // expected-error {{can't convert}} + uc = bc / uc2; // expected-error {{can't convert}} + + sc /= sc2; + uc /= uc2; + bc /= bc2; // expected-error {{invalid operands}} + + sc /= uc2; // expected-error {{can't convert}} + uc /= bc2; // expected-error {{can't convert}} + bc /= sc2; // expected-error {{can't convert}} + + ss /= ss2; + us /= us2; + bs /= bs2; // expected-error {{invalid operands}} + + si /= si2; + ui /= ui2; + bi /= bi2; // expected-error {{invalid operands}} + + sl /= sl2; + ul /= ul2; + bl /= bl2; // expected-error {{invalid operands}} + + fd /= fd2; + + // ------------------------------------------------------------------------- + // Test that / rules apply to % too, except that doubles are not allowed. + // ------------------------------------------------------------------------- + + sc = sc % sc2; + uc = uc % uc2; + bc = bc % bc2; // expected-error {{invalid operands}} + + sc = uc % sc2; // expected-error {{can't convert}} + sc = sc % bc2; // expected-error {{can't convert}} + uc = bc % uc2; // expected-error {{can't convert}} + + sc %= sc2; + uc %= uc2; + bc %= bc2; // expected-error {{invalid operands}} + + sc %= uc2; // expected-error {{can't convert}} + uc %= bc2; // expected-error {{can't convert}} + bc %= sc2; // expected-error {{can't convert}} + + ss %= ss2; + us %= us2; + bs %= bs2; // expected-error {{invalid operands}} + + si %= si2; + ui %= ui2; + bi %= bi2; // expected-error {{invalid operands}} + + sl %= sl2; + ul %= ul2; + bl %= bl2; // expected-error {{invalid operands}} + + fd %= fd2; // expected-error {{invalid operands}} + + // ------------------------------------------------------------------------- + // Test &. + // ------------------------------------------------------------------------- + + sc = sc & sc2; + sc = sc & uc2; // expected-error {{can't convert}} + sc = uc & sc2; // expected-error {{can't convert}} + sc = sc & bc2; + sc = bc & sc2; + + uc = uc & uc2; + uc = sc & uc2; // expected-error {{can't convert}} + uc = uc & sc2; // expected-error {{can't convert}} + uc = bc & uc2; + uc = uc & bc2; + + bc = bc & bc2; + bc = bc & uc2; // expected-error {{incompatible type}} + bc = uc & bc2; // expected-error {{incompatible type}} + bc = bc & sc2; // expected-error {{incompatible type}} + bc = sc & bc2; // expected-error {{incompatible type}} + + fd = fd & fd2; // expected-error {{invalid operands}} + fd = bl & fd2; // expected-error {{invalid operands}} + fd = fd & bl2; // expected-error {{invalid operands}} + fd = fd & sl2; // expected-error {{invalid operands}} + fd = fd & ul2; // expected-error {{invalid operands}} + + sc &= sc2; + sc &= uc2; // expected-error {{can't convert}} + sc &= bc2; + + uc &= uc2; + uc &= sc2; // expected-error {{can't convert}} + uc &= bc2; + + bc &= bc2; + bc &= sc2; // expected-error {{can't convert}} + bc &= uc2; // expected-error {{can't convert}} + + sc &= ss2; // expected-error {{can't convert}} + sc &= si2; // expected-error {{can't convert}} + sc &= sl2; // expected-error {{can't convert}} + sc &= fd2; // expected-error {{invalid operands}} + + us &= bc2; // expected-error {{can't convert}} + ui &= bc2; // expected-error {{can't convert}} + ul &= bc2; // expected-error {{can't convert}} + fd &= bc2; // expected-error {{invalid operands}} + + ss &= ss2; + us &= us2; + bs &= bs2; + + si &= si2; + ui &= ui2; + bi &= bi2; + + sl &= sl2; + ul &= ul2; + bl &= bl2; + + // ------------------------------------------------------------------------- + // Test that & rules apply to | too. + // ------------------------------------------------------------------------- + + sc = sc | sc2; + sc = sc | uc2; // expected-error {{can't convert}} + sc = sc | bc2; + + uc = uc | uc2; + uc = sc | uc2; // expected-error {{can't convert}} + uc = bc | uc2; + + bc = bc | bc2; + bc = uc | bc2; // expected-error {{incompatible type}} + bc = bc | sc2; // expected-error {{incompatible type}} + + fd = fd | fd2; // expected-error {{invalid operands}} + fd = bl | fd2; // expected-error {{invalid operands}} + + ss |= ss2; + us |= us2; + bs |= bs2; + + si |= si2; + ui |= ui2; + bi |= bi2; + + sl |= sl2; + ul |= ul2; + bl |= bl2; + + fd |= bl2; // expected-error {{invalid operands}} + fd |= fd2; // expected-error {{invalid operands}} + + // ------------------------------------------------------------------------- + // Test that & rules apply to ^ too. + // ------------------------------------------------------------------------- + + sc = sc ^ sc2; + sc = sc ^ uc2; // expected-error {{can't convert}} + sc = sc ^ bc2; + + uc = uc ^ uc2; + uc = sc ^ uc2; // expected-error {{can't convert}} + uc = bc ^ uc2; + + bc = bc ^ bc2; + bc = uc ^ bc2; // expected-error {{incompatible type}} + bc = bc ^ sc2; // expected-error {{incompatible type}} + + fd = fd ^ fd2; // expected-error {{invalid operands}} + fd = bl ^ fd2; // expected-error {{invalid operands}} + + ss ^= ss2; + us ^= us2; + bs ^= bs2; + + si ^= si2; + ui ^= ui2; + bi ^= bi2; + + sl ^= sl2; + ul ^= ul2; + bl ^= bl2; + + fd ^= bl2; // expected-error {{invalid operands}} + fd ^= fd2; // expected-error {{invalid operands}} + + // ------------------------------------------------------------------------- + // Test <<. + // ------------------------------------------------------------------------- + + sc = sc << sc2; + sc = sc << uc2; + sc = uc << sc2; // expected-error {{incompatible type}} + sc = sc << bc2; // expected-error {{invalid operands}} + sc = bc << sc2; // expected-error {{invalid operands}} + + uc = uc << uc2; + uc = sc << uc2; // expected-error {{assigning to}} + uc = uc << sc2; + uc = bc << uc2; // expected-error {{invalid operands}} + uc = uc << bc2; // expected-error {{invalid operands}} + + bc = bc << bc2; // expected-error {{invalid operands}} + bc = bc << uc2; // expected-error {{invalid operands}} + bc = uc << bc2; // expected-error {{invalid operands}} + bc = bc << sc2; // expected-error {{invalid operands}} + bc = sc << bc2; // expected-error {{invalid operands}} + + sc = sc << 1; + sc = sc << 1.0f; // expected-error {{integer is required}} + sc = sc << sc_scalar; + sc = sc << uc_scalar; + sc = sc << ss_scalar; + sc = sc << us_scalar; + sc = sc << si_scalar; + sc = sc << ui_scalar; + sc = sc << sl_scalar; + sc = sc << ul_scalar; + sc = sc_scalar << sc; // expected-error {{first operand is not a vector}} + sc = uc_scalar << sc; // expected-error {{first operand is not a vector}} + uc = uc << sc_scalar; + uc = uc << uc_scalar; + uc = sc_scalar << uc; // expected-error {{first operand is not a vector}} + uc = uc_scalar << uc; // expected-error {{first operand is not a vector}} + + ss = ss << ss2; + ss = ss << ss_scalar; + us = us << us2; + us = us << us_scalar; + bs = bs << bs2; // expected-error {{invalid operands}} + + si = si << si2; + si = si << si_scalar; + ui = ui << ui2; + ui = ui << ui_scalar; + bi = bi << bi2; // expected-error {{invalid operands}} + + sl = sl << sl2; + sl = sl << sl_scalar; + ul = ul << ul2; + ul = ul << ul_scalar; + bl = bl << bl2; // expected-error {{invalid operands}} + + fd = fd << fd2; // expected-error {{integer is required}} + fd = fd << ul2; // expected-error {{integer is required}} + fd = sl << fd2; // expected-error {{integer is required}} + + sc <<= sc2; + sc <<= uc2; + sc <<= bc2; // expected-error {{invalid operands}} + sc <<= sc_scalar; + + uc <<= uc2; + uc <<= sc2; + uc <<= bc2; // expected-error {{invalid operands}} + uc <<= uc_scalar; + + bc <<= bc2; // expected-error {{invalid operands}} + bc <<= sc2; // expected-error {{invalid operands}} + bc <<= uc2; // expected-error {{invalid operands}} + + sc <<= ss2; // expected-error {{vector operands do not have the same number of elements}} + sc <<= si2; // expected-error {{vector operands do not have the same number of elements}} + sc <<= sl2; // expected-error {{vector operands do not have the same number of elements}} + sc <<= fd2; // expected-error {{integer is required}} + + ss <<= ss2; + ss <<= ss_scalar; + us <<= us2; + us <<= us_scalar; + bs <<= bs2; // expected-error {{invalid operands}} + + si <<= si2; + si <<= si_scalar; + ui <<= ui2; + ui <<= ui_scalar; + bi <<= bi2; // expected-error {{invalid operands}} + + sl <<= sl2; + sl <<= sl_scalar; + ul <<= ul2; + ul <<= ul_scalar; + bl <<= bl2; // expected-error {{invalid operands}} + + fd <<= fd2; // expected-error {{integer is required}} + + // ------------------------------------------------------------------------- + // Test >>. + // ------------------------------------------------------------------------- + + sc = sc >> sc2; + sc = sc >> uc2; + sc = uc >> sc2; // expected-error {{incompatible type}} + sc = sc >> bc2; // expected-error {{invalid operands}} + sc = bc >> sc2; // expected-error {{invalid operands}} + + uc = uc >> uc2; + uc = sc >> uc2; // expected-error {{assigning to}} + uc = uc >> sc2; + uc = bc >> uc2; // expected-error {{invalid operands}} + uc = uc >> bc2; // expected-error {{invalid operands}} + + bc = bc >> bc2; // expected-error {{invalid operands}} + bc = bc >> uc2; // expected-error {{invalid operands}} + bc = uc >> bc2; // expected-error {{invalid operands}} + bc = bc >> sc2; // expected-error {{invalid operands}} + bc = sc >> bc2; // expected-error {{invalid operands}} + + sc = sc >> 1; + sc = sc >> 1.0f; // expected-error {{integer is required}} + sc = sc >> sc_scalar; + sc = sc >> uc_scalar; + sc = sc >> ss_scalar; + sc = sc >> us_scalar; + sc = sc >> si_scalar; + sc = sc >> ui_scalar; + sc = sc >> sl_scalar; + sc = sc >> ul_scalar; + sc = sc_scalar >> sc; // expected-error {{first operand is not a vector}} + sc = uc_scalar >> sc; // expected-error {{first operand is not a vector}} + uc = uc >> sc_scalar; + uc = uc >> uc_scalar; + uc = sc_scalar >> uc; // expected-error {{first operand is not a vector}} + uc = uc_scalar >> uc; // expected-error {{first operand is not a vector}} + + ss = ss >> ss2; + ss = ss >> ss_scalar; + us = us >> us2; + us = us >> us_scalar; + bs = bs >> bs2; // expected-error {{invalid operands}} + + si = si >> si2; + si = si >> si_scalar; + ui = ui >> ui2; + ui = ui >> ui_scalar; + bi = bi >> bi2; // expected-error {{invalid operands}} + + sl = sl >> sl2; + sl = sl >> sl_scalar; + ul = ul >> ul2; + ul = ul >> ul_scalar; + bl = bl >> bl2; // expected-error {{invalid operands}} + + fd = fd >> fd2; // expected-error {{integer is required}} + fd = fd >> ul2; // expected-error {{integer is required}} + fd = sl >> fd2; // expected-error {{integer is required}} + + sc >>= sc2; + sc >>= uc2; + sc >>= bc2; // expected-error {{invalid operands}} + sc >>= sc_scalar; + + uc >>= uc2; + uc >>= sc2; + uc >>= bc2; // expected-error {{invalid operands}} + uc >>= uc_scalar; + + bc >>= bc2; // expected-error {{invalid operands}} + bc >>= sc2; // expected-error {{invalid operands}} + bc >>= uc2; // expected-error {{invalid operands}} + + sc >>= ss2; // expected-error {{vector operands do not have the same number of elements}} + sc >>= si2; // expected-error {{vector operands do not have the same number of elements}} + sc >>= sl2; // expected-error {{vector operands do not have the same number of elements}} + sc >>= fd2; // expected-error {{integer is required}} + + ss >>= ss2; + ss >>= ss_scalar; + us >>= us2; + us >>= us_scalar; + bs >>= bs2; // expected-error {{invalid operands}} + + si >>= si2; + si >>= si_scalar; + ui >>= ui2; + ui >>= ui_scalar; + bi >>= bi2; // expected-error {{invalid operands}} + + sl >>= sl2; + sl >>= sl_scalar; + ul >>= ul2; + ul >>= ul_scalar; + bl >>= bl2; // expected-error {{invalid operands}} + + fd >>= fd2; // expected-error {{integer is required}} + + // ------------------------------------------------------------------------- + // Test ==. + // ------------------------------------------------------------------------- + + (void)(sc == sc2); + (void)(uc == uc2); + (void)(bc == bc2); + + (void)(sc == uc); // expected-error {{can't convert}} + (void)(sc == bc); + + (void)(uc == sc); // expected-error {{can't convert}} + (void)(uc == bc); + + (void)(bc == sc); + (void)(bc == uc); + + (void)(ss == ss2); + (void)(us == us2); + (void)(bs == bs2); + + (void)(si == si2); + (void)(ui == ui2); + (void)(bi == bi2); + + (void)(sl == sl2); + (void)(ul == ul2); + (void)(bl == bl2); + (void)(fd == fd2); + + (void)(fd == ul); // expected-error {{can't convert}} + (void)(ul == fd); // expected-error {{can't convert}} + + // ------------------------------------------------------------------------- + // Test that == rules apply to != too. + // ------------------------------------------------------------------------- + + (void)(sc != sc2); + (void)(uc != uc2); + (void)(bc != bc2); + + (void)(sc != uc); // expected-error {{can't convert}} + (void)(sc != bc); + + (void)(ss != ss2); + (void)(us != us2); + (void)(bs != bs2); + + (void)(si != si2); + (void)(ui != ui2); + (void)(bi != bi2); + + (void)(sl != sl2); + (void)(ul != ul2); + (void)(bl != bl2); + (void)(fd != fd2); + + // ------------------------------------------------------------------------- + // Test that == rules apply to <= too. + // ------------------------------------------------------------------------- + + (void)(sc <= sc2); + (void)(uc <= uc2); + (void)(bc <= bc2); + + (void)(sc <= uc); // expected-error {{can't convert}} + (void)(sc <= bc); + + (void)(ss <= ss2); + (void)(us <= us2); + (void)(bs <= bs2); + + (void)(si <= si2); + (void)(ui <= ui2); + (void)(bi <= bi2); + + (void)(sl <= sl2); + (void)(ul <= ul2); + (void)(bl <= bl2); + (void)(fd <= fd2); + + // ------------------------------------------------------------------------- + // Test that == rules apply to >= too. + // ------------------------------------------------------------------------- + + (void)(sc >= sc2); + (void)(uc >= uc2); + (void)(bc >= bc2); + + (void)(sc >= uc); // expected-error {{can't convert}} + (void)(sc >= bc); + + (void)(ss >= ss2); + (void)(us >= us2); + (void)(bs >= bs2); + + (void)(si >= si2); + (void)(ui >= ui2); + (void)(bi >= bi2); + + (void)(sl >= sl2); + (void)(ul >= ul2); + (void)(bl >= bl2); + (void)(fd >= fd2); + + // ------------------------------------------------------------------------- + // Test that == rules apply to < too. + // ------------------------------------------------------------------------- + + (void)(sc < sc2); + (void)(uc < uc2); + (void)(bc < bc2); + + (void)(sc < uc); // expected-error {{can't convert}} + (void)(sc < bc); + + (void)(ss < ss2); + (void)(us < us2); + (void)(bs < bs2); + + (void)(si < si2); + (void)(ui < ui2); + (void)(bi < bi2); + + (void)(sl < sl2); + (void)(ul < ul2); + (void)(bl < bl2); + (void)(fd < fd2); + + // ------------------------------------------------------------------------- + // Test that == rules apply to > too. + // ------------------------------------------------------------------------- + + (void)(sc > sc2); + (void)(uc > uc2); + (void)(bc > bc2); + + (void)(sc > uc); // expected-error {{can't convert}} + (void)(sc > bc); + + (void)(ss > ss2); + (void)(us > us2); + (void)(bs > bs2); + + (void)(si > si2); + (void)(ui > ui2); + (void)(bi > bi2); + + (void)(sl > sl2); + (void)(ul > ul2); + (void)(bl > bl2); + (void)(fd > fd2); +}